1/***********************license start***************
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
22 *
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
33 *
34 *
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
36 *
37 ***********************license end**************************************/
38
39
40
41
42
43
44/**
45 * @file
46 *
47 * Interface to the hardware Packet Input Processing unit.
48 *
49 * <hr>$Revision: 41586 $<hr>
50 */
51
52
53#ifndef __CVMX_PIP_H__
54#define __CVMX_PIP_H__
55
56#include "cvmx-wqe.h"
57#include "cvmx-fpa.h"
58#ifndef CVMX_DONT_INCLUDE_CONFIG
59#include "executive-config.h"
60#endif
61
62#ifdef __cplusplus
63extern "C" {
64#endif
65
66#define CVMX_PIP_NUM_INPUT_PORTS 40
67#define CVMX_PIP_NUM_WATCHERS 4
68
69
70
71
72
73
74
75//
76// Encodes the different error and exception codes
77//
78typedef enum
79{
80 CVMX_PIP_L4_NO_ERR = 0ull,
81 // 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header
82 CVMX_PIP_L4_MAL_ERR = 1ull,
83 // 2 = TCP/UDP checksum failure
84 CVMX_PIP_CHK_ERR = 2ull,
85 // 3 = TCP/UDP length check (TCP/UDP length does not match IP length)
86 CVMX_PIP_L4_LENGTH_ERR = 3ull,
87 // 4 = illegal TCP/UDP port (either source or dest port is zero)
88 CVMX_PIP_BAD_PRT_ERR = 4ull,
89 // 8 = TCP flags = FIN only
90 CVMX_PIP_TCP_FLG8_ERR = 8ull,
91 // 9 = TCP flags = 0
92 CVMX_PIP_TCP_FLG9_ERR = 9ull,
93 // 10 = TCP flags = FIN+RST+*
94 CVMX_PIP_TCP_FLG10_ERR = 10ull,
95 // 11 = TCP flags = SYN+URG+*
96 CVMX_PIP_TCP_FLG11_ERR = 11ull,
97 // 12 = TCP flags = SYN+RST+*
98 CVMX_PIP_TCP_FLG12_ERR = 12ull,
99 // 13 = TCP flags = SYN+FIN+*
100 CVMX_PIP_TCP_FLG13_ERR = 13ull
101} cvmx_pip_l4_err_t;
102
103typedef enum
104{
105
106 CVMX_PIP_IP_NO_ERR = 0ull,
107 // 1 = not IPv4 or IPv6
108 CVMX_PIP_NOT_IP = 1ull,
109 // 2 = IPv4 header checksum violation
110 CVMX_PIP_IPV4_HDR_CHK = 2ull,
111 // 3 = malformed (packet not long enough to cover IP hdr)
112 CVMX_PIP_IP_MAL_HDR = 3ull,
113 // 4 = malformed (packet not long enough to cover len in IP hdr)
114 CVMX_PIP_IP_MAL_PKT = 4ull,
115 // 5 = TTL / hop count equal zero
116 CVMX_PIP_TTL_HOP = 5ull,
117 // 6 = IPv4 options / IPv6 early extension headers
118 CVMX_PIP_OPTS = 6ull
119} cvmx_pip_ip_exc_t;
120
121
122/**
123 * NOTES
124 * late collision (data received before collision)
125 * late collisions cannot be detected by the receiver
126 * they would appear as JAM bits which would appear as bad FCS
127 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
128 */
129typedef enum
130{
131 /**
132 * No error
133 */
134 CVMX_PIP_RX_NO_ERR = 0ull,
135
136 CVMX_PIP_PARTIAL_ERR = 1ull, // RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate)
137 CVMX_PIP_JABBER_ERR = 2ull, // RGM+SPI 2 = receive packet too large and truncated
138 CVMX_PIP_OVER_FCS_ERR = 3ull, // RGM 3 = max frame error (pkt len > max frame len) (with FCS error)
139 CVMX_PIP_OVER_ERR = 4ull, // RGM+SPI 4 = max frame error (pkt len > max frame len)
140 CVMX_PIP_ALIGN_ERR = 5ull, // RGM 5 = nibble error (data not byte multiple - 100M and 10M only)
141 CVMX_PIP_UNDER_FCS_ERR = 6ull, // RGM 6 = min frame error (pkt len < min frame len) (with FCS error)
142 CVMX_PIP_GMX_FCS_ERR = 7ull, // RGM 7 = FCS error
143 CVMX_PIP_UNDER_ERR = 8ull, // RGM+SPI 8 = min frame error (pkt len < min frame len)
144 CVMX_PIP_EXTEND_ERR = 9ull, // RGM 9 = Frame carrier extend error
145 CVMX_PIP_LENGTH_ERR = 10ull, // RGM 10 = length mismatch (len did not match len in L2 length/type)
146 CVMX_PIP_DAT_ERR = 11ull, // RGM 11 = Frame error (some or all data bits marked err)
147 CVMX_PIP_DIP_ERR = 11ull, // SPI 11 = DIP4 error
148 CVMX_PIP_SKIP_ERR = 12ull, // RGM 12 = packet was not large enough to pass the skipper - no inspection could occur
149 CVMX_PIP_NIBBLE_ERR = 13ull, // RGM 13 = studder error (data not repeated - 100M and 10M only)
150 CVMX_PIP_PIP_FCS = 16L, // RGM+SPI 16 = FCS error
151 CVMX_PIP_PIP_SKIP_ERR = 17L, // RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur
152 CVMX_PIP_PIP_L2_MAL_HDR= 18L // RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr)
153 // NOTES
154 // xx = late collision (data received before collision)
155 // late collisions cannot be detected by the receiver
156 // they would appear as JAM bits which would appear as bad FCS
157 // or carrier extend error which is CVMX_PIP_EXTEND_ERR
158
159
160
161} cvmx_pip_rcv_err_t;
162
163/**
164 * This defines the err_code field errors in the work Q entry
165 */
166typedef union
167{
168 cvmx_pip_l4_err_t l4_err;
169 cvmx_pip_ip_exc_t ip_exc;
170 cvmx_pip_rcv_err_t rcv_err;
171} cvmx_pip_err_t;
172
173
174/**
175 * Status statistics for a port
176 */
177typedef struct
178{
179 uint32_t dropped_octets; /**< Inbound octets marked to be dropped by the IPD */
180 uint32_t dropped_packets; /**< Inbound packets marked to be dropped by the IPD */
181 uint32_t pci_raw_packets; /**< RAW PCI Packets received by PIP per port */
182 uint32_t octets; /**< Number of octets processed by PIP */
183 uint32_t packets; /**< Number of packets processed by PIP */
184 uint32_t multicast_packets; /**< Number of indentified L2 multicast packets.
185 Does not include broadcast packets.
186 Only includes packets whose parse mode is
187 SKIP_TO_L2 */
188 uint32_t broadcast_packets; /**< Number of indentified L2 broadcast packets.
189 Does not include multicast packets.
190 Only includes packets whose parse mode is
191 SKIP_TO_L2 */
192 uint32_t len_64_packets; /**< Number of 64B packets */
193 uint32_t len_65_127_packets; /**< Number of 65-127B packets */
194 uint32_t len_128_255_packets; /**< Number of 128-255B packets */
195 uint32_t len_256_511_packets; /**< Number of 256-511B packets */
196 uint32_t len_512_1023_packets; /**< Number of 512-1023B packets */
197 uint32_t len_1024_1518_packets; /**< Number of 1024-1518B packets */
198 uint32_t len_1519_max_packets; /**< Number of 1519-max packets */
199 uint32_t fcs_align_err_packets; /**< Number of packets with FCS or Align opcode errors */
200 uint32_t runt_packets; /**< Number of packets with length < min */
201 uint32_t runt_crc_packets; /**< Number of packets with length < min and FCS error */
202 uint32_t oversize_packets; /**< Number of packets with length > max */
203 uint32_t oversize_crc_packets; /**< Number of packets with length > max and FCS error */
204 uint32_t inb_packets; /**< Number of packets without GMX/SPX/PCI errors received by PIP */
205 uint64_t inb_octets; /**< Total number of octets from all packets received by PIP, including CRC */
206 uint16_t inb_errors; /**< Number of packets with GMX/SPX/PCI errors received by PIP */
207} cvmx_pip_port_status_t;
208
209
210/**
211 * Definition of the PIP custom header that can be prepended
212 * to a packet by external hardware.
213 */
214typedef union
215{
216 uint64_t u64;
217 struct
218 {
219 uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set,
220 this header must be the full 8 bytes */
221 uint64_t reserved0 : 5; /**< Must be zero */
222 cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */
223 uint64_t reserved1 : 1; /**< Must be zero */
224 uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */
225 uint64_t reserved2 : 6; /**< Must be zero */
226 uint64_t qos : 3; /**< POW input queue for this packet */
227 uint64_t grp : 4; /**< POW input group for this packet */
228 uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */
229 cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */
230 uint64_t tag : 32; /**< POW input tag */
231 } s;
232} cvmx_pip_pkt_inst_hdr_t;
233
234/* CSR typedefs have been moved to cvmx-csr-*.h */
235
236/**
237 * Configure an ethernet input port
238 *
239 * @param port_num Port number to configure
240 * @param port_cfg Port hardware configuration
241 * @param port_tag_cfg
242 * Port POW tagging configuration
243 */
244static inline void cvmx_pip_config_port(uint64_t port_num,
245 cvmx_pip_port_cfg_t port_cfg,
246 cvmx_pip_port_tag_cfg_t port_tag_cfg)
247{
248 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
249 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
250}
251
252
253/**
254 * @deprecated This function is a thin wrapper around the Pass1 version
255 * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
256 * setting the group that is incompatible with this function,
257 * the preferred upgrade path is to use the CSR directly.
258 *
259 * Configure the global QoS packet watchers. Each watcher is
260 * capable of matching a field in a packet to determine the
261 * QoS queue for scheduling.
262 *
263 * @param watcher Watcher number to configure (0 - 3).
264 * @param match_type Watcher match type
265 * @param match_value
266 * Value the watcher will match against
267 * @param qos QoS queue for packets matching this watcher
268 */
269static inline void cvmx_pip_config_watcher(uint64_t watcher,
270 cvmx_pip_qos_watch_types match_type,
271 uint64_t match_value, uint64_t qos)
272{
273 cvmx_pip_port_watcher_cfg_t watcher_config;
274
275 watcher_config.u64 = 0;
276 watcher_config.s.match_type = match_type;
277 watcher_config.s.match_value = match_value;
278 watcher_config.s.qos = qos;
279
280 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
281}
282
283
284/**
285 * Configure the VLAN priority to QoS queue mapping.
286 *
287 * @param vlan_priority
288 * VLAN priority (0-7)
289 * @param qos QoS queue for packets matching this watcher
290 */
291static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos)
292{
293 cvmx_pip_qos_vlanx_t pip_qos_vlanx;
294 pip_qos_vlanx.u64 = 0;
295 pip_qos_vlanx.s.qos = qos;
296 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
297}
298
299
300/**
301 * Configure the Diffserv to QoS queue mapping.
302 *
303 * @param diffserv Diffserv field value (0-63)
304 * @param qos QoS queue for packets matching this watcher
305 */
306static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
307{
308 cvmx_pip_qos_diffx_t pip_qos_diffx;
309 pip_qos_diffx.u64 = 0;
310 pip_qos_diffx.s.qos = qos;
311 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
312}
313
314
315/**
316 * Get the status counters for a port.
317 *
318 * @param port_num Port number to get statistics for.
319 * @param clear Set to 1 to clear the counters after they are read
320 * @param status Where to put the results.
321 */
322static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pip_port_status_t *status)
323{
324 cvmx_pip_stat_ctl_t pip_stat_ctl;
325 cvmx_pip_stat0_prtx_t stat0;
326 cvmx_pip_stat1_prtx_t stat1;
327 cvmx_pip_stat2_prtx_t stat2;
328 cvmx_pip_stat3_prtx_t stat3;
329 cvmx_pip_stat4_prtx_t stat4;
330 cvmx_pip_stat5_prtx_t stat5;
331 cvmx_pip_stat6_prtx_t stat6;
332 cvmx_pip_stat7_prtx_t stat7;
333 cvmx_pip_stat8_prtx_t stat8;
334 cvmx_pip_stat9_prtx_t stat9;
335 cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
336 cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
337 cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
338
339 pip_stat_ctl.u64 = 0;
340 pip_stat_ctl.s.rdclr = clear;
341 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
342
343 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
344 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
345 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
346 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
347 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
348 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
349 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
350 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
351 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
352 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
353 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
354 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
355 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
356
357 status->dropped_octets = stat0.s.drp_octs;
358 status->dropped_packets = stat0.s.drp_pkts;
359 status->octets = stat1.s.octs;
360 status->pci_raw_packets = stat2.s.raw;
361 status->packets = stat2.s.pkts;
362 status->multicast_packets = stat3.s.mcst;
363 status->broadcast_packets = stat3.s.bcst;
364 status->len_64_packets = stat4.s.h64;
365 status->len_65_127_packets = stat4.s.h65to127;
366 status->len_128_255_packets = stat5.s.h128to255;
367 status->len_256_511_packets = stat5.s.h256to511;
368 status->len_512_1023_packets = stat6.s.h512to1023;
369 status->len_1024_1518_packets = stat6.s.h1024to1518;
370 status->len_1519_max_packets = stat7.s.h1519;
371 status->fcs_align_err_packets = stat7.s.fcs;
372 status->runt_packets = stat8.s.undersz;
373 status->runt_crc_packets = stat8.s.frag;
374 status->oversize_packets = stat9.s.oversz;
375 status->oversize_crc_packets = stat9.s.jabber;
376 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
377 status->inb_octets = pip_stat_inb_octsx.s.octs;
378 status->inb_errors = pip_stat_inb_errsx.s.errs;
379
380 if (cvmx_octeon_is_pass1())
381 {
382 /* Kludge to fix Octeon Pass 1 errata - Drop counts don't work */
383 if (status->inb_packets > status->packets)
384 status->dropped_packets = status->inb_packets - status->packets;
385 else
386 status->dropped_packets = 0;
387 if (status->inb_octets - status->inb_packets*4 > status->octets)
388 status->dropped_octets = status->inb_octets - status->inb_packets*4 - status->octets;
389 else
390 status->dropped_octets = 0;
391 }
392}
393
394
395/**
396 * Configure the hardware CRC engine
397 *
398 * @param interface Interface to configure (0 or 1)
399 * @param invert_result
400 * Invert the result of the CRC
401 * @param reflect Reflect
402 * @param initialization_vector
403 * CRC initialization vector
404 */
405static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, uint32_t initialization_vector)
406{
407 if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
408 {
409 cvmx_pip_crc_ctlx_t config;
410 cvmx_pip_crc_ivx_t pip_crc_ivx;
411
412 config.u64 = 0;
413 config.s.invres = invert_result;
414 config.s.reflect = reflect;
415 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
416
417 pip_crc_ivx.u64 = 0;
418 pip_crc_ivx.s.iv = initialization_vector;
419 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
420 }
421}
422
423
424/**
425 * Clear all bits in a tag mask. This should be called on
426 * startup before any calls to cvmx_pip_tag_mask_set. Each bit
427 * set in the final mask represent a byte used in the packet for
428 * tag generation.
429 *
430 * @param mask_index Which tag mask to clear (0..3)
431 */
432static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
433{
434 uint64_t index;
435 cvmx_pip_tag_incx_t pip_tag_incx;
436 pip_tag_incx.u64 = 0;
437 pip_tag_incx.s.en = 0;
438 for (index=mask_index*16; index<(mask_index+1)*16; index++)
439 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
440}
441
442
443/**
444 * Sets a range of bits in the tag mask. The tag mask is used
445 * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
446 * There are four separate masks that can be configured.
447 *
448 * @param mask_index Which tag mask to modify (0..3)
449 * @param offset Offset into the bitmask to set bits at. Use the GCC macro
450 * offsetof() to determine the offsets into packet headers.
451 * For example, offsetof(ethhdr, protocol) returns the offset
452 * of the ethernet protocol field. The bitmask selects which bytes
453 * to include the the tag, with bit offset X selecting byte at offset X
454 * from the beginning of the packet data.
455 * @param len Number of bytes to include. Usually this is the sizeof()
456 * the field.
457 */
458static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len)
459{
460 while (len--)
461 {
462 cvmx_pip_tag_incx_t pip_tag_incx;
463 uint64_t index = mask_index*16 + offset/8;
464 pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
465 pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
466 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
467 offset++;
468 }
469}
470
471#ifdef __cplusplus
472}
473#endif
474
475#endif /* __CVMX_PIP_H__ */
2 * Copyright (c) 2003-2008 Cavium Networks (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17 *
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
22 *
23 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
24 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
25 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
26 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
27 * REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
28 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
29 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
30 * PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
31 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
32 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
33 *
34 *
35 * For any questions regarding licensing please contact marketing@caviumnetworks.com
36 *
37 ***********************license end**************************************/
38
39
40
41
42
43
44/**
45 * @file
46 *
47 * Interface to the hardware Packet Input Processing unit.
48 *
49 * <hr>$Revision: 41586 $<hr>
50 */
51
52
53#ifndef __CVMX_PIP_H__
54#define __CVMX_PIP_H__
55
56#include "cvmx-wqe.h"
57#include "cvmx-fpa.h"
58#ifndef CVMX_DONT_INCLUDE_CONFIG
59#include "executive-config.h"
60#endif
61
62#ifdef __cplusplus
63extern "C" {
64#endif
65
66#define CVMX_PIP_NUM_INPUT_PORTS 40
67#define CVMX_PIP_NUM_WATCHERS 4
68
69
70
71
72
73
74
75//
76// Encodes the different error and exception codes
77//
78typedef enum
79{
80 CVMX_PIP_L4_NO_ERR = 0ull,
81 // 1 = TCP (UDP) packet not long enough to cover TCP (UDP) header
82 CVMX_PIP_L4_MAL_ERR = 1ull,
83 // 2 = TCP/UDP checksum failure
84 CVMX_PIP_CHK_ERR = 2ull,
85 // 3 = TCP/UDP length check (TCP/UDP length does not match IP length)
86 CVMX_PIP_L4_LENGTH_ERR = 3ull,
87 // 4 = illegal TCP/UDP port (either source or dest port is zero)
88 CVMX_PIP_BAD_PRT_ERR = 4ull,
89 // 8 = TCP flags = FIN only
90 CVMX_PIP_TCP_FLG8_ERR = 8ull,
91 // 9 = TCP flags = 0
92 CVMX_PIP_TCP_FLG9_ERR = 9ull,
93 // 10 = TCP flags = FIN+RST+*
94 CVMX_PIP_TCP_FLG10_ERR = 10ull,
95 // 11 = TCP flags = SYN+URG+*
96 CVMX_PIP_TCP_FLG11_ERR = 11ull,
97 // 12 = TCP flags = SYN+RST+*
98 CVMX_PIP_TCP_FLG12_ERR = 12ull,
99 // 13 = TCP flags = SYN+FIN+*
100 CVMX_PIP_TCP_FLG13_ERR = 13ull
101} cvmx_pip_l4_err_t;
102
103typedef enum
104{
105
106 CVMX_PIP_IP_NO_ERR = 0ull,
107 // 1 = not IPv4 or IPv6
108 CVMX_PIP_NOT_IP = 1ull,
109 // 2 = IPv4 header checksum violation
110 CVMX_PIP_IPV4_HDR_CHK = 2ull,
111 // 3 = malformed (packet not long enough to cover IP hdr)
112 CVMX_PIP_IP_MAL_HDR = 3ull,
113 // 4 = malformed (packet not long enough to cover len in IP hdr)
114 CVMX_PIP_IP_MAL_PKT = 4ull,
115 // 5 = TTL / hop count equal zero
116 CVMX_PIP_TTL_HOP = 5ull,
117 // 6 = IPv4 options / IPv6 early extension headers
118 CVMX_PIP_OPTS = 6ull
119} cvmx_pip_ip_exc_t;
120
121
122/**
123 * NOTES
124 * late collision (data received before collision)
125 * late collisions cannot be detected by the receiver
126 * they would appear as JAM bits which would appear as bad FCS
127 * or carrier extend error which is CVMX_PIP_EXTEND_ERR
128 */
129typedef enum
130{
131 /**
132 * No error
133 */
134 CVMX_PIP_RX_NO_ERR = 0ull,
135
136 CVMX_PIP_PARTIAL_ERR = 1ull, // RGM+SPI 1 = partially received packet (buffering/bandwidth not adequate)
137 CVMX_PIP_JABBER_ERR = 2ull, // RGM+SPI 2 = receive packet too large and truncated
138 CVMX_PIP_OVER_FCS_ERR = 3ull, // RGM 3 = max frame error (pkt len > max frame len) (with FCS error)
139 CVMX_PIP_OVER_ERR = 4ull, // RGM+SPI 4 = max frame error (pkt len > max frame len)
140 CVMX_PIP_ALIGN_ERR = 5ull, // RGM 5 = nibble error (data not byte multiple - 100M and 10M only)
141 CVMX_PIP_UNDER_FCS_ERR = 6ull, // RGM 6 = min frame error (pkt len < min frame len) (with FCS error)
142 CVMX_PIP_GMX_FCS_ERR = 7ull, // RGM 7 = FCS error
143 CVMX_PIP_UNDER_ERR = 8ull, // RGM+SPI 8 = min frame error (pkt len < min frame len)
144 CVMX_PIP_EXTEND_ERR = 9ull, // RGM 9 = Frame carrier extend error
145 CVMX_PIP_LENGTH_ERR = 10ull, // RGM 10 = length mismatch (len did not match len in L2 length/type)
146 CVMX_PIP_DAT_ERR = 11ull, // RGM 11 = Frame error (some or all data bits marked err)
147 CVMX_PIP_DIP_ERR = 11ull, // SPI 11 = DIP4 error
148 CVMX_PIP_SKIP_ERR = 12ull, // RGM 12 = packet was not large enough to pass the skipper - no inspection could occur
149 CVMX_PIP_NIBBLE_ERR = 13ull, // RGM 13 = studder error (data not repeated - 100M and 10M only)
150 CVMX_PIP_PIP_FCS = 16L, // RGM+SPI 16 = FCS error
151 CVMX_PIP_PIP_SKIP_ERR = 17L, // RGM+SPI+PCI 17 = packet was not large enough to pass the skipper - no inspection could occur
152 CVMX_PIP_PIP_L2_MAL_HDR= 18L // RGM+SPI+PCI 18 = malformed l2 (packet not long enough to cover L2 hdr)
153 // NOTES
154 // xx = late collision (data received before collision)
155 // late collisions cannot be detected by the receiver
156 // they would appear as JAM bits which would appear as bad FCS
157 // or carrier extend error which is CVMX_PIP_EXTEND_ERR
158
159
160
161} cvmx_pip_rcv_err_t;
162
163/**
164 * This defines the err_code field errors in the work Q entry
165 */
166typedef union
167{
168 cvmx_pip_l4_err_t l4_err;
169 cvmx_pip_ip_exc_t ip_exc;
170 cvmx_pip_rcv_err_t rcv_err;
171} cvmx_pip_err_t;
172
173
174/**
175 * Status statistics for a port
176 */
177typedef struct
178{
179 uint32_t dropped_octets; /**< Inbound octets marked to be dropped by the IPD */
180 uint32_t dropped_packets; /**< Inbound packets marked to be dropped by the IPD */
181 uint32_t pci_raw_packets; /**< RAW PCI Packets received by PIP per port */
182 uint32_t octets; /**< Number of octets processed by PIP */
183 uint32_t packets; /**< Number of packets processed by PIP */
184 uint32_t multicast_packets; /**< Number of indentified L2 multicast packets.
185 Does not include broadcast packets.
186 Only includes packets whose parse mode is
187 SKIP_TO_L2 */
188 uint32_t broadcast_packets; /**< Number of indentified L2 broadcast packets.
189 Does not include multicast packets.
190 Only includes packets whose parse mode is
191 SKIP_TO_L2 */
192 uint32_t len_64_packets; /**< Number of 64B packets */
193 uint32_t len_65_127_packets; /**< Number of 65-127B packets */
194 uint32_t len_128_255_packets; /**< Number of 128-255B packets */
195 uint32_t len_256_511_packets; /**< Number of 256-511B packets */
196 uint32_t len_512_1023_packets; /**< Number of 512-1023B packets */
197 uint32_t len_1024_1518_packets; /**< Number of 1024-1518B packets */
198 uint32_t len_1519_max_packets; /**< Number of 1519-max packets */
199 uint32_t fcs_align_err_packets; /**< Number of packets with FCS or Align opcode errors */
200 uint32_t runt_packets; /**< Number of packets with length < min */
201 uint32_t runt_crc_packets; /**< Number of packets with length < min and FCS error */
202 uint32_t oversize_packets; /**< Number of packets with length > max */
203 uint32_t oversize_crc_packets; /**< Number of packets with length > max and FCS error */
204 uint32_t inb_packets; /**< Number of packets without GMX/SPX/PCI errors received by PIP */
205 uint64_t inb_octets; /**< Total number of octets from all packets received by PIP, including CRC */
206 uint16_t inb_errors; /**< Number of packets with GMX/SPX/PCI errors received by PIP */
207} cvmx_pip_port_status_t;
208
209
210/**
211 * Definition of the PIP custom header that can be prepended
212 * to a packet by external hardware.
213 */
214typedef union
215{
216 uint64_t u64;
217 struct
218 {
219 uint64_t rawfull : 1; /**< Documented as R - Set if the Packet is RAWFULL. If set,
220 this header must be the full 8 bytes */
221 uint64_t reserved0 : 5; /**< Must be zero */
222 cvmx_pip_port_parse_mode_t parse_mode : 2; /**< PIP parse mode for this packet */
223 uint64_t reserved1 : 1; /**< Must be zero */
224 uint64_t skip_len : 7; /**< Skip amount, including this header, to the beginning of the packet */
225 uint64_t reserved2 : 6; /**< Must be zero */
226 uint64_t qos : 3; /**< POW input queue for this packet */
227 uint64_t grp : 4; /**< POW input group for this packet */
228 uint64_t rs : 1; /**< Flag to store this packet in the work queue entry, if possible */
229 cvmx_pow_tag_type_t tag_type : 2; /**< POW input tag type */
230 uint64_t tag : 32; /**< POW input tag */
231 } s;
232} cvmx_pip_pkt_inst_hdr_t;
233
234/* CSR typedefs have been moved to cvmx-csr-*.h */
235
236/**
237 * Configure an ethernet input port
238 *
239 * @param port_num Port number to configure
240 * @param port_cfg Port hardware configuration
241 * @param port_tag_cfg
242 * Port POW tagging configuration
243 */
244static inline void cvmx_pip_config_port(uint64_t port_num,
245 cvmx_pip_port_cfg_t port_cfg,
246 cvmx_pip_port_tag_cfg_t port_tag_cfg)
247{
248 cvmx_write_csr(CVMX_PIP_PRT_CFGX(port_num), port_cfg.u64);
249 cvmx_write_csr(CVMX_PIP_PRT_TAGX(port_num), port_tag_cfg.u64);
250}
251
252
253/**
254 * @deprecated This function is a thin wrapper around the Pass1 version
255 * of the CVMX_PIP_QOS_WATCHX CSR; Pass2 has added a field for
256 * setting the group that is incompatible with this function,
257 * the preferred upgrade path is to use the CSR directly.
258 *
259 * Configure the global QoS packet watchers. Each watcher is
260 * capable of matching a field in a packet to determine the
261 * QoS queue for scheduling.
262 *
263 * @param watcher Watcher number to configure (0 - 3).
264 * @param match_type Watcher match type
265 * @param match_value
266 * Value the watcher will match against
267 * @param qos QoS queue for packets matching this watcher
268 */
269static inline void cvmx_pip_config_watcher(uint64_t watcher,
270 cvmx_pip_qos_watch_types match_type,
271 uint64_t match_value, uint64_t qos)
272{
273 cvmx_pip_port_watcher_cfg_t watcher_config;
274
275 watcher_config.u64 = 0;
276 watcher_config.s.match_type = match_type;
277 watcher_config.s.match_value = match_value;
278 watcher_config.s.qos = qos;
279
280 cvmx_write_csr(CVMX_PIP_QOS_WATCHX(watcher), watcher_config.u64);
281}
282
283
284/**
285 * Configure the VLAN priority to QoS queue mapping.
286 *
287 * @param vlan_priority
288 * VLAN priority (0-7)
289 * @param qos QoS queue for packets matching this watcher
290 */
291static inline void cvmx_pip_config_vlan_qos(uint64_t vlan_priority, uint64_t qos)
292{
293 cvmx_pip_qos_vlanx_t pip_qos_vlanx;
294 pip_qos_vlanx.u64 = 0;
295 pip_qos_vlanx.s.qos = qos;
296 cvmx_write_csr(CVMX_PIP_QOS_VLANX(vlan_priority), pip_qos_vlanx.u64);
297}
298
299
300/**
301 * Configure the Diffserv to QoS queue mapping.
302 *
303 * @param diffserv Diffserv field value (0-63)
304 * @param qos QoS queue for packets matching this watcher
305 */
306static inline void cvmx_pip_config_diffserv_qos(uint64_t diffserv, uint64_t qos)
307{
308 cvmx_pip_qos_diffx_t pip_qos_diffx;
309 pip_qos_diffx.u64 = 0;
310 pip_qos_diffx.s.qos = qos;
311 cvmx_write_csr(CVMX_PIP_QOS_DIFFX(diffserv), pip_qos_diffx.u64);
312}
313
314
315/**
316 * Get the status counters for a port.
317 *
318 * @param port_num Port number to get statistics for.
319 * @param clear Set to 1 to clear the counters after they are read
320 * @param status Where to put the results.
321 */
322static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear, cvmx_pip_port_status_t *status)
323{
324 cvmx_pip_stat_ctl_t pip_stat_ctl;
325 cvmx_pip_stat0_prtx_t stat0;
326 cvmx_pip_stat1_prtx_t stat1;
327 cvmx_pip_stat2_prtx_t stat2;
328 cvmx_pip_stat3_prtx_t stat3;
329 cvmx_pip_stat4_prtx_t stat4;
330 cvmx_pip_stat5_prtx_t stat5;
331 cvmx_pip_stat6_prtx_t stat6;
332 cvmx_pip_stat7_prtx_t stat7;
333 cvmx_pip_stat8_prtx_t stat8;
334 cvmx_pip_stat9_prtx_t stat9;
335 cvmx_pip_stat_inb_pktsx_t pip_stat_inb_pktsx;
336 cvmx_pip_stat_inb_octsx_t pip_stat_inb_octsx;
337 cvmx_pip_stat_inb_errsx_t pip_stat_inb_errsx;
338
339 pip_stat_ctl.u64 = 0;
340 pip_stat_ctl.s.rdclr = clear;
341 cvmx_write_csr(CVMX_PIP_STAT_CTL, pip_stat_ctl.u64);
342
343 stat0.u64 = cvmx_read_csr(CVMX_PIP_STAT0_PRTX(port_num));
344 stat1.u64 = cvmx_read_csr(CVMX_PIP_STAT1_PRTX(port_num));
345 stat2.u64 = cvmx_read_csr(CVMX_PIP_STAT2_PRTX(port_num));
346 stat3.u64 = cvmx_read_csr(CVMX_PIP_STAT3_PRTX(port_num));
347 stat4.u64 = cvmx_read_csr(CVMX_PIP_STAT4_PRTX(port_num));
348 stat5.u64 = cvmx_read_csr(CVMX_PIP_STAT5_PRTX(port_num));
349 stat6.u64 = cvmx_read_csr(CVMX_PIP_STAT6_PRTX(port_num));
350 stat7.u64 = cvmx_read_csr(CVMX_PIP_STAT7_PRTX(port_num));
351 stat8.u64 = cvmx_read_csr(CVMX_PIP_STAT8_PRTX(port_num));
352 stat9.u64 = cvmx_read_csr(CVMX_PIP_STAT9_PRTX(port_num));
353 pip_stat_inb_pktsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_PKTSX(port_num));
354 pip_stat_inb_octsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_OCTSX(port_num));
355 pip_stat_inb_errsx.u64 = cvmx_read_csr(CVMX_PIP_STAT_INB_ERRSX(port_num));
356
357 status->dropped_octets = stat0.s.drp_octs;
358 status->dropped_packets = stat0.s.drp_pkts;
359 status->octets = stat1.s.octs;
360 status->pci_raw_packets = stat2.s.raw;
361 status->packets = stat2.s.pkts;
362 status->multicast_packets = stat3.s.mcst;
363 status->broadcast_packets = stat3.s.bcst;
364 status->len_64_packets = stat4.s.h64;
365 status->len_65_127_packets = stat4.s.h65to127;
366 status->len_128_255_packets = stat5.s.h128to255;
367 status->len_256_511_packets = stat5.s.h256to511;
368 status->len_512_1023_packets = stat6.s.h512to1023;
369 status->len_1024_1518_packets = stat6.s.h1024to1518;
370 status->len_1519_max_packets = stat7.s.h1519;
371 status->fcs_align_err_packets = stat7.s.fcs;
372 status->runt_packets = stat8.s.undersz;
373 status->runt_crc_packets = stat8.s.frag;
374 status->oversize_packets = stat9.s.oversz;
375 status->oversize_crc_packets = stat9.s.jabber;
376 status->inb_packets = pip_stat_inb_pktsx.s.pkts;
377 status->inb_octets = pip_stat_inb_octsx.s.octs;
378 status->inb_errors = pip_stat_inb_errsx.s.errs;
379
380 if (cvmx_octeon_is_pass1())
381 {
382 /* Kludge to fix Octeon Pass 1 errata - Drop counts don't work */
383 if (status->inb_packets > status->packets)
384 status->dropped_packets = status->inb_packets - status->packets;
385 else
386 status->dropped_packets = 0;
387 if (status->inb_octets - status->inb_packets*4 > status->octets)
388 status->dropped_octets = status->inb_octets - status->inb_packets*4 - status->octets;
389 else
390 status->dropped_octets = 0;
391 }
392}
393
394
395/**
396 * Configure the hardware CRC engine
397 *
398 * @param interface Interface to configure (0 or 1)
399 * @param invert_result
400 * Invert the result of the CRC
401 * @param reflect Reflect
402 * @param initialization_vector
403 * CRC initialization vector
404 */
405static inline void cvmx_pip_config_crc(uint64_t interface, uint64_t invert_result, uint64_t reflect, uint32_t initialization_vector)
406{
407 if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)))
408 {
409 cvmx_pip_crc_ctlx_t config;
410 cvmx_pip_crc_ivx_t pip_crc_ivx;
411
412 config.u64 = 0;
413 config.s.invres = invert_result;
414 config.s.reflect = reflect;
415 cvmx_write_csr(CVMX_PIP_CRC_CTLX(interface), config.u64);
416
417 pip_crc_ivx.u64 = 0;
418 pip_crc_ivx.s.iv = initialization_vector;
419 cvmx_write_csr(CVMX_PIP_CRC_IVX(interface), pip_crc_ivx.u64);
420 }
421}
422
423
424/**
425 * Clear all bits in a tag mask. This should be called on
426 * startup before any calls to cvmx_pip_tag_mask_set. Each bit
427 * set in the final mask represent a byte used in the packet for
428 * tag generation.
429 *
430 * @param mask_index Which tag mask to clear (0..3)
431 */
432static inline void cvmx_pip_tag_mask_clear(uint64_t mask_index)
433{
434 uint64_t index;
435 cvmx_pip_tag_incx_t pip_tag_incx;
436 pip_tag_incx.u64 = 0;
437 pip_tag_incx.s.en = 0;
438 for (index=mask_index*16; index<(mask_index+1)*16; index++)
439 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
440}
441
442
443/**
444 * Sets a range of bits in the tag mask. The tag mask is used
445 * when the cvmx_pip_port_tag_cfg_t tag_mode is non zero.
446 * There are four separate masks that can be configured.
447 *
448 * @param mask_index Which tag mask to modify (0..3)
449 * @param offset Offset into the bitmask to set bits at. Use the GCC macro
450 * offsetof() to determine the offsets into packet headers.
451 * For example, offsetof(ethhdr, protocol) returns the offset
452 * of the ethernet protocol field. The bitmask selects which bytes
453 * to include the the tag, with bit offset X selecting byte at offset X
454 * from the beginning of the packet data.
455 * @param len Number of bytes to include. Usually this is the sizeof()
456 * the field.
457 */
458static inline void cvmx_pip_tag_mask_set(uint64_t mask_index, uint64_t offset, uint64_t len)
459{
460 while (len--)
461 {
462 cvmx_pip_tag_incx_t pip_tag_incx;
463 uint64_t index = mask_index*16 + offset/8;
464 pip_tag_incx.u64 = cvmx_read_csr(CVMX_PIP_TAG_INCX(index));
465 pip_tag_incx.s.en |= 0x80 >> (offset & 0x7);
466 cvmx_write_csr(CVMX_PIP_TAG_INCX(index), pip_tag_incx.u64);
467 offset++;
468 }
469}
470
471#ifdef __cplusplus
472}
473#endif
474
475#endif /* __CVMX_PIP_H__ */