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ena_eth_io_defs.h (343397) ena_eth_io_defs.h (361467)
1/*-
2 * BSD LICENSE
3 *
1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
4 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.

--- 16 unchanged lines hidden (view full) ---

29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33#ifndef _ENA_ETH_IO_H_
34#define _ENA_ETH_IO_H_
35
36enum ena_eth_io_l3_proto_index {
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.

--- 16 unchanged lines hidden (view full) ---

29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33#ifndef _ENA_ETH_IO_H_
34#define _ENA_ETH_IO_H_
35
36enum ena_eth_io_l3_proto_index {
37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
38
39 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
40
41 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
42
43 ENA_ETH_IO_L3_PROTO_FCOE = 21,
44
45 ENA_ETH_IO_L3_PROTO_ROCE = 22,
37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
38 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
39 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
40 ENA_ETH_IO_L3_PROTO_FCOE = 21,
41 ENA_ETH_IO_L3_PROTO_ROCE = 22,
46};
47
48enum ena_eth_io_l4_proto_index {
42};
43
44enum ena_eth_io_l4_proto_index {
49 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
50
51 ENA_ETH_IO_L4_PROTO_TCP = 12,
52
53 ENA_ETH_IO_L4_PROTO_UDP = 13,
54
55 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
45 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
46 ENA_ETH_IO_L4_PROTO_TCP = 12,
47 ENA_ETH_IO_L4_PROTO_UDP = 13,
48 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
56};
57
58struct ena_eth_io_tx_desc {
59 /* 15:0 : length - Buffer length in bytes, must
60 * include any packet trailers that the ENA supposed
61 * to update like End-to-End CRC, Authentication GMAC
62 * etc. This length must not include the
63 * 'Push_Buffer' length. This length must not include

--- 174 unchanged lines hidden (view full) ---

238 * 13 : l3_csum_err - when set, either the L3
239 * checksum error detected, or, the controller didn't
240 * validate the checksum. This bit is valid only when
241 * l3_proto_idx indicates IPv4 packet
242 * 14 : l4_csum_err - when set, either the L4
243 * checksum error detected, or, the controller didn't
244 * validate the checksum. This bit is valid only when
245 * l4_proto_idx indicates TCP/UDP packet, and,
49};
50
51struct ena_eth_io_tx_desc {
52 /* 15:0 : length - Buffer length in bytes, must
53 * include any packet trailers that the ENA supposed
54 * to update like End-to-End CRC, Authentication GMAC
55 * etc. This length must not include the
56 * 'Push_Buffer' length. This length must not include

--- 174 unchanged lines hidden (view full) ---

231 * 13 : l3_csum_err - when set, either the L3
232 * checksum error detected, or, the controller didn't
233 * validate the checksum. This bit is valid only when
234 * l3_proto_idx indicates IPv4 packet
235 * 14 : l4_csum_err - when set, either the L4
236 * checksum error detected, or, the controller didn't
237 * validate the checksum. This bit is valid only when
238 * l4_proto_idx indicates TCP/UDP packet, and,
246 * ipv4_frag is not set
239 * ipv4_frag is not set. This bit is valid only when
240 * l4_csum_checked below is set.
247 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
241 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
248 * 23:16 : reserved16
242 * 16 : l4_csum_checked - L4 checksum was verified
243 * (could be OK or error), when cleared the status of
244 * checksum is unknown
245 * 23:17 : reserved17 - MBZ
249 * 24 : phase
250 * 25 : l3_csum2 - second checksum engine result
251 * 26 : first - Indicates first descriptor in
252 * transaction
253 * 27 : last - Indicates last descriptor in
254 * transaction
255 * 29:28 : reserved28
256 * 30 : buffer - 0: Metadata descriptor. 1: Buffer

--- 42 unchanged lines hidden (view full) ---

299 /* 7:0 : numa
300 * 30:8 : reserved
301 * 31 : enabled
302 */
303 uint32_t numa_cfg;
304};
305
306/* tx_desc */
246 * 24 : phase
247 * 25 : l3_csum2 - second checksum engine result
248 * 26 : first - Indicates first descriptor in
249 * transaction
250 * 27 : last - Indicates last descriptor in
251 * transaction
252 * 29:28 : reserved28
253 * 30 : buffer - 0: Metadata descriptor. 1: Buffer

--- 42 unchanged lines hidden (view full) ---

296 /* 7:0 : numa
297 * 30:8 : reserved
298 * 31 : enabled
299 */
300 uint32_t numa_cfg;
301};
302
303/* tx_desc */
307#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
308#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
309#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
310#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
311#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
312#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
313#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
314#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
315#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
316#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
317#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
318#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
319#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
320#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
321#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
322#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
323#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
324#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
325#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
326#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
327#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
328#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
329#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
330#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
331#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
332#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
333#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
334#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
335#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
336#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
337#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
338#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
339#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
304#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
305#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
306#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
307#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
308#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
309#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
310#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
311#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
312#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
313#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
314#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
315#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
316#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
317#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
318#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
319#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
320#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
321#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
322#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
323#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
324#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
325#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
326#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
327#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
328#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
329#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
330#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
331#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
332#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
333#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
334#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
335#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
336#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
340
341/* tx_meta_desc */
337
338/* tx_meta_desc */
342#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
343#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
344#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
345#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
346#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
347#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
348#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
349#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
350#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
351#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
352#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
353#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
354#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
355#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
356#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
357#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
358#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
359#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
360#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
361#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
362#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
363#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
364#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
365#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
366#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
367#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
368#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
339#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
340#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
341#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
342#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
343#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
344#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
345#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
346#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
347#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
348#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
349#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
350#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
351#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
352#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
353#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
354#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
355#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
356#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
357#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
358#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
359#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
360#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
361#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
362#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
363#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
364#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
365#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
369
370/* tx_cdesc */
366
367/* tx_cdesc */
371#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
368#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
372
373/* rx_desc */
369
370/* rx_desc */
374#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
375#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
376#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
377#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
378#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
379#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
380#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
371#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
372#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
373#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
374#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
375#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
376#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
377#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
381
382/* rx_cdesc_base */
378
379/* rx_cdesc_base */
383#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
384#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
385#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
386#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
387#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
388#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
389#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
390#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
392#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
393#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
394#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
395#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
396#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
397#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
398#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
399#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
400#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
401#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
402#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
403#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
380#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
381#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
382#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
383#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
384#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
385#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
386#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
387#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
388#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
389#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
390#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
392#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
393#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
394#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
395#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
396#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
397#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
398#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
399#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
400#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
401#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
402#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
404
405/* intr_reg */
403
404/* intr_reg */
406#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
407#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
408#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
409#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
410#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
405#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
406#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
407#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
408#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
409#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
411
412/* numa_node_cfg_reg */
410
411/* numa_node_cfg_reg */
413#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
415#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
412#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
413#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
416
415
417#if !defined(ENA_DEFS_LINUX_MAINLINE)
416#if !defined(DEFS_LINUX_MAINLINE)
418static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)
419{
420 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
421}
422
423static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)
424{
425 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;

--- 424 unchanged lines hidden (view full) ---

850 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
851}
852
853static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
854{
855 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
856}
857
417static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)
418{
419 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
420}
421
422static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)
423{
424 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;

--- 424 unchanged lines hidden (view full) ---

849 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
850}
851
852static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
853{
854 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
855}
856
857static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p)
858{
859 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT;
860}
861
862static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
863{
864 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK;
865}
866
858static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
859{
860 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
861}
862
863static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
864{
865 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;

--- 84 unchanged lines hidden (view full) ---

950 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
951}
952
953static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
954{
955 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
956}
957
867static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
868{
869 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
870}
871
872static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
873{
874 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;

--- 84 unchanged lines hidden (view full) ---

959 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
960}
961
962static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
963{
964 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
965}
966
958#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
967#endif /* !defined(DEFS_LINUX_MAINLINE) */
959#endif /*_ENA_ETH_IO_H_ */
968#endif /*_ENA_ETH_IO_H_ */