4c4
< * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
---
> * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
37,45c37,41
< ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
<
< ENA_ETH_IO_L3_PROTO_IPV4 = 8,
<
< ENA_ETH_IO_L3_PROTO_IPV6 = 11,
<
< ENA_ETH_IO_L3_PROTO_FCOE = 21,
<
< ENA_ETH_IO_L3_PROTO_ROCE = 22,
---
> ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
> ENA_ETH_IO_L3_PROTO_IPV4 = 8,
> ENA_ETH_IO_L3_PROTO_IPV6 = 11,
> ENA_ETH_IO_L3_PROTO_FCOE = 21,
> ENA_ETH_IO_L3_PROTO_ROCE = 22,
49,55c45,48
< ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
<
< ENA_ETH_IO_L4_PROTO_TCP = 12,
<
< ENA_ETH_IO_L4_PROTO_UDP = 13,
<
< ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
---
> ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
> ENA_ETH_IO_L4_PROTO_TCP = 12,
> ENA_ETH_IO_L4_PROTO_UDP = 13,
> ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
246c239,240
< * ipv4_frag is not set
---
> * ipv4_frag is not set. This bit is valid only when
> * l4_csum_checked below is set.
248c242,245
< * 23:16 : reserved16
---
> * 16 : l4_csum_checked - L4 checksum was verified
> * (could be OK or error), when cleared the status of
> * checksum is unknown
> * 23:17 : reserved17 - MBZ
307,339c304,336
< #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
< #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
< #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
< #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
< #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
< #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
< #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
< #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
< #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
< #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
< #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
< #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
< #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
< #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
< #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
< #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
< #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
< #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
< #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
< #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
< #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
< #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
< #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
< #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
< #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
< #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
< #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
---
> #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
> #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
> #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
> #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
> #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
> #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
> #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
> #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
> #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
> #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
> #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
> #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
> #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
> #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
> #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
> #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
> #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
> #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
> #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
> #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
> #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
> #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
> #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
> #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
> #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
> #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
> #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
342,368c339,365
< #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
< #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
< #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
< #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
< #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
< #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
< #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
< #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
< #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
< #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
< #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
< #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
< #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
< #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
< #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
< #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
< #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
< #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
< #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
< #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
< #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
< #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
---
> #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
> #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
> #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
> #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
> #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
> #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
> #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
> #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
> #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
> #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
> #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
> #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
> #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
> #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
> #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
> #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
> #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
> #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
> #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
> #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
> #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
> #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
371c368
< #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
---
> #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
374,380c371,377
< #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
< #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
< #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
< #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
< #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
< #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
< #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
---
> #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
> #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
> #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
> #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
> #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
> #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
> #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
383,403c380,402
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
< #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
< #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
< #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
< #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
< #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
< #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
< #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
< #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
< #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
< #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
< #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
---
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
> #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
> #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
> #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
> #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
> #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
> #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
> #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
> #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
> #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
> #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
> #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
406,410c405,409
< #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
< #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
< #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
< #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
< #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
---
> #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
> #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
> #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
> #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
> #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
413,415c412,414
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
---
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
417c416
< #if !defined(ENA_DEFS_LINUX_MAINLINE)
---
> #if !defined(DEFS_LINUX_MAINLINE)
857a857,866
> static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p)
> {
> return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT;
> }
>
> static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
> {
> p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK;
> }
>
958c967
< #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
---
> #endif /* !defined(DEFS_LINUX_MAINLINE) */
< * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
---
> * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
37,45c37,41
< ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
<
< ENA_ETH_IO_L3_PROTO_IPV4 = 8,
<
< ENA_ETH_IO_L3_PROTO_IPV6 = 11,
<
< ENA_ETH_IO_L3_PROTO_FCOE = 21,
<
< ENA_ETH_IO_L3_PROTO_ROCE = 22,
---
> ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
> ENA_ETH_IO_L3_PROTO_IPV4 = 8,
> ENA_ETH_IO_L3_PROTO_IPV6 = 11,
> ENA_ETH_IO_L3_PROTO_FCOE = 21,
> ENA_ETH_IO_L3_PROTO_ROCE = 22,
49,55c45,48
< ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
<
< ENA_ETH_IO_L4_PROTO_TCP = 12,
<
< ENA_ETH_IO_L4_PROTO_UDP = 13,
<
< ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
---
> ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
> ENA_ETH_IO_L4_PROTO_TCP = 12,
> ENA_ETH_IO_L4_PROTO_UDP = 13,
> ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
246c239,240
< * ipv4_frag is not set
---
> * ipv4_frag is not set. This bit is valid only when
> * l4_csum_checked below is set.
248c242,245
< * 23:16 : reserved16
---
> * 16 : l4_csum_checked - L4 checksum was verified
> * (could be OK or error), when cleared the status of
> * checksum is unknown
> * 23:17 : reserved17 - MBZ
307,339c304,336
< #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
< #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
< #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
< #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
< #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
< #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
< #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
< #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
< #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
< #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
< #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
< #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
< #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
< #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
< #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
< #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
< #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
< #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
< #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
< #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
< #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
< #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
< #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
< #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
< #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
< #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
< #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
< #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
---
> #define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
> #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
> #define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
> #define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
> #define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
> #define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
> #define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
> #define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
> #define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
> #define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
> #define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
> #define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
> #define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
> #define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
> #define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
> #define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
> #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
> #define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
> #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
> #define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
> #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
> #define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
> #define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
> #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
> #define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
> #define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
> #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
> #define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
342,368c339,365
< #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
< #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
< #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
< #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
< #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
< #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
< #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
< #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
< #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
< #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
< #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
< #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
< #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
< #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
< #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
< #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
< #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
< #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
< #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
< #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
< #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
< #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
< #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
---
> #define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
> #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
> #define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
> #define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
> #define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
> #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
> #define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
> #define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
> #define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
> #define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
> #define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
> #define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
> #define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
> #define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
> #define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
> #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
> #define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
> #define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
> #define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
> #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
> #define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
> #define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
> #define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
371c368
< #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
---
> #define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
374,380c371,377
< #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
< #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
< #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
< #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
< #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
< #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
< #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
---
> #define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
> #define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
> #define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
> #define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
> #define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
> #define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
> #define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
383,403c380,402
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
< #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
< #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
< #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
< #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
< #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
< #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
< #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
< #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
< #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
< #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
< #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
< #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
< #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
< #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
---
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
> #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
> #define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
> #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
> #define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT 16
> #define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK BIT(16)
> #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
> #define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
> #define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
> #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
> #define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
> #define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
> #define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
> #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
> #define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
406,410c405,409
< #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
< #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
< #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
< #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
< #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
---
> #define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
> #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
> #define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
> #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
> #define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
413,415c412,414
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
< #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
---
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
> #define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
417c416
< #if !defined(ENA_DEFS_LINUX_MAINLINE)
---
> #if !defined(DEFS_LINUX_MAINLINE)
857a857,866
> static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_checked(const struct ena_eth_io_rx_cdesc_base *p)
> {
> return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT;
> }
>
> static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_checked(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
> {
> p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_CHECKED_MASK;
> }
>
958c967
< #endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
---
> #endif /* !defined(DEFS_LINUX_MAINLINE) */