1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33#ifndef _ENA_ETH_IO_H_
34#define _ENA_ETH_IO_H_
35
36enum ena_eth_io_l3_proto_index {
37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
38
39 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
40
41 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
42
43 ENA_ETH_IO_L3_PROTO_FCOE = 21,
44
45 ENA_ETH_IO_L3_PROTO_ROCE = 22,
46};
47
48enum ena_eth_io_l4_proto_index {
49 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
50
51 ENA_ETH_IO_L4_PROTO_TCP = 12,
52
53 ENA_ETH_IO_L4_PROTO_UDP = 13,
54
55 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
56};
57
58struct ena_eth_io_tx_desc {
59 /* 15:0 : length - Buffer length in bytes, must
60 * include any packet trailers that the ENA supposed
61 * to update like End-to-End CRC, Authentication GMAC
62 * etc. This length must not include the
63 * 'Push_Buffer' length. This length must not include
64 * the 4-byte added in the end for 802.3 Ethernet FCS
65 * 21:16 : req_id_hi - Request ID[15:10]
66 * 22 : reserved22 - MBZ
67 * 23 : meta_desc - MBZ
68 * 24 : phase
69 * 25 : reserved1 - MBZ
70 * 26 : first - Indicates first descriptor in
71 * transaction
72 * 27 : last - Indicates last descriptor in
73 * transaction
74 * 28 : comp_req - Indicates whether completion
75 * should be posted, after packet is transmitted.
76 * Valid only for first descriptor
77 * 30:29 : reserved29 - MBZ
78 * 31 : reserved31 - MBZ
79 */
80 uint32_t len_ctrl;
81
82 /* 3:0 : l3_proto_idx - L3 protocol. This field
83 * required when l3_csum_en,l3_csum or tso_en are set.
84 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
85 * DF flags of the IPv4 header is 0. Otherwise must
86 * be set to 1
87 * 6:5 : reserved5
88 * 7 : tso_en - Enable TSO, For TCP only.
89 * 12:8 : l4_proto_idx - L4 protocol. This field need
90 * to be set when l4_csum_en or tso_en are set.
91 * 13 : l3_csum_en - enable IPv4 header checksum.
92 * 14 : l4_csum_en - enable TCP/UDP checksum.
93 * 15 : ethernet_fcs_dis - when set, the controller
94 * will not append the 802.3 Ethernet Frame Check
95 * Sequence to the packet
96 * 16 : reserved16
97 * 17 : l4_csum_partial - L4 partial checksum. when
98 * set to 0, the ENA calculates the L4 checksum,
99 * where the Destination Address required for the
100 * TCP/UDP pseudo-header is taken from the actual
101 * packet L3 header. when set to 1, the ENA doesn't
102 * calculate the sum of the pseudo-header, instead,
103 * the checksum field of the L4 is used instead. When
104 * TSO enabled, the checksum of the pseudo-header
105 * must not include the tcp length field. L4 partial
106 * checksum should be used for IPv6 packet that
107 * contains Routing Headers.
108 * 20:18 : reserved18 - MBZ
109 * 21 : reserved21 - MBZ
110 * 31:22 : req_id_lo - Request ID[9:0]
111 */
112 uint32_t meta_ctrl;
113
114 uint32_t buff_addr_lo;
115
116 /* address high and header size
117 * 15:0 : addr_hi - Buffer Pointer[47:32]
118 * 23:16 : reserved16_w2
119 * 31:24 : header_length - Header length. For Low
120 * Latency Queues, this fields indicates the number
121 * of bytes written to the headers' memory. For
122 * normal queues, if packet is TCP or UDP, and longer
123 * than max_header_size, then this field should be
124 * set to the sum of L4 header offset and L4 header
125 * size(without options), otherwise, this field
126 * should be set to 0. For both modes, this field
127 * must not exceed the max_header_size.
128 * max_header_size value is reported by the Max
129 * Queues Feature descriptor
130 */
131 uint32_t buff_addr_hi_hdr_sz;
132};
133
134struct ena_eth_io_tx_meta_desc {
135 /* 9:0 : req_id_lo - Request ID[9:0]
136 * 11:10 : reserved10 - MBZ
137 * 12 : reserved12 - MBZ
138 * 13 : reserved13 - MBZ
139 * 14 : ext_valid - if set, offset fields in Word2
140 * are valid Also MSS High in Word 0 and bits [31:24]
141 * in Word 3
142 * 15 : reserved15
143 * 19:16 : mss_hi
144 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
145 * Extended Metadata Descriptor
146 * 21 : meta_store - Store extended metadata in queue
147 * cache
148 * 22 : reserved22 - MBZ
149 * 23 : meta_desc - MBO
150 * 24 : phase
151 * 25 : reserved25 - MBZ
152 * 26 : first - Indicates first descriptor in
153 * transaction
154 * 27 : last - Indicates last descriptor in
155 * transaction
156 * 28 : comp_req - Indicates whether completion
157 * should be posted, after packet is transmitted.
158 * Valid only for first descriptor
159 * 30:29 : reserved29 - MBZ
160 * 31 : reserved31 - MBZ
161 */
162 uint32_t len_ctrl;
163
164 /* 5:0 : req_id_hi
165 * 31:6 : reserved6 - MBZ
166 */
167 uint32_t word1;
168
169 /* 7:0 : l3_hdr_len
170 * 15:8 : l3_hdr_off
171 * 21:16 : l4_hdr_len_in_words - counts the L4 header
172 * length in words. there is an explicit assumption
173 * that L4 header appears right after L3 header and
174 * L4 offset is based on l3_hdr_off+l3_hdr_len
175 * 31:22 : mss_lo
176 */
177 uint32_t word2;
178
179 uint32_t reserved;
180};
181
182struct ena_eth_io_tx_cdesc {
183 /* Request ID[15:0] */
184 uint16_t req_id;
185
186 uint8_t status;
187
188 /* flags
189 * 0 : phase
190 * 7:1 : reserved1
191 */
192 uint8_t flags;
193
194 uint16_t sub_qid;
195
196 uint16_t sq_head_idx;
197};
198
199struct ena_eth_io_rx_desc {
200 /* In bytes. 0 means 64KB */
201 uint16_t length;
202
203 /* MBZ */
204 uint8_t reserved2;
205
206 /* 0 : phase
207 * 1 : reserved1 - MBZ
208 * 2 : first - Indicates first descriptor in
209 * transaction
210 * 3 : last - Indicates last descriptor in transaction
211 * 4 : comp_req
212 * 5 : reserved5 - MBO
213 * 7:6 : reserved6 - MBZ
214 */
215 uint8_t ctrl;
216
217 uint16_t req_id;
218
219 /* MBZ */
220 uint16_t reserved6;
221
222 uint32_t buff_addr_lo;
223
224 uint16_t buff_addr_hi;
225
226 /* MBZ */
227 uint16_t reserved16_w3;
228};
229
230/* 4-word format Note: all ethernet parsing information are valid only when
231 * last=1
232 */
233struct ena_eth_io_rx_cdesc_base {
234 /* 4:0 : l3_proto_idx
235 * 6:5 : src_vlan_cnt
236 * 7 : reserved7 - MBZ
237 * 12:8 : l4_proto_idx
238 * 13 : l3_csum_err - when set, either the L3
239 * checksum error detected, or, the controller didn't
240 * validate the checksum. This bit is valid only when
241 * l3_proto_idx indicates IPv4 packet
242 * 14 : l4_csum_err - when set, either the L4
243 * checksum error detected, or, the controller didn't
244 * validate the checksum. This bit is valid only when
245 * l4_proto_idx indicates TCP/UDP packet, and,
246 * ipv4_frag is not set
247 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
248 * 23:16 : reserved16
249 * 24 : phase
250 * 25 : l3_csum2 - second checksum engine result
251 * 26 : first - Indicates first descriptor in
252 * transaction
253 * 27 : last - Indicates last descriptor in
254 * transaction
255 * 29:28 : reserved28
256 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
257 * Descriptor was used
258 * 31 : reserved31
259 */
260 uint32_t status;
261
262 uint16_t length;
263
264 uint16_t req_id;
265
266 /* 32-bit hash result */
267 uint32_t hash;
268
269 uint16_t sub_qid;
270
271 uint16_t reserved;
272};
273
274/* 8-word format */
275struct ena_eth_io_rx_cdesc_ext {
276 struct ena_eth_io_rx_cdesc_base base;
277
278 uint32_t buff_addr_lo;
279
280 uint16_t buff_addr_hi;
281
282 uint16_t reserved16;
283
284 uint32_t reserved_w6;
285
286 uint32_t reserved_w7;
287};
288
289struct ena_eth_io_intr_reg {
290 /* 14:0 : rx_intr_delay
291 * 29:15 : tx_intr_delay
292 * 30 : intr_unmask
293 * 31 : reserved
294 */
295 uint32_t intr_control;
296};
297
298struct ena_eth_io_numa_node_cfg_reg {
299 /* 7:0 : numa
300 * 30:8 : reserved
301 * 31 : enabled
302 */
303 uint32_t numa_cfg;
304};
305
306/* tx_desc */
307#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
308#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
309#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
310#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
311#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
312#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
313#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
314#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
315#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
316#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
317#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
318#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
319#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
320#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
321#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
322#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
323#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
324#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
325#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
326#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
327#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
328#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
329#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
330#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
331#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
332#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
333#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
334#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
335#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
336#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
337#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
338#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
339#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
340
341/* tx_meta_desc */
342#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
343#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
344#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
345#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
346#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
347#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
348#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
349#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
350#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
351#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
352#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
353#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
354#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
355#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
356#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
357#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
358#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
359#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
360#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
361#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
362#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
363#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
364#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
365#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
366#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
367#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
368#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
369
370/* tx_cdesc */
371#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
372
373/* rx_desc */
374#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
375#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
376#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
377#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
378#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
379#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
380#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
381
382/* rx_cdesc_base */
383#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
384#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
385#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
386#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
387#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
388#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
389#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
390#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
392#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
393#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
394#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
395#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
396#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
397#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
398#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
399#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
400#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
401#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
402#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
403#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
404
405/* intr_reg */
406#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
407#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
408#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
409#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
410#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
411
412/* numa_node_cfg_reg */
413#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
415#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
416
417#if !defined(ENA_DEFS_LINUX_MAINLINE)
418static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)
419{
420 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
421}
422
423static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)
424{
425 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
426}
427
428static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p)
429{
430 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;
431}
432
433static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
434{
435 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
436}
437
438static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p)
439{
440 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;
441}
442
443static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val)
444{
445 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK;
446}
447
448static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p)
449{
450 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;
451}
452
453static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val)
454{
455 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK;
456}
457
458static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p)
459{
460 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;
461}
462
463static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val)
464{
465 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK;
466}
467
468static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p)
469{
470 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;
471}
472
473static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val)
474{
475 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK;
476}
477
478static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p)
479{
480 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;
481}
482
483static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val)
484{
485 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
486}
487
488static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p)
489{
490 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
491}
492
493static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
494{
495 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
496}
497
498static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p)
499{
500 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT;
501}
502
503static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val)
504{
505 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK;
506}
507
508static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p)
509{
510 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;
511}
512
513static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val)
514{
515 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
516}
517
518static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p)
519{
520 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;
521}
522
523static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
524{
525 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
526}
527
528static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p)
529{
530 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;
531}
532
533static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
534{
535 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
536}
537
538static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p)
539{
540 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;
541}
542
543static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
544{
545 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
546}
547
548static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p)
549{
550 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;
551}
552
553static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val)
554{
555 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;
556}
557
558static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p)
559{
560 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;
561}
562
563static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val)
564{
565 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
566}
567
568static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p)
569{
570 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;
571}
572
573static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val)
574{
575 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
576}
577
578static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p)
579{
580 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
581}
582
583static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
584{
585 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
586}
587
588static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p)
589{
590 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;
591}
592
593static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val)
594{
595 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
596}
597
598static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p)
599{
600 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
601}
602
603static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
604{
605 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
606}
607
608static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p)
609{
610 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;
611}
612
613static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
614{
615 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
616}
617
618static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p)
619{
620 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT;
621}
622
623static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
624{
625 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
626}
627
628static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p)
629{
630 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;
631}
632
633static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
634{
635 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
636}
637
638static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p)
639{
640 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;
641}
642
643static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
644{
645 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
646}
647
648static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p)
649{
650 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;
651}
652
653static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
654{
655 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
656}
657
658static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p)
659{
660 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;
661}
662
663static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
664{
665 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
666}
667
668static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p)
669{
670 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;
671}
672
673static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
674{
675 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
676}
677
678static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p)
679{
680 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;
681}
682
683static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
684{
685 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK;
686}
687
688static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p)
689{
690 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;
691}
692
693static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
694{
695 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
696}
697
698static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p)
699{
700 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
701}
702
703static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
704{
705 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
706}
707
708static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p)
709{
710 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
711}
712
713static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
714{
715 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
716}
717
718static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p)
719{
720 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;
721}
722
723static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
724{
725 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
726}
727
728static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p)
729{
730 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;
731}
732
733static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
734{
735 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
736}
737
738static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p)
739{
740 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;
741}
742
743static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
744{
745 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
746}
747
748static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p)
749{
750 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
751}
752
753static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val)
754{
755 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
756}
757
758static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)
759{
760 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
761}
762
763static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val)
764{
765 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;
766}
767
768static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p)
769{
770 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;
771}
772
773static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val)
774{
775 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK;
776}
777
778static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p)
779{
780 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;
781}
782
783static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val)
784{
785 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK;
786}
787
788static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p)
789{
790 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;
791}
792
793static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val)
794{
795 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
796}
797
798static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
799{
800 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
801}
802
803static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
804{
805 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
806}
807
808static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p)
809{
810 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;
811}
812
813static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
814{
815 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
816}
817
818static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
819{
820 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
821}
822
823static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
824{
825 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
826}
827
828static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
829{
830 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
831}
832
833static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
834{
835 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
836}
837
838static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
839{
840 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
841}
842
843static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
844{
845 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
846}
847
848static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p)
849{
850 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
851}
852
853static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
854{
855 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
856}
857
858static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
859{
860 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
861}
862
863static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
864{
865 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
866}
867
868static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p)
869{
870 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;
871}
872
873static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
874{
875 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
876}
877
878static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p)
879{
880 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;
881}
882
883static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
884{
885 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
886}
887
888static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p)
889{
890 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
891}
892
893static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
894{
895 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
896}
897
898static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p)
899{
900 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;
901}
902
903static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
904{
905 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
906}
907
908static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p)
909{
910 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
911}
912
913static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
914{
915 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
916}
917
918static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p)
919{
920 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;
921}
922
923static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
924{
925 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
926}
927
928static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p)
929{
930 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;
931}
932
933static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val)
934{
935 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
936}
937
938static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p)
939{
940 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
941}
942
943static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
944{
945 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
946}
947
948static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p)
949{
950 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
951}
952
953static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
954{
955 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
956}
957
958#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
959#endif /*_ENA_ETH_IO_H_ */
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33#ifndef _ENA_ETH_IO_H_
34#define _ENA_ETH_IO_H_
35
36enum ena_eth_io_l3_proto_index {
37 ENA_ETH_IO_L3_PROTO_UNKNOWN = 0,
38
39 ENA_ETH_IO_L3_PROTO_IPV4 = 8,
40
41 ENA_ETH_IO_L3_PROTO_IPV6 = 11,
42
43 ENA_ETH_IO_L3_PROTO_FCOE = 21,
44
45 ENA_ETH_IO_L3_PROTO_ROCE = 22,
46};
47
48enum ena_eth_io_l4_proto_index {
49 ENA_ETH_IO_L4_PROTO_UNKNOWN = 0,
50
51 ENA_ETH_IO_L4_PROTO_TCP = 12,
52
53 ENA_ETH_IO_L4_PROTO_UDP = 13,
54
55 ENA_ETH_IO_L4_PROTO_ROUTEABLE_ROCE = 23,
56};
57
58struct ena_eth_io_tx_desc {
59 /* 15:0 : length - Buffer length in bytes, must
60 * include any packet trailers that the ENA supposed
61 * to update like End-to-End CRC, Authentication GMAC
62 * etc. This length must not include the
63 * 'Push_Buffer' length. This length must not include
64 * the 4-byte added in the end for 802.3 Ethernet FCS
65 * 21:16 : req_id_hi - Request ID[15:10]
66 * 22 : reserved22 - MBZ
67 * 23 : meta_desc - MBZ
68 * 24 : phase
69 * 25 : reserved1 - MBZ
70 * 26 : first - Indicates first descriptor in
71 * transaction
72 * 27 : last - Indicates last descriptor in
73 * transaction
74 * 28 : comp_req - Indicates whether completion
75 * should be posted, after packet is transmitted.
76 * Valid only for first descriptor
77 * 30:29 : reserved29 - MBZ
78 * 31 : reserved31 - MBZ
79 */
80 uint32_t len_ctrl;
81
82 /* 3:0 : l3_proto_idx - L3 protocol. This field
83 * required when l3_csum_en,l3_csum or tso_en are set.
84 * 4 : DF - IPv4 DF, must be 0 if packet is IPv4 and
85 * DF flags of the IPv4 header is 0. Otherwise must
86 * be set to 1
87 * 6:5 : reserved5
88 * 7 : tso_en - Enable TSO, For TCP only.
89 * 12:8 : l4_proto_idx - L4 protocol. This field need
90 * to be set when l4_csum_en or tso_en are set.
91 * 13 : l3_csum_en - enable IPv4 header checksum.
92 * 14 : l4_csum_en - enable TCP/UDP checksum.
93 * 15 : ethernet_fcs_dis - when set, the controller
94 * will not append the 802.3 Ethernet Frame Check
95 * Sequence to the packet
96 * 16 : reserved16
97 * 17 : l4_csum_partial - L4 partial checksum. when
98 * set to 0, the ENA calculates the L4 checksum,
99 * where the Destination Address required for the
100 * TCP/UDP pseudo-header is taken from the actual
101 * packet L3 header. when set to 1, the ENA doesn't
102 * calculate the sum of the pseudo-header, instead,
103 * the checksum field of the L4 is used instead. When
104 * TSO enabled, the checksum of the pseudo-header
105 * must not include the tcp length field. L4 partial
106 * checksum should be used for IPv6 packet that
107 * contains Routing Headers.
108 * 20:18 : reserved18 - MBZ
109 * 21 : reserved21 - MBZ
110 * 31:22 : req_id_lo - Request ID[9:0]
111 */
112 uint32_t meta_ctrl;
113
114 uint32_t buff_addr_lo;
115
116 /* address high and header size
117 * 15:0 : addr_hi - Buffer Pointer[47:32]
118 * 23:16 : reserved16_w2
119 * 31:24 : header_length - Header length. For Low
120 * Latency Queues, this fields indicates the number
121 * of bytes written to the headers' memory. For
122 * normal queues, if packet is TCP or UDP, and longer
123 * than max_header_size, then this field should be
124 * set to the sum of L4 header offset and L4 header
125 * size(without options), otherwise, this field
126 * should be set to 0. For both modes, this field
127 * must not exceed the max_header_size.
128 * max_header_size value is reported by the Max
129 * Queues Feature descriptor
130 */
131 uint32_t buff_addr_hi_hdr_sz;
132};
133
134struct ena_eth_io_tx_meta_desc {
135 /* 9:0 : req_id_lo - Request ID[9:0]
136 * 11:10 : reserved10 - MBZ
137 * 12 : reserved12 - MBZ
138 * 13 : reserved13 - MBZ
139 * 14 : ext_valid - if set, offset fields in Word2
140 * are valid Also MSS High in Word 0 and bits [31:24]
141 * in Word 3
142 * 15 : reserved15
143 * 19:16 : mss_hi
144 * 20 : eth_meta_type - 0: Tx Metadata Descriptor, 1:
145 * Extended Metadata Descriptor
146 * 21 : meta_store - Store extended metadata in queue
147 * cache
148 * 22 : reserved22 - MBZ
149 * 23 : meta_desc - MBO
150 * 24 : phase
151 * 25 : reserved25 - MBZ
152 * 26 : first - Indicates first descriptor in
153 * transaction
154 * 27 : last - Indicates last descriptor in
155 * transaction
156 * 28 : comp_req - Indicates whether completion
157 * should be posted, after packet is transmitted.
158 * Valid only for first descriptor
159 * 30:29 : reserved29 - MBZ
160 * 31 : reserved31 - MBZ
161 */
162 uint32_t len_ctrl;
163
164 /* 5:0 : req_id_hi
165 * 31:6 : reserved6 - MBZ
166 */
167 uint32_t word1;
168
169 /* 7:0 : l3_hdr_len
170 * 15:8 : l3_hdr_off
171 * 21:16 : l4_hdr_len_in_words - counts the L4 header
172 * length in words. there is an explicit assumption
173 * that L4 header appears right after L3 header and
174 * L4 offset is based on l3_hdr_off+l3_hdr_len
175 * 31:22 : mss_lo
176 */
177 uint32_t word2;
178
179 uint32_t reserved;
180};
181
182struct ena_eth_io_tx_cdesc {
183 /* Request ID[15:0] */
184 uint16_t req_id;
185
186 uint8_t status;
187
188 /* flags
189 * 0 : phase
190 * 7:1 : reserved1
191 */
192 uint8_t flags;
193
194 uint16_t sub_qid;
195
196 uint16_t sq_head_idx;
197};
198
199struct ena_eth_io_rx_desc {
200 /* In bytes. 0 means 64KB */
201 uint16_t length;
202
203 /* MBZ */
204 uint8_t reserved2;
205
206 /* 0 : phase
207 * 1 : reserved1 - MBZ
208 * 2 : first - Indicates first descriptor in
209 * transaction
210 * 3 : last - Indicates last descriptor in transaction
211 * 4 : comp_req
212 * 5 : reserved5 - MBO
213 * 7:6 : reserved6 - MBZ
214 */
215 uint8_t ctrl;
216
217 uint16_t req_id;
218
219 /* MBZ */
220 uint16_t reserved6;
221
222 uint32_t buff_addr_lo;
223
224 uint16_t buff_addr_hi;
225
226 /* MBZ */
227 uint16_t reserved16_w3;
228};
229
230/* 4-word format Note: all ethernet parsing information are valid only when
231 * last=1
232 */
233struct ena_eth_io_rx_cdesc_base {
234 /* 4:0 : l3_proto_idx
235 * 6:5 : src_vlan_cnt
236 * 7 : reserved7 - MBZ
237 * 12:8 : l4_proto_idx
238 * 13 : l3_csum_err - when set, either the L3
239 * checksum error detected, or, the controller didn't
240 * validate the checksum. This bit is valid only when
241 * l3_proto_idx indicates IPv4 packet
242 * 14 : l4_csum_err - when set, either the L4
243 * checksum error detected, or, the controller didn't
244 * validate the checksum. This bit is valid only when
245 * l4_proto_idx indicates TCP/UDP packet, and,
246 * ipv4_frag is not set
247 * 15 : ipv4_frag - Indicates IPv4 fragmented packet
248 * 23:16 : reserved16
249 * 24 : phase
250 * 25 : l3_csum2 - second checksum engine result
251 * 26 : first - Indicates first descriptor in
252 * transaction
253 * 27 : last - Indicates last descriptor in
254 * transaction
255 * 29:28 : reserved28
256 * 30 : buffer - 0: Metadata descriptor. 1: Buffer
257 * Descriptor was used
258 * 31 : reserved31
259 */
260 uint32_t status;
261
262 uint16_t length;
263
264 uint16_t req_id;
265
266 /* 32-bit hash result */
267 uint32_t hash;
268
269 uint16_t sub_qid;
270
271 uint16_t reserved;
272};
273
274/* 8-word format */
275struct ena_eth_io_rx_cdesc_ext {
276 struct ena_eth_io_rx_cdesc_base base;
277
278 uint32_t buff_addr_lo;
279
280 uint16_t buff_addr_hi;
281
282 uint16_t reserved16;
283
284 uint32_t reserved_w6;
285
286 uint32_t reserved_w7;
287};
288
289struct ena_eth_io_intr_reg {
290 /* 14:0 : rx_intr_delay
291 * 29:15 : tx_intr_delay
292 * 30 : intr_unmask
293 * 31 : reserved
294 */
295 uint32_t intr_control;
296};
297
298struct ena_eth_io_numa_node_cfg_reg {
299 /* 7:0 : numa
300 * 30:8 : reserved
301 * 31 : enabled
302 */
303 uint32_t numa_cfg;
304};
305
306/* tx_desc */
307#define ENA_ETH_IO_TX_DESC_LENGTH_MASK GENMASK(15, 0)
308#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT 16
309#define ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK GENMASK(21, 16)
310#define ENA_ETH_IO_TX_DESC_META_DESC_SHIFT 23
311#define ENA_ETH_IO_TX_DESC_META_DESC_MASK BIT(23)
312#define ENA_ETH_IO_TX_DESC_PHASE_SHIFT 24
313#define ENA_ETH_IO_TX_DESC_PHASE_MASK BIT(24)
314#define ENA_ETH_IO_TX_DESC_FIRST_SHIFT 26
315#define ENA_ETH_IO_TX_DESC_FIRST_MASK BIT(26)
316#define ENA_ETH_IO_TX_DESC_LAST_SHIFT 27
317#define ENA_ETH_IO_TX_DESC_LAST_MASK BIT(27)
318#define ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT 28
319#define ENA_ETH_IO_TX_DESC_COMP_REQ_MASK BIT(28)
320#define ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK GENMASK(3, 0)
321#define ENA_ETH_IO_TX_DESC_DF_SHIFT 4
322#define ENA_ETH_IO_TX_DESC_DF_MASK BIT(4)
323#define ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT 7
324#define ENA_ETH_IO_TX_DESC_TSO_EN_MASK BIT(7)
325#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT 8
326#define ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK GENMASK(12, 8)
327#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT 13
328#define ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK BIT(13)
329#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT 14
330#define ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK BIT(14)
331#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT 15
332#define ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK BIT(15)
333#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT 17
334#define ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK BIT(17)
335#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT 22
336#define ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK GENMASK(31, 22)
337#define ENA_ETH_IO_TX_DESC_ADDR_HI_MASK GENMASK(15, 0)
338#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT 24
339#define ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK GENMASK(31, 24)
340
341/* tx_meta_desc */
342#define ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK GENMASK(9, 0)
343#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT 14
344#define ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK BIT(14)
345#define ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT 16
346#define ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK GENMASK(19, 16)
347#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT 20
348#define ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK BIT(20)
349#define ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT 21
350#define ENA_ETH_IO_TX_META_DESC_META_STORE_MASK BIT(21)
351#define ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT 23
352#define ENA_ETH_IO_TX_META_DESC_META_DESC_MASK BIT(23)
353#define ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT 24
354#define ENA_ETH_IO_TX_META_DESC_PHASE_MASK BIT(24)
355#define ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT 26
356#define ENA_ETH_IO_TX_META_DESC_FIRST_MASK BIT(26)
357#define ENA_ETH_IO_TX_META_DESC_LAST_SHIFT 27
358#define ENA_ETH_IO_TX_META_DESC_LAST_MASK BIT(27)
359#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT 28
360#define ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK BIT(28)
361#define ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK GENMASK(5, 0)
362#define ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK GENMASK(7, 0)
363#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT 8
364#define ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK GENMASK(15, 8)
365#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT 16
366#define ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK GENMASK(21, 16)
367#define ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT 22
368#define ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK GENMASK(31, 22)
369
370/* tx_cdesc */
371#define ENA_ETH_IO_TX_CDESC_PHASE_MASK BIT(0)
372
373/* rx_desc */
374#define ENA_ETH_IO_RX_DESC_PHASE_MASK BIT(0)
375#define ENA_ETH_IO_RX_DESC_FIRST_SHIFT 2
376#define ENA_ETH_IO_RX_DESC_FIRST_MASK BIT(2)
377#define ENA_ETH_IO_RX_DESC_LAST_SHIFT 3
378#define ENA_ETH_IO_RX_DESC_LAST_MASK BIT(3)
379#define ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT 4
380#define ENA_ETH_IO_RX_DESC_COMP_REQ_MASK BIT(4)
381
382/* rx_cdesc_base */
383#define ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK GENMASK(4, 0)
384#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT 5
385#define ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK GENMASK(6, 5)
386#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT 8
387#define ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK GENMASK(12, 8)
388#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT 13
389#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK BIT(13)
390#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT 14
391#define ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK BIT(14)
392#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT 15
393#define ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK BIT(15)
394#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT 24
395#define ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK BIT(24)
396#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT 25
397#define ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK BIT(25)
398#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT 26
399#define ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK BIT(26)
400#define ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT 27
401#define ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK BIT(27)
402#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT 30
403#define ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK BIT(30)
404
405/* intr_reg */
406#define ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK GENMASK(14, 0)
407#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT 15
408#define ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK GENMASK(29, 15)
409#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT 30
410#define ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK BIT(30)
411
412/* numa_node_cfg_reg */
413#define ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK GENMASK(7, 0)
414#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT 31
415#define ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK BIT(31)
416
417#if !defined(ENA_DEFS_LINUX_MAINLINE)
418static inline uint32_t get_ena_eth_io_tx_desc_length(const struct ena_eth_io_tx_desc *p)
419{
420 return p->len_ctrl & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
421}
422
423static inline void set_ena_eth_io_tx_desc_length(struct ena_eth_io_tx_desc *p, uint32_t val)
424{
425 p->len_ctrl |= val & ENA_ETH_IO_TX_DESC_LENGTH_MASK;
426}
427
428static inline uint32_t get_ena_eth_io_tx_desc_req_id_hi(const struct ena_eth_io_tx_desc *p)
429{
430 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT;
431}
432
433static inline void set_ena_eth_io_tx_desc_req_id_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
434{
435 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_HI_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_HI_MASK;
436}
437
438static inline uint32_t get_ena_eth_io_tx_desc_meta_desc(const struct ena_eth_io_tx_desc *p)
439{
440 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_DESC_META_DESC_SHIFT;
441}
442
443static inline void set_ena_eth_io_tx_desc_meta_desc(struct ena_eth_io_tx_desc *p, uint32_t val)
444{
445 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_DESC_META_DESC_MASK;
446}
447
448static inline uint32_t get_ena_eth_io_tx_desc_phase(const struct ena_eth_io_tx_desc *p)
449{
450 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_DESC_PHASE_SHIFT;
451}
452
453static inline void set_ena_eth_io_tx_desc_phase(struct ena_eth_io_tx_desc *p, uint32_t val)
454{
455 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_DESC_PHASE_MASK;
456}
457
458static inline uint32_t get_ena_eth_io_tx_desc_first(const struct ena_eth_io_tx_desc *p)
459{
460 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_DESC_FIRST_SHIFT;
461}
462
463static inline void set_ena_eth_io_tx_desc_first(struct ena_eth_io_tx_desc *p, uint32_t val)
464{
465 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_DESC_FIRST_MASK;
466}
467
468static inline uint32_t get_ena_eth_io_tx_desc_last(const struct ena_eth_io_tx_desc *p)
469{
470 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_LAST_MASK) >> ENA_ETH_IO_TX_DESC_LAST_SHIFT;
471}
472
473static inline void set_ena_eth_io_tx_desc_last(struct ena_eth_io_tx_desc *p, uint32_t val)
474{
475 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_DESC_LAST_MASK;
476}
477
478static inline uint32_t get_ena_eth_io_tx_desc_comp_req(const struct ena_eth_io_tx_desc *p)
479{
480 return (p->len_ctrl & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT;
481}
482
483static inline void set_ena_eth_io_tx_desc_comp_req(struct ena_eth_io_tx_desc *p, uint32_t val)
484{
485 p->len_ctrl |= (val << ENA_ETH_IO_TX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_DESC_COMP_REQ_MASK;
486}
487
488static inline uint32_t get_ena_eth_io_tx_desc_l3_proto_idx(const struct ena_eth_io_tx_desc *p)
489{
490 return p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
491}
492
493static inline void set_ena_eth_io_tx_desc_l3_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
494{
495 p->meta_ctrl |= val & ENA_ETH_IO_TX_DESC_L3_PROTO_IDX_MASK;
496}
497
498static inline uint32_t get_ena_eth_io_tx_desc_DF(const struct ena_eth_io_tx_desc *p)
499{
500 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_DF_MASK) >> ENA_ETH_IO_TX_DESC_DF_SHIFT;
501}
502
503static inline void set_ena_eth_io_tx_desc_DF(struct ena_eth_io_tx_desc *p, uint32_t val)
504{
505 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_DF_SHIFT) & ENA_ETH_IO_TX_DESC_DF_MASK;
506}
507
508static inline uint32_t get_ena_eth_io_tx_desc_tso_en(const struct ena_eth_io_tx_desc *p)
509{
510 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_TSO_EN_MASK) >> ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT;
511}
512
513static inline void set_ena_eth_io_tx_desc_tso_en(struct ena_eth_io_tx_desc *p, uint32_t val)
514{
515 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_TSO_EN_SHIFT) & ENA_ETH_IO_TX_DESC_TSO_EN_MASK;
516}
517
518static inline uint32_t get_ena_eth_io_tx_desc_l4_proto_idx(const struct ena_eth_io_tx_desc *p)
519{
520 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT;
521}
522
523static inline void set_ena_eth_io_tx_desc_l4_proto_idx(struct ena_eth_io_tx_desc *p, uint32_t val)
524{
525 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_TX_DESC_L4_PROTO_IDX_MASK;
526}
527
528static inline uint32_t get_ena_eth_io_tx_desc_l3_csum_en(const struct ena_eth_io_tx_desc *p)
529{
530 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT;
531}
532
533static inline void set_ena_eth_io_tx_desc_l3_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
534{
535 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L3_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L3_CSUM_EN_MASK;
536}
537
538static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_en(const struct ena_eth_io_tx_desc *p)
539{
540 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT;
541}
542
543static inline void set_ena_eth_io_tx_desc_l4_csum_en(struct ena_eth_io_tx_desc *p, uint32_t val)
544{
545 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_EN_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_EN_MASK;
546}
547
548static inline uint32_t get_ena_eth_io_tx_desc_ethernet_fcs_dis(const struct ena_eth_io_tx_desc *p)
549{
550 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK) >> ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT;
551}
552
553static inline void set_ena_eth_io_tx_desc_ethernet_fcs_dis(struct ena_eth_io_tx_desc *p, uint32_t val)
554{
555 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_SHIFT) & ENA_ETH_IO_TX_DESC_ETHERNET_FCS_DIS_MASK;
556}
557
558static inline uint32_t get_ena_eth_io_tx_desc_l4_csum_partial(const struct ena_eth_io_tx_desc *p)
559{
560 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK) >> ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT;
561}
562
563static inline void set_ena_eth_io_tx_desc_l4_csum_partial(struct ena_eth_io_tx_desc *p, uint32_t val)
564{
565 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_SHIFT) & ENA_ETH_IO_TX_DESC_L4_CSUM_PARTIAL_MASK;
566}
567
568static inline uint32_t get_ena_eth_io_tx_desc_req_id_lo(const struct ena_eth_io_tx_desc *p)
569{
570 return (p->meta_ctrl & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK) >> ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT;
571}
572
573static inline void set_ena_eth_io_tx_desc_req_id_lo(struct ena_eth_io_tx_desc *p, uint32_t val)
574{
575 p->meta_ctrl |= (val << ENA_ETH_IO_TX_DESC_REQ_ID_LO_SHIFT) & ENA_ETH_IO_TX_DESC_REQ_ID_LO_MASK;
576}
577
578static inline uint32_t get_ena_eth_io_tx_desc_addr_hi(const struct ena_eth_io_tx_desc *p)
579{
580 return p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
581}
582
583static inline void set_ena_eth_io_tx_desc_addr_hi(struct ena_eth_io_tx_desc *p, uint32_t val)
584{
585 p->buff_addr_hi_hdr_sz |= val & ENA_ETH_IO_TX_DESC_ADDR_HI_MASK;
586}
587
588static inline uint32_t get_ena_eth_io_tx_desc_header_length(const struct ena_eth_io_tx_desc *p)
589{
590 return (p->buff_addr_hi_hdr_sz & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK) >> ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT;
591}
592
593static inline void set_ena_eth_io_tx_desc_header_length(struct ena_eth_io_tx_desc *p, uint32_t val)
594{
595 p->buff_addr_hi_hdr_sz |= (val << ENA_ETH_IO_TX_DESC_HEADER_LENGTH_SHIFT) & ENA_ETH_IO_TX_DESC_HEADER_LENGTH_MASK;
596}
597
598static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_lo(const struct ena_eth_io_tx_meta_desc *p)
599{
600 return p->len_ctrl & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
601}
602
603static inline void set_ena_eth_io_tx_meta_desc_req_id_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
604{
605 p->len_ctrl |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_LO_MASK;
606}
607
608static inline uint32_t get_ena_eth_io_tx_meta_desc_ext_valid(const struct ena_eth_io_tx_meta_desc *p)
609{
610 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK) >> ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT;
611}
612
613static inline void set_ena_eth_io_tx_meta_desc_ext_valid(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
614{
615 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_EXT_VALID_SHIFT) & ENA_ETH_IO_TX_META_DESC_EXT_VALID_MASK;
616}
617
618static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_hi(const struct ena_eth_io_tx_meta_desc *p)
619{
620 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT;
621}
622
623static inline void set_ena_eth_io_tx_meta_desc_mss_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
624{
625 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
626}
627
628static inline uint32_t get_ena_eth_io_tx_meta_desc_eth_meta_type(const struct ena_eth_io_tx_meta_desc *p)
629{
630 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK) >> ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT;
631}
632
633static inline void set_ena_eth_io_tx_meta_desc_eth_meta_type(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
634{
635 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_SHIFT) & ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
636}
637
638static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_store(const struct ena_eth_io_tx_meta_desc *p)
639{
640 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK) >> ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT;
641}
642
643static inline void set_ena_eth_io_tx_meta_desc_meta_store(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
644{
645 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_STORE_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_STORE_MASK;
646}
647
648static inline uint32_t get_ena_eth_io_tx_meta_desc_meta_desc(const struct ena_eth_io_tx_meta_desc *p)
649{
650 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK) >> ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT;
651}
652
653static inline void set_ena_eth_io_tx_meta_desc_meta_desc(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
654{
655 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_META_DESC_SHIFT) & ENA_ETH_IO_TX_META_DESC_META_DESC_MASK;
656}
657
658static inline uint32_t get_ena_eth_io_tx_meta_desc_phase(const struct ena_eth_io_tx_meta_desc *p)
659{
660 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_PHASE_MASK) >> ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT;
661}
662
663static inline void set_ena_eth_io_tx_meta_desc_phase(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
664{
665 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_PHASE_SHIFT) & ENA_ETH_IO_TX_META_DESC_PHASE_MASK;
666}
667
668static inline uint32_t get_ena_eth_io_tx_meta_desc_first(const struct ena_eth_io_tx_meta_desc *p)
669{
670 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_FIRST_MASK) >> ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT;
671}
672
673static inline void set_ena_eth_io_tx_meta_desc_first(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
674{
675 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_FIRST_SHIFT) & ENA_ETH_IO_TX_META_DESC_FIRST_MASK;
676}
677
678static inline uint32_t get_ena_eth_io_tx_meta_desc_last(const struct ena_eth_io_tx_meta_desc *p)
679{
680 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_LAST_MASK) >> ENA_ETH_IO_TX_META_DESC_LAST_SHIFT;
681}
682
683static inline void set_ena_eth_io_tx_meta_desc_last(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
684{
685 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_LAST_SHIFT) & ENA_ETH_IO_TX_META_DESC_LAST_MASK;
686}
687
688static inline uint32_t get_ena_eth_io_tx_meta_desc_comp_req(const struct ena_eth_io_tx_meta_desc *p)
689{
690 return (p->len_ctrl & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT;
691}
692
693static inline void set_ena_eth_io_tx_meta_desc_comp_req(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
694{
695 p->len_ctrl |= (val << ENA_ETH_IO_TX_META_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_TX_META_DESC_COMP_REQ_MASK;
696}
697
698static inline uint32_t get_ena_eth_io_tx_meta_desc_req_id_hi(const struct ena_eth_io_tx_meta_desc *p)
699{
700 return p->word1 & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
701}
702
703static inline void set_ena_eth_io_tx_meta_desc_req_id_hi(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
704{
705 p->word1 |= val & ENA_ETH_IO_TX_META_DESC_REQ_ID_HI_MASK;
706}
707
708static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_len(const struct ena_eth_io_tx_meta_desc *p)
709{
710 return p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
711}
712
713static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_len(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
714{
715 p->word2 |= val & ENA_ETH_IO_TX_META_DESC_L3_HDR_LEN_MASK;
716}
717
718static inline uint32_t get_ena_eth_io_tx_meta_desc_l3_hdr_off(const struct ena_eth_io_tx_meta_desc *p)
719{
720 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK) >> ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT;
721}
722
723static inline void set_ena_eth_io_tx_meta_desc_l3_hdr_off(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
724{
725 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_SHIFT) & ENA_ETH_IO_TX_META_DESC_L3_HDR_OFF_MASK;
726}
727
728static inline uint32_t get_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(const struct ena_eth_io_tx_meta_desc *p)
729{
730 return (p->word2 & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK) >> ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT;
731}
732
733static inline void set_ena_eth_io_tx_meta_desc_l4_hdr_len_in_words(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
734{
735 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_SHIFT) & ENA_ETH_IO_TX_META_DESC_L4_HDR_LEN_IN_WORDS_MASK;
736}
737
738static inline uint32_t get_ena_eth_io_tx_meta_desc_mss_lo(const struct ena_eth_io_tx_meta_desc *p)
739{
740 return (p->word2 & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK) >> ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT;
741}
742
743static inline void set_ena_eth_io_tx_meta_desc_mss_lo(struct ena_eth_io_tx_meta_desc *p, uint32_t val)
744{
745 p->word2 |= (val << ENA_ETH_IO_TX_META_DESC_MSS_LO_SHIFT) & ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
746}
747
748static inline uint8_t get_ena_eth_io_tx_cdesc_phase(const struct ena_eth_io_tx_cdesc *p)
749{
750 return p->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
751}
752
753static inline void set_ena_eth_io_tx_cdesc_phase(struct ena_eth_io_tx_cdesc *p, uint8_t val)
754{
755 p->flags |= val & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
756}
757
758static inline uint8_t get_ena_eth_io_rx_desc_phase(const struct ena_eth_io_rx_desc *p)
759{
760 return p->ctrl & ENA_ETH_IO_RX_DESC_PHASE_MASK;
761}
762
763static inline void set_ena_eth_io_rx_desc_phase(struct ena_eth_io_rx_desc *p, uint8_t val)
764{
765 p->ctrl |= val & ENA_ETH_IO_RX_DESC_PHASE_MASK;
766}
767
768static inline uint8_t get_ena_eth_io_rx_desc_first(const struct ena_eth_io_rx_desc *p)
769{
770 return (p->ctrl & ENA_ETH_IO_RX_DESC_FIRST_MASK) >> ENA_ETH_IO_RX_DESC_FIRST_SHIFT;
771}
772
773static inline void set_ena_eth_io_rx_desc_first(struct ena_eth_io_rx_desc *p, uint8_t val)
774{
775 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_FIRST_SHIFT) & ENA_ETH_IO_RX_DESC_FIRST_MASK;
776}
777
778static inline uint8_t get_ena_eth_io_rx_desc_last(const struct ena_eth_io_rx_desc *p)
779{
780 return (p->ctrl & ENA_ETH_IO_RX_DESC_LAST_MASK) >> ENA_ETH_IO_RX_DESC_LAST_SHIFT;
781}
782
783static inline void set_ena_eth_io_rx_desc_last(struct ena_eth_io_rx_desc *p, uint8_t val)
784{
785 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_LAST_SHIFT) & ENA_ETH_IO_RX_DESC_LAST_MASK;
786}
787
788static inline uint8_t get_ena_eth_io_rx_desc_comp_req(const struct ena_eth_io_rx_desc *p)
789{
790 return (p->ctrl & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK) >> ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT;
791}
792
793static inline void set_ena_eth_io_rx_desc_comp_req(struct ena_eth_io_rx_desc *p, uint8_t val)
794{
795 p->ctrl |= (val << ENA_ETH_IO_RX_DESC_COMP_REQ_SHIFT) & ENA_ETH_IO_RX_DESC_COMP_REQ_MASK;
796}
797
798static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
799{
800 return p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
801}
802
803static inline void set_ena_eth_io_rx_cdesc_base_l3_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
804{
805 p->status |= val & ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
806}
807
808static inline uint32_t get_ena_eth_io_rx_cdesc_base_src_vlan_cnt(const struct ena_eth_io_rx_cdesc_base *p)
809{
810 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT;
811}
812
813static inline void set_ena_eth_io_rx_cdesc_base_src_vlan_cnt(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
814{
815 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_SRC_VLAN_CNT_MASK;
816}
817
818static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_proto_idx(const struct ena_eth_io_rx_cdesc_base *p)
819{
820 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
821}
822
823static inline void set_ena_eth_io_rx_cdesc_base_l4_proto_idx(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
824{
825 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK;
826}
827
828static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
829{
830 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
831}
832
833static inline void set_ena_eth_io_rx_cdesc_base_l3_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
834{
835 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK;
836}
837
838static inline uint32_t get_ena_eth_io_rx_cdesc_base_l4_csum_err(const struct ena_eth_io_rx_cdesc_base *p)
839{
840 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT;
841}
842
843static inline void set_ena_eth_io_rx_cdesc_base_l4_csum_err(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
844{
845 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L4_CSUM_ERR_MASK;
846}
847
848static inline uint32_t get_ena_eth_io_rx_cdesc_base_ipv4_frag(const struct ena_eth_io_rx_cdesc_base *p)
849{
850 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT;
851}
852
853static inline void set_ena_eth_io_rx_cdesc_base_ipv4_frag(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
854{
855 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_IPV4_FRAG_MASK;
856}
857
858static inline uint32_t get_ena_eth_io_rx_cdesc_base_phase(const struct ena_eth_io_rx_cdesc_base *p)
859{
860 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
861}
862
863static inline void set_ena_eth_io_rx_cdesc_base_phase(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
864{
865 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK;
866}
867
868static inline uint32_t get_ena_eth_io_rx_cdesc_base_l3_csum2(const struct ena_eth_io_rx_cdesc_base *p)
869{
870 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT;
871}
872
873static inline void set_ena_eth_io_rx_cdesc_base_l3_csum2(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
874{
875 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM2_MASK;
876}
877
878static inline uint32_t get_ena_eth_io_rx_cdesc_base_first(const struct ena_eth_io_rx_cdesc_base *p)
879{
880 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT;
881}
882
883static inline void set_ena_eth_io_rx_cdesc_base_first(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
884{
885 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_FIRST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_FIRST_MASK;
886}
887
888static inline uint32_t get_ena_eth_io_rx_cdesc_base_last(const struct ena_eth_io_rx_cdesc_base *p)
889{
890 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
891}
892
893static inline void set_ena_eth_io_rx_cdesc_base_last(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
894{
895 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK;
896}
897
898static inline uint32_t get_ena_eth_io_rx_cdesc_base_buffer(const struct ena_eth_io_rx_cdesc_base *p)
899{
900 return (p->status & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK) >> ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT;
901}
902
903static inline void set_ena_eth_io_rx_cdesc_base_buffer(struct ena_eth_io_rx_cdesc_base *p, uint32_t val)
904{
905 p->status |= (val << ENA_ETH_IO_RX_CDESC_BASE_BUFFER_SHIFT) & ENA_ETH_IO_RX_CDESC_BASE_BUFFER_MASK;
906}
907
908static inline uint32_t get_ena_eth_io_intr_reg_rx_intr_delay(const struct ena_eth_io_intr_reg *p)
909{
910 return p->intr_control & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
911}
912
913static inline void set_ena_eth_io_intr_reg_rx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
914{
915 p->intr_control |= val & ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
916}
917
918static inline uint32_t get_ena_eth_io_intr_reg_tx_intr_delay(const struct ena_eth_io_intr_reg *p)
919{
920 return (p->intr_control & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK) >> ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT;
921}
922
923static inline void set_ena_eth_io_intr_reg_tx_intr_delay(struct ena_eth_io_intr_reg *p, uint32_t val)
924{
925 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT) & ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
926}
927
928static inline uint32_t get_ena_eth_io_intr_reg_intr_unmask(const struct ena_eth_io_intr_reg *p)
929{
930 return (p->intr_control & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK) >> ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT;
931}
932
933static inline void set_ena_eth_io_intr_reg_intr_unmask(struct ena_eth_io_intr_reg *p, uint32_t val)
934{
935 p->intr_control |= (val << ENA_ETH_IO_INTR_REG_INTR_UNMASK_SHIFT) & ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
936}
937
938static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_numa(const struct ena_eth_io_numa_node_cfg_reg *p)
939{
940 return p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
941}
942
943static inline void set_ena_eth_io_numa_node_cfg_reg_numa(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
944{
945 p->numa_cfg |= val & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK;
946}
947
948static inline uint32_t get_ena_eth_io_numa_node_cfg_reg_enabled(const struct ena_eth_io_numa_node_cfg_reg *p)
949{
950 return (p->numa_cfg & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK) >> ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT;
951}
952
953static inline void set_ena_eth_io_numa_node_cfg_reg_enabled(struct ena_eth_io_numa_node_cfg_reg *p, uint32_t val)
954{
955 p->numa_cfg |= (val << ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_SHIFT) & ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
956}
957
958#endif /* !defined(ENA_DEFS_LINUX_MAINLINE) */
959#endif /*_ENA_ETH_IO_H_ */