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ena_com.h (343397) ena_com.h (361467)
1/*-
2 * BSD LICENSE
3 *
1/*-
2 * BSD LICENSE
3 *
4 * Copyright (c) 2015-2017 Amazon.com, Inc. or its affiliates.
4 * Copyright (c) 2015-2019 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.

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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef ENA_COM
35#define ENA_COM
36
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.

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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#ifndef ENA_COM
35#define ENA_COM
36
37#ifndef ENA_INTERNAL
38#include "ena_plat.h"
37#include "ena_plat.h"
39#else
40#include "ena_plat.h"
41#include "ena_includes.h"
42#endif
43
44#define ENA_MAX_NUM_IO_QUEUES 128U
45/* We need to queues for each IO (on for Tx and one for Rx) */
46#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
47
48#define ENA_MAX_HANDLERS 256
49
50#define ENA_MAX_PHYS_ADDR_SIZE_BITS 48

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84#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4
85#define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6
86#define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4
87#define ENA_INTR_MODER_LEVEL_STRIDE 1
88#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF
89
90#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
91
38
39#define ENA_MAX_NUM_IO_QUEUES 128U
40/* We need to queues for each IO (on for Tx and one for Rx) */
41#define ENA_TOTAL_NUM_QUEUES (2 * (ENA_MAX_NUM_IO_QUEUES))
42
43#define ENA_MAX_HANDLERS 256
44
45#define ENA_MAX_PHYS_ADDR_SIZE_BITS 48

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79#define ENA_INTR_INITIAL_RX_INTERVAL_USECS 4
80#define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6
81#define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4
82#define ENA_INTR_MODER_LEVEL_STRIDE 1
83#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF
84
85#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
86
87#define ENA_FEATURE_MAX_QUEUE_EXT_VER 1
88
92enum ena_intr_moder_level {
93 ENA_INTR_MODER_LOWEST = 0,
94 ENA_INTR_MODER_LOW,
95 ENA_INTR_MODER_MID,
96 ENA_INTR_MODER_HIGH,
97 ENA_INTR_MODER_HIGHEST,
98 ENA_INTR_MAX_NUM_OF_LEVELS,
99};
100
89enum ena_intr_moder_level {
90 ENA_INTR_MODER_LOWEST = 0,
91 ENA_INTR_MODER_LOW,
92 ENA_INTR_MODER_MID,
93 ENA_INTR_MODER_HIGH,
94 ENA_INTR_MODER_HIGHEST,
95 ENA_INTR_MAX_NUM_OF_LEVELS,
96};
97
98struct ena_llq_configurations {
99 enum ena_admin_llq_header_location llq_header_location;
100 enum ena_admin_llq_ring_entry_size llq_ring_entry_size;
101 enum ena_admin_llq_stride_ctrl llq_stride_ctrl;
102 enum ena_admin_llq_num_descs_before_header llq_num_decs_before_header;
103 u16 llq_ring_entry_size_value;
104};
105
101struct ena_intr_moder_entry {
102 unsigned int intr_moder_interval;
103 unsigned int pkts_per_interval;
104 unsigned int bytes_per_interval;
105};
106
107enum queue_direction {
108 ENA_COM_IO_QUEUE_DIRECTION_TX,

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129struct ena_com_tx_meta {
130 u16 mss;
131 u16 l3_hdr_len;
132 u16 l3_hdr_offset;
133 u16 l4_hdr_len; /* In words */
134};
135
136struct ena_com_llq_info {
106struct ena_intr_moder_entry {
107 unsigned int intr_moder_interval;
108 unsigned int pkts_per_interval;
109 unsigned int bytes_per_interval;
110};
111
112enum queue_direction {
113 ENA_COM_IO_QUEUE_DIRECTION_TX,

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134struct ena_com_tx_meta {
135 u16 mss;
136 u16 l3_hdr_len;
137 u16 l3_hdr_offset;
138 u16 l4_hdr_len; /* In words */
139};
140
141struct ena_com_llq_info {
137 bool inline_header;
142 u16 header_location_ctrl;
138 u16 desc_stride_ctrl;
143 u16 desc_stride_ctrl;
139
144 u16 desc_list_entry_size_ctrl;
140 u16 desc_list_entry_size;
141 u16 descs_num_before_header;
142 u16 descs_per_entry;
145 u16 desc_list_entry_size;
146 u16 descs_num_before_header;
147 u16 descs_per_entry;
148 u16 max_entries_in_tx_burst;
143};
144
145struct ena_com_io_cq {
146 struct ena_com_io_desc_addr cdesc_addr;
147 void *bus;
148
149 /* Interrupt unmask register */
150 u32 __iomem *unmask_reg;

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216 u16 idx;
217 u16 tail;
218 u16 next_to_comp;
219 u16 llq_last_copy_tail;
220 u32 tx_max_header_size;
221 u8 phase;
222 u8 desc_entry_size;
223 u8 dma_addr_bits;
149};
150
151struct ena_com_io_cq {
152 struct ena_com_io_desc_addr cdesc_addr;
153 void *bus;
154
155 /* Interrupt unmask register */
156 u32 __iomem *unmask_reg;

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222 u16 idx;
223 u16 tail;
224 u16 next_to_comp;
225 u16 llq_last_copy_tail;
226 u32 tx_max_header_size;
227 u8 phase;
228 u8 desc_entry_size;
229 u8 dma_addr_bits;
230 u16 entries_in_tx_burst_left;
224} ____cacheline_aligned;
225
226struct ena_com_admin_cq {
227 struct ena_admin_acq_entry *entries;
228 ena_mem_handle_t mem_handle;
229 dma_addr_t dma_addr;
230
231 u16 head;

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333 u32 debug_area_size;
334
335 /* Host information */
336 struct ena_admin_host_info *host_info;
337 dma_addr_t host_info_dma_addr;
338 ena_mem_handle_t host_info_dma_handle;
339};
340
231} ____cacheline_aligned;
232
233struct ena_com_admin_cq {
234 struct ena_admin_acq_entry *entries;
235 ena_mem_handle_t mem_handle;
236 dma_addr_t dma_addr;
237
238 u16 head;

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340 u32 debug_area_size;
341
342 /* Host information */
343 struct ena_admin_host_info *host_info;
344 dma_addr_t host_info_dma_addr;
345 ena_mem_handle_t host_info_dma_handle;
346};
347
348struct ena_extra_properties_strings {
349 u8 *virt_addr;
350 dma_addr_t dma_addr;
351 ena_mem_handle_t dma_handle;
352 u32 size;
353};
354
341/* Each ena_dev is a PCI function. */
342struct ena_com_dev {
343 struct ena_com_admin_queue admin_queue;
344 struct ena_com_aenq aenq;
345 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
346 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
347 u8 __iomem *reg_bar;
348 void __iomem *mem_bar;

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362
363 struct ena_host_attribute host_attr;
364 bool adaptive_coalescing;
365 u16 intr_delay_resolution;
366 u32 intr_moder_tx_interval;
367 struct ena_intr_moder_entry *intr_moder_tbl;
368
369 struct ena_com_llq_info llq_info;
355/* Each ena_dev is a PCI function. */
356struct ena_com_dev {
357 struct ena_com_admin_queue admin_queue;
358 struct ena_com_aenq aenq;
359 struct ena_com_io_cq io_cq_queues[ENA_TOTAL_NUM_QUEUES];
360 struct ena_com_io_sq io_sq_queues[ENA_TOTAL_NUM_QUEUES];
361 u8 __iomem *reg_bar;
362 void __iomem *mem_bar;

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376
377 struct ena_host_attribute host_attr;
378 bool adaptive_coalescing;
379 u16 intr_delay_resolution;
380 u32 intr_moder_tx_interval;
381 struct ena_intr_moder_entry *intr_moder_tbl;
382
383 struct ena_com_llq_info llq_info;
384 struct ena_extra_properties_strings extra_properties_strings;
370};
371
372struct ena_com_dev_get_features_ctx {
373 struct ena_admin_queue_feature_desc max_queues;
385};
386
387struct ena_com_dev_get_features_ctx {
388 struct ena_admin_queue_feature_desc max_queues;
389 struct ena_admin_queue_ext_feature_desc max_queue_ext;
374 struct ena_admin_device_attr_feature_desc dev_attr;
375 struct ena_admin_feature_aenq_desc aenq;
376 struct ena_admin_feature_offload_desc offload;
377 struct ena_admin_ena_hw_hints hw_hints;
378 struct ena_admin_feature_llq_desc llq;
390 struct ena_admin_device_attr_feature_desc dev_attr;
391 struct ena_admin_feature_aenq_desc aenq;
392 struct ena_admin_feature_offload_desc offload;
393 struct ena_admin_ena_hw_hints hw_hints;
394 struct ena_admin_feature_llq_desc llq;
395 struct ena_admin_feature_rss_ind_table ind_table;
379};
380
381struct ena_com_create_io_ctx {
382 enum ena_admin_placement_policy_type mem_queue_type;
383 enum queue_direction direction;
384 int numa_node;
385 u32 msix_vector;
386 u16 queue_size;

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429/* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
430 * @ena_dev: ENA communication layer struct
431 */
432void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
433
434/* ena_com_admin_init - Init the admin and the async queues
435 * @ena_dev: ENA communication layer struct
436 * @aenq_handlers: Those handlers to be called upon event.
396};
397
398struct ena_com_create_io_ctx {
399 enum ena_admin_placement_policy_type mem_queue_type;
400 enum queue_direction direction;
401 int numa_node;
402 u32 msix_vector;
403 u16 queue_size;

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446/* ena_com_mmio_reg_read_request_destroy - Destroy the mmio reg read mechanism
447 * @ena_dev: ENA communication layer struct
448 */
449void ena_com_mmio_reg_read_request_destroy(struct ena_com_dev *ena_dev);
450
451/* ena_com_admin_init - Init the admin and the async queues
452 * @ena_dev: ENA communication layer struct
453 * @aenq_handlers: Those handlers to be called upon event.
437 * @init_spinlock: Indicate if this method should init the admin spinlock or
438 * the spinlock was init before (for example, in a case of FLR).
439 *
440 * Initialize the admin submission and completion queues.
441 * Initialize the asynchronous events notification queues.
442 *
443 * @return - 0 on success, negative value on failure.
444 */
445int ena_com_admin_init(struct ena_com_dev *ena_dev,
454 *
455 * Initialize the admin submission and completion queues.
456 * Initialize the asynchronous events notification queues.
457 *
458 * @return - 0 on success, negative value on failure.
459 */
460int ena_com_admin_init(struct ena_com_dev *ena_dev,
446 struct ena_aenq_handlers *aenq_handlers,
447 bool init_spinlock);
461 struct ena_aenq_handlers *aenq_handlers);
448
449/* ena_com_admin_destroy - Destroy the admin and the async events queues.
450 * @ena_dev: ENA communication layer struct
451 *
452 * @note: Before calling this method, the caller must validate that the device
453 * won't send any additional admin completions/aenq.
454 * To achieve that, a FLR is recommended.
455 */

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589 * Retrieve the physical link parameters,
590 * like speed, auto-negotiation and full duplex support.
591 *
592 * @return - 0 on Success negative value otherwise.
593 */
594int ena_com_get_link_params(struct ena_com_dev *ena_dev,
595 struct ena_admin_get_feat_resp *resp);
596
462
463/* ena_com_admin_destroy - Destroy the admin and the async events queues.
464 * @ena_dev: ENA communication layer struct
465 *
466 * @note: Before calling this method, the caller must validate that the device
467 * won't send any additional admin completions/aenq.
468 * To achieve that, a FLR is recommended.
469 */

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603 * Retrieve the physical link parameters,
604 * like speed, auto-negotiation and full duplex support.
605 *
606 * @return - 0 on Success negative value otherwise.
607 */
608int ena_com_get_link_params(struct ena_com_dev *ena_dev,
609 struct ena_admin_get_feat_resp *resp);
610
611/* ena_com_extra_properties_strings_init - Initialize the extra properties strings buffer.
612 * @ena_dev: ENA communication layer struct
613 *
614 * Initialize the extra properties strings buffer.
615 */
616int ena_com_extra_properties_strings_init(struct ena_com_dev *ena_dev);
617
618/* ena_com_delete_extra_properties_strings - Free the extra properties strings buffer.
619 * @ena_dev: ENA communication layer struct
620 *
621 * Free the allocated extra properties strings buffer.
622 */
623void ena_com_delete_extra_properties_strings(struct ena_com_dev *ena_dev);
624
625/* ena_com_get_extra_properties_flags - Retrieve extra properties flags.
626 * @ena_dev: ENA communication layer struct
627 * @resp: Extra properties flags.
628 *
629 * Retrieve the extra properties flags.
630 *
631 * @return - 0 on Success negative value otherwise.
632 */
633int ena_com_get_extra_properties_flags(struct ena_com_dev *ena_dev,
634 struct ena_admin_get_feat_resp *resp);
635
597/* ena_com_get_dma_width - Retrieve physical dma address width the device
598 * supports.
599 * @ena_dev: ENA communication layer struct
600 *
601 * Retrieve the maximum physical address bits the device can handle.
602 *
603 * @return: > 0 on Success and negative value otherwise.
604 */

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967 * @entry: Entry to fill.
968 *
969 * Initialize the entry according to the adaptive interrupt moderation table.
970 */
971void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
972 enum ena_intr_moder_level level,
973 struct ena_intr_moder_entry *entry);
974
636/* ena_com_get_dma_width - Retrieve physical dma address width the device
637 * supports.
638 * @ena_dev: ENA communication layer struct
639 *
640 * Retrieve the maximum physical address bits the device can handle.
641 *
642 * @return: > 0 on Success and negative value otherwise.
643 */

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1006 * @entry: Entry to fill.
1007 *
1008 * Initialize the entry according to the adaptive interrupt moderation table.
1009 */
1010void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
1011 enum ena_intr_moder_level level,
1012 struct ena_intr_moder_entry *entry);
1013
975
976/* ena_com_config_dev_mode - Configure the placement policy of the device.
977 * @ena_dev: ENA communication layer struct
1014/* ena_com_config_dev_mode - Configure the placement policy of the device.
1015 * @ena_dev: ENA communication layer struct
978 * @llq: LLQ feature descriptor, retrieve via ena_com_get_dev_attr_feat.
979 *
1016 * @llq_features: LLQ feature descriptor, retrieve via
1017 * ena_com_get_dev_attr_feat.
1018 * @ena_llq_config: The default driver LLQ parameters configurations
980 */
981int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
1019 */
1020int ena_com_config_dev_mode(struct ena_com_dev *ena_dev,
982 struct ena_admin_feature_llq_desc *llq);
1021 struct ena_admin_feature_llq_desc *llq_features,
1022 struct ena_llq_configurations *llq_default_config);
983
984static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
985{
986 return ena_dev->adaptive_coalescing;
987}
988
989static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
990{

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1096 u8 *buf;
1097
1098 size = bounce_buf_ctrl->buffer_size;
1099 buffers_num = bounce_buf_ctrl->buffers_num;
1100
1101 buf = bounce_buf_ctrl->base_buffer +
1102 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
1103
1023
1024static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
1025{
1026 return ena_dev->adaptive_coalescing;
1027}
1028
1029static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
1030{

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1136 u8 *buf;
1137
1138 size = bounce_buf_ctrl->buffer_size;
1139 buffers_num = bounce_buf_ctrl->buffers_num;
1140
1141 buf = bounce_buf_ctrl->base_buffer +
1142 (bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
1143
1104 prefetch(bounce_buf_ctrl->base_buffer +
1144 prefetchw(bounce_buf_ctrl->base_buffer +
1105 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1106
1107 return buf;
1108}
1109
1110#ifdef ENA_EXTENDED_STATS
1111int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
1112 u32 len);
1113
1114int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
1115 u32 funct_queue);
1116#endif
1117#if defined(__cplusplus)
1118}
1119#endif /* __cplusplus */
1120#endif /* !(ENA_COM) */
1145 (bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
1146
1147 return buf;
1148}
1149
1150#ifdef ENA_EXTENDED_STATS
1151int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
1152 u32 len);
1153
1154int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
1155 u32 funct_queue);
1156#endif
1157#if defined(__cplusplus)
1158}
1159#endif /* __cplusplus */
1160#endif /* !(ENA_COM) */