| armreg.h (296256) | armreg.h (297536) |
|---|---|
| 1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2013, 2014 Andrew Turner 3 * Copyright (c) 2015 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This software was developed by Andrew Turner under 7 * sponsorship from the FreeBSD Foundation. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/arm64/include/armreg.h 296256 2016-03-01 08:15:00Z wma $ | 30 * $FreeBSD: head/sys/arm64/include/armreg.h 297536 2016-04-04 07:06:20Z wma $ |
| 31 */ 32 33#ifndef _MACHINE_ARMREG_H_ 34#define _MACHINE_ARMREG_H_ 35 36#define INSN_SIZE 4 37 38#define READ_SPECIALREG(reg) \ --- 22 unchanged lines hidden (view full) --- 61/* CTR_EL0 - Cache Type Register */ 62#define CTR_DLINE_SHIFT 16 63#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 64#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 65#define CTR_ILINE_SHIFT 0 66#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 67#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 68 | 31 */ 32 33#ifndef _MACHINE_ARMREG_H_ 34#define _MACHINE_ARMREG_H_ 35 36#define INSN_SIZE 4 37 38#define READ_SPECIALREG(reg) \ --- 22 unchanged lines hidden (view full) --- 61/* CTR_EL0 - Cache Type Register */ 62#define CTR_DLINE_SHIFT 16 63#define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 64#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 65#define CTR_ILINE_SHIFT 0 66#define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 67#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 68 |
| 69/* DCZID_EL0 - Data Cache Zero ID register */ 70#define DCZID_DZP (1 << 4) /* DC ZVA prohibited if non-0 */ 71#define DCZID_BS_SHIFT 0 72#define DCZID_BS_MASK (0xf << DCZID_BS_SHIFT) 73#define DCZID_BS_SIZE(reg) (((reg) & DCZID_BS_MASK) >> DCZID_BS_SHIFT) 74 |
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| 69/* ESR_ELx */ 70#define ESR_ELx_ISS_MASK 0x00ffffff 71#define ISS_INSN_FnV (0x01 << 10) 72#define ISS_INSN_EA (0x01 << 9) 73#define ISS_INSN_S1PTW (0x01 << 7) 74#define ISS_INSN_IFSC_MASK (0x1f << 0) 75#define ISS_DATA_ISV (0x01 << 24) 76#define ISS_DATA_SAS_MASK (0x03 << 22) --- 329 unchanged lines hidden --- | 75/* ESR_ELx */ 76#define ESR_ELx_ISS_MASK 0x00ffffff 77#define ISS_INSN_FnV (0x01 << 10) 78#define ISS_INSN_EA (0x01 << 9) 79#define ISS_INSN_S1PTW (0x01 << 7) 80#define ISS_INSN_IFSC_MASK (0x1f << 0) 81#define ISS_DATA_ISV (0x01 << 24) 82#define ISS_DATA_SAS_MASK (0x03 << 22) --- 329 unchanged lines hidden --- |