| machdep.c (317004) | machdep.c (319202) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include "opt_platform.h" 29#include "opt_ddb.h" 30 31#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2014 Andrew Turner 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include "opt_platform.h" 29#include "opt_ddb.h" 30 31#include <sys/cdefs.h> |
| 32__FBSDID("$FreeBSD: stable/11/sys/arm64/arm64/machdep.c 317004 2017-04-16 07:21:20Z mmel $"); | 32__FBSDID("$FreeBSD: stable/11/sys/arm64/arm64/machdep.c 319202 2017-05-30 12:26:36Z andrew $"); |
| 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/buf.h> 37#include <sys/bus.h> 38#include <sys/cons.h> 39#include <sys/cpu.h> 40#include <sys/devmap.h> --- 63 unchanged lines hidden (view full) --- 104u_int physmap_idx; 105 106struct kva_md_info kmi; 107 108int64_t dcache_line_size; /* The minimum D cache line size */ 109int64_t icache_line_size; /* The minimum I cache line size */ 110int64_t idcache_line_size; /* The minimum cache line size */ 111int64_t dczva_line_size; /* The size of cache line the dc zva zeroes */ | 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/buf.h> 37#include <sys/bus.h> 38#include <sys/cons.h> 39#include <sys/cpu.h> 40#include <sys/devmap.h> --- 63 unchanged lines hidden (view full) --- 104u_int physmap_idx; 105 106struct kva_md_info kmi; 107 108int64_t dcache_line_size; /* The minimum D cache line size */ 109int64_t icache_line_size; /* The minimum I cache line size */ 110int64_t idcache_line_size; /* The minimum cache line size */ 111int64_t dczva_line_size; /* The size of cache line the dc zva zeroes */ |
| 112int has_pan; |
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| 112 113/* pagezero_* implementations are provided in support.S */ 114void pagezero_simple(void *); 115void pagezero_cache(void *); 116 117/* pagezero_simple is default pagezero */ 118void (*pagezero)(void *p) = pagezero_simple; 119 120static void | 113 114/* pagezero_* implementations are provided in support.S */ 115void pagezero_simple(void *); 116void pagezero_cache(void *); 117 118/* pagezero_simple is default pagezero */ 119void (*pagezero)(void *p) = pagezero_simple; 120 121static void |
| 122pan_setup(void) 123{ 124 uint64_t id_aa64mfr1; 125 126 id_aa64mfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); 127 if (ID_AA64MMFR1_PAN(id_aa64mfr1) != ID_AA64MMFR1_PAN_NONE) 128 has_pan = 1; 129} 130 131void 132pan_enable(void) 133{ 134 135 /* 136 * The LLVM integrated assembler doesn't understand the PAN 137 * PSTATE field. Because of this we need to manually create 138 * the instruction in an asm block. This is equivalent to: 139 * msr pan, #1 140 * 141 * This sets the PAN bit, stopping the kernel from accessing 142 * memory when userspace can also access it unless the kernel 143 * uses the userspace load/store instructions. 144 */ 145 if (has_pan) { 146 WRITE_SPECIALREG(sctlr_el1, 147 READ_SPECIALREG(sctlr_el1) & ~SCTLR_SPAN); 148 __asm __volatile(".inst 0xd500409f | (0x1 << 8)"); 149 } 150} 151 152static void |
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| 121cpu_startup(void *dummy) 122{ 123 124 identify_cpu(); 125 126 vm_ksubmap_init(&kmi); 127 bufinit(); 128 vm_pager_bufferinit(); --- 786 unchanged lines hidden (view full) --- 915 "msr tpidr_el1, %0" :: "r"(pcpup)); 916 917 PCPU_SET(curthread, &thread0); 918 919 /* Do basic tuning, hz etc */ 920 init_param1(); 921 922 cache_setup(); | 153cpu_startup(void *dummy) 154{ 155 156 identify_cpu(); 157 158 vm_ksubmap_init(&kmi); 159 bufinit(); 160 vm_pager_bufferinit(); --- 786 unchanged lines hidden (view full) --- 947 "msr tpidr_el1, %0" :: "r"(pcpup)); 948 949 PCPU_SET(curthread, &thread0); 950 951 /* Do basic tuning, hz etc */ 952 init_param1(); 953 954 cache_setup(); |
| 955 pan_setup(); |
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| 923 924 /* Bootstrap enough of pmap to enter the kernel proper */ 925 pmap_bootstrap(abp->kern_l0pt, abp->kern_l1pt, 926 KERNBASE - abp->kern_delta, lastaddr - KERNBASE); 927 928 devmap_bootstrap(0, NULL); 929 930 cninit(); 931 932 init_proc0(abp->kern_stack); 933 msgbufinit(msgbufp, msgbufsize); 934 mutex_init(); 935 init_param2(physmem); 936 937 dbg_monitor_init(); 938 kdb_init(); | 956 957 /* Bootstrap enough of pmap to enter the kernel proper */ 958 pmap_bootstrap(abp->kern_l0pt, abp->kern_l1pt, 959 KERNBASE - abp->kern_delta, lastaddr - KERNBASE); 960 961 devmap_bootstrap(0, NULL); 962 963 cninit(); 964 965 init_proc0(abp->kern_stack); 966 msgbufinit(msgbufp, msgbufsize); 967 mutex_init(); 968 init_param2(physmem); 969 970 dbg_monitor_init(); 971 kdb_init(); |
| 972 pan_enable(); |
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| 939 940 early_boot = 0; 941} 942 943#ifdef DDB 944#include <ddb/ddb.h> 945 946DB_SHOW_COMMAND(specialregs, db_show_spregs) --- 87 unchanged lines hidden --- | 973 974 early_boot = 0; 975} 976 977#ifdef DDB 978#include <ddb/ddb.h> 979 980DB_SHOW_COMMAND(specialregs, db_show_spregs) --- 87 unchanged lines hidden --- |