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ixp425_qmgr.c (215034) ixp425_qmgr.c (236987)
1/*-
2 * Copyright (c) 2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30/*-
31 * Copyright (c) 2001-2005, Intel Corporation.
32 * All rights reserved.
1/*-
2 * Copyright (c) 2006 Sam Leffler, Errno Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
28 */
29
30/*-
31 * Copyright (c) 2001-2005, Intel Corporation.
32 * All rights reserved.
33 *
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. Neither the name of the Intel Corporation nor the names of its contributors
43 * may be used to endorse or promote products derived from this software
44 * without specific prior written permission.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. Neither the name of the Intel Corporation nor the names of its contributors
43 * may be used to endorse or promote products derived from this software
44 * without specific prior written permission.
45 *
46 *
45 *
46 *
47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
48 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * SUCH DAMAGE.
58*/
59#include <sys/cdefs.h>
47 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
48 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
51 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57 * SUCH DAMAGE.
58*/
59#include <sys/cdefs.h>
60__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_qmgr.c 215034 2010-11-09 10:59:09Z brucec $");
60__FBSDID("$FreeBSD: head/sys/arm/xscale/ixp425/ixp425_qmgr.c 236987 2012-06-13 04:38:09Z imp $");
61
62/*
63 * Intel XScale Queue Manager support.
64 *
65 * Each IXP4XXX device has a hardware block that implements a priority
66 * queue manager that is shared between the XScale cpu and the backend
67 * devices (such as the NPE). Queues are accessed by reading/writing
68 * special memory locations. The queue contents are mapped into a shared

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119
120 uint32_t intRegCheckMask; /* interrupt reg check mask */
121 void (*cb)(int, void *); /* callback function */
122 void *cbarg; /* callback argument */
123 int priority; /* dispatch priority */
124#if 0
125 /* NB: needed only for A0 parts */
126 u_int statusWordOffset; /* status word offset */
61
62/*
63 * Intel XScale Queue Manager support.
64 *
65 * Each IXP4XXX device has a hardware block that implements a priority
66 * queue manager that is shared between the XScale cpu and the backend
67 * devices (such as the NPE). Queues are accessed by reading/writing
68 * special memory locations. The queue contents are mapped into a shared

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119
120 uint32_t intRegCheckMask; /* interrupt reg check mask */
121 void (*cb)(int, void *); /* callback function */
122 void *cbarg; /* callback argument */
123 int priority; /* dispatch priority */
124#if 0
125 /* NB: needed only for A0 parts */
126 u_int statusWordOffset; /* status word offset */
127 uint32_t statusMask; /* status mask */
127 uint32_t statusMask; /* status mask */
128 uint32_t statusCheckValue; /* status check value */
129#endif
130};
131
132struct ixpqmgr_softc {
133 device_t sc_dev;
134 bus_space_tag_t sc_iot;
135 bus_space_handle_t sc_ioh;

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252 }
253
254 /* NB: softc is pre-zero'd */
255 for (i = 0; i < IX_QMGR_MAX_NUM_QUEUES; i++) {
256 struct qmgrInfo *qi = &sc->qinfo[i];
257
258 qi->cb = dummyCallback;
259 qi->priority = IX_QMGR_Q_PRIORITY_0; /* default priority */
128 uint32_t statusCheckValue; /* status check value */
129#endif
130};
131
132struct ixpqmgr_softc {
133 device_t sc_dev;
134 bus_space_tag_t sc_iot;
135 bus_space_handle_t sc_ioh;

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252 }
253
254 /* NB: softc is pre-zero'd */
255 for (i = 0; i < IX_QMGR_MAX_NUM_QUEUES; i++) {
256 struct qmgrInfo *qi = &sc->qinfo[i];
257
258 qi->cb = dummyCallback;
259 qi->priority = IX_QMGR_Q_PRIORITY_0; /* default priority */
260 /*
260 /*
261 * There are two interrupt registers, 32 bits each. One
262 * for the lower queues(0-31) and one for the upper
263 * queues(32-63). Therefore need to mod by 32 i.e the
264 * min upper queue identifier.
265 */
266 qi->intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
267
268 /*

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275 qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
276 qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
277 qi->qConfigRegAddr = IX_QMGR_Q_CONFIG_ADDR_GET(i);
278
279 /* AQM Queue lower-group (0-31), only */
280 if (i < IX_QMGR_MIN_QUEUPP_QID) {
281 /* AQM Q underflow/overflow status reg address, per queue */
282 qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET +
261 * There are two interrupt registers, 32 bits each. One
262 * for the lower queues(0-31) and one for the upper
263 * queues(32-63). Therefore need to mod by 32 i.e the
264 * min upper queue identifier.
265 */
266 qi->intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
267
268 /*

--- 6 unchanged lines hidden (view full) ---

275 qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
276 qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
277 qi->qConfigRegAddr = IX_QMGR_Q_CONFIG_ADDR_GET(i);
278
279 /* AQM Queue lower-group (0-31), only */
280 if (i < IX_QMGR_MIN_QUEUPP_QID) {
281 /* AQM Q underflow/overflow status reg address, per queue */
282 qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET +
283 ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
283 ((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
284 sizeof(uint32_t));
285
286 /* AQM Q underflow status bit masks for status reg per queue */
284 sizeof(uint32_t));
285
286 /* AQM Q underflow status bit masks for status reg per queue */
287 qi->qUflowStatBitMask =
287 qi->qUflowStatBitMask =
288 (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
289 ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
290 (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
291
292 /* AQM Q overflow status bit masks for status reg, per queue */
288 (IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
289 ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
290 (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
291
292 /* AQM Q overflow status bit masks for status reg, per queue */
293 qi->qOflowStatBitMask =
293 qi->qOflowStatBitMask =
294 (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
295 ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
296 (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
297
298 /* AQM Q lower-group (0-31) status reg addresses, per queue */
299 qi->qStatRegAddr = IX_QMGR_QUELOWSTAT0_OFFSET +
300 ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
301 sizeof(uint32_t));
302
303 /* AQM Q lower-group (0-31) status register bit offset */
304 qi->qStatBitsOffset =
294 (IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
295 ((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
296 (32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
297
298 /* AQM Q lower-group (0-31) status reg addresses, per queue */
299 qi->qStatRegAddr = IX_QMGR_QUELOWSTAT0_OFFSET +
300 ((i / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
301 sizeof(uint32_t));
302
303 /* AQM Q lower-group (0-31) status register bit offset */
304 qi->qStatBitsOffset =
305 (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
305 (i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
306 (32 / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
307 } else { /* AQM Q upper-group (32-63), only */
308 qi->qUOStatRegAddr = 0; /* XXX */
309
310 /* AQM Q upper-group (32-63) Nearly Empty status reg bitmasks */
311 qi->qStat0BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
312
313 /* AQM Q upper-group (32-63) Full status register bitmasks */

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400 * Increment the current number of entries in the queue
401 * and check for overflow .
402 */
403 if (qi->qWriteCount++ == qSize) { /* check for overflow */
404 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
405 int qPtrs;
406
407 /*
306 (32 / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
307 } else { /* AQM Q upper-group (32-63), only */
308 qi->qUOStatRegAddr = 0; /* XXX */
309
310 /* AQM Q upper-group (32-63) Nearly Empty status reg bitmasks */
311 qi->qStat0BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
312
313 /* AQM Q upper-group (32-63) Full status register bitmasks */

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400 * Increment the current number of entries in the queue
401 * and check for overflow .
402 */
403 if (qi->qWriteCount++ == qSize) { /* check for overflow */
404 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
405 int qPtrs;
406
407 /*
408 * Read the status twice because the status may
408 * Read the status twice because the status may
409 * not be immediately ready after the write operation
410 */
411 if ((status & qi->qOflowStatBitMask) ||
412 ((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) {
413 /*
414 * The queue is full, clear the overflow status bit if set.
415 */
416 aqm_reg_write(sc, qi->qUOStatRegAddr,

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427 * updated from the current number of entries in the queue
428 */
429
430 /* calculate number of words in q */
431 qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr);
432 DPRINTFn(2, sc->sc_dev,
433 "%s(%u, 0x%x) Q full, no overflow status, qConfig 0x%x\n",
434 __func__, qId, entry, qPtrs);
409 * not be immediately ready after the write operation
410 */
411 if ((status & qi->qOflowStatBitMask) ||
412 ((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) {
413 /*
414 * The queue is full, clear the overflow status bit if set.
415 */
416 aqm_reg_write(sc, qi->qUOStatRegAddr,

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427 * updated from the current number of entries in the queue
428 */
429
430 /* calculate number of words in q */
431 qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr);
432 DPRINTFn(2, sc->sc_dev,
433 "%s(%u, 0x%x) Q full, no overflow status, qConfig 0x%x\n",
434 __func__, qId, entry, qPtrs);
435 qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
435 qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
436
437 if (qPtrs == 0) {
438 /*
436
437 if (qPtrs == 0) {
438 /*
439 * The queue may be full at the time of the
440 * snapshot. Next access will check
439 * The queue may be full at the time of the
440 * snapshot. Next access will check
441 * the overflow status again.
442 */
443 qi->qWriteCount = qSize;
444 } else {
445 /* convert the number of words to a number of entries */
446 qi->qWriteCount = qPtrs & (qSize - 1);
447 }
448 }

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455{
456 struct ixpqmgr_softc *sc = ixpqmgr_sc;
457 struct qmgrInfo *qi = &sc->qinfo[qId];
458 bus_size_t off = qi->qAccRegAddr;
459
460 *entry = aqm_reg_read(sc, off);
461
462 /*
441 * the overflow status again.
442 */
443 qi->qWriteCount = qSize;
444 } else {
445 /* convert the number of words to a number of entries */
446 qi->qWriteCount = qPtrs & (qSize - 1);
447 }
448 }

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455{
456 struct ixpqmgr_softc *sc = ixpqmgr_sc;
457 struct qmgrInfo *qi = &sc->qinfo[qId];
458 bus_size_t off = qi->qAccRegAddr;
459
460 *entry = aqm_reg_read(sc, off);
461
462 /*
463 * Reset the current read count : next access to the read function
463 * Reset the current read count : next access to the read function
464 * will force a underflow status check.
465 */
466 qi->qReadCount = 0;
467
468 /* Check if underflow occurred on the read */
469 if (*entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) {
470 /* get the queue status */
471 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);

--- 22 unchanged lines hidden (view full) ---

494 break;
495 }
496 *p++ = entry; /* store */
497 entry = aqm_reg_read(sc, off);
498 }
499 *p = entry;
500
501 /*
464 * will force a underflow status check.
465 */
466 qi->qReadCount = 0;
467
468 /* Check if underflow occurred on the read */
469 if (*entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) {
470 /* get the queue status */
471 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);

--- 22 unchanged lines hidden (view full) ---

494 break;
495 }
496 *p++ = entry; /* store */
497 entry = aqm_reg_read(sc, off);
498 }
499 *p = entry;
500
501 /*
502 * Reset the current read count : next access to the read function
502 * Reset the current read count : next access to the read function
503 * will force a underflow status check.
504 */
505 qi->qReadCount = 0;
506
507 /* Check if underflow occurred on the read */
508 if (entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) {
509 /* get the queue status */
510 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);

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662 sc->uppPriorityTableFirstHalfMask = 0;
663
664 lowQuePriorityTableIndex = 0;
665 uppQuePriorityTableIndex = 32;
666 for (pri = 0; pri < IX_QMGR_NUM_PRIORITY_LEVELS; pri++) {
667 /* low priority q's */
668 for (q = 0; q < IX_QMGR_MIN_QUEUPP_QID; q++) {
669 qi = &sc->qinfo[q];
503 * will force a underflow status check.
504 */
505 qi->qReadCount = 0;
506
507 /* Check if underflow occurred on the read */
508 if (entry == 0 && qId < IX_QMGR_MIN_QUEUPP_QID) {
509 /* get the queue status */
510 uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);

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662 sc->uppPriorityTableFirstHalfMask = 0;
663
664 lowQuePriorityTableIndex = 0;
665 uppQuePriorityTableIndex = 32;
666 for (pri = 0; pri < IX_QMGR_NUM_PRIORITY_LEVELS; pri++) {
667 /* low priority q's */
668 for (q = 0; q < IX_QMGR_MIN_QUEUPP_QID; q++) {
669 qi = &sc->qinfo[q];
670 if (qi->priority == pri) {
670 if (qi->priority == pri) {
671 /*
672 * Build the priority table bitmask which match the
673 * queues of the first half of the priority table.
674 */
675 if (lowQuePriorityTableIndex < 16) {
676 sc->lowPriorityTableFirstHalfMask |=
677 qi->intRegCheckMask;
678 }

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707 * word (in) return value (out)
708 * 0x80000000 0
709 * 0x40000000 1
710 * ,,, ,,,
711 * 0x00000002 30
712 * 0x00000001 31
713 * 0x00000000 32
714 *
671 /*
672 * Build the priority table bitmask which match the
673 * queues of the first half of the priority table.
674 */
675 if (lowQuePriorityTableIndex < 16) {
676 sc->lowPriorityTableFirstHalfMask |=
677 qi->intRegCheckMask;
678 }

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707 * word (in) return value (out)
708 * 0x80000000 0
709 * 0x40000000 1
710 * ,,, ,,,
711 * 0x00000002 30
712 * 0x00000001 31
713 * 0x00000000 32
714 *
715 * The C version of this function is used as a replacement
716 * for system not providing the equivalent of the CLZ
715 * The C version of this function is used as a replacement
716 * for system not providing the equivalent of the CLZ
717 * assembly language instruction.
718 *
719 * Note that this version is big-endian
720 */
721static unsigned int
722_lzcount(uint32_t word)
723{
724 unsigned int lzcount = 0;

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814 * against (statusCheckValue) and the mask (statusMask) to mask
815 * out all but the bits to check in the status word.
816 */
817static void
818aqm_calc_statuscheck(int qId, IxQMgrSourceId srcSel)
819{
820 struct qmgrInfo *qi = &qinfo[qId];
821 uint32_t shiftVal;
717 * assembly language instruction.
718 *
719 * Note that this version is big-endian
720 */
721static unsigned int
722_lzcount(uint32_t word)
723{
724 unsigned int lzcount = 0;

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814 * against (statusCheckValue) and the mask (statusMask) to mask
815 * out all but the bits to check in the status word.
816 */
817static void
818aqm_calc_statuscheck(int qId, IxQMgrSourceId srcSel)
819{
820 struct qmgrInfo *qi = &qinfo[qId];
821 uint32_t shiftVal;
822
822
823 if (qId < IX_QMGR_MIN_QUEUPP_QID) {
824 switch (srcSel) {
825 case IX_QMGR_Q_SOURCE_ID_E:
826 qi->statusCheckValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
827 qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
828 break;
829 case IX_QMGR_Q_SOURCE_ID_NE:
830 qi->statusCheckValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;

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858 /* Should never hit */
859 IX_OSAL_ASSERT(0);
860 break;
861 }
862
863 /* One nibble of status per queue so need to shift the
864 * check value and mask out to the correct position.
865 */
823 if (qId < IX_QMGR_MIN_QUEUPP_QID) {
824 switch (srcSel) {
825 case IX_QMGR_Q_SOURCE_ID_E:
826 qi->statusCheckValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
827 qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
828 break;
829 case IX_QMGR_Q_SOURCE_ID_NE:
830 qi->statusCheckValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;

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858 /* Should never hit */
859 IX_OSAL_ASSERT(0);
860 break;
861 }
862
863 /* One nibble of status per queue so need to shift the
864 * check value and mask out to the correct position.
865 */
866 shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
866 shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
867 IX_QMGR_QUELOWSTAT_BITS_PER_Q;
868
869 /* Calculate the which status word to check from the qId,
870 * 8 Qs status per word
871 */
872 qi->statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
873
874 qi->statusCheckValue <<= shiftVal;

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965 /* Build config register */
966 qCfg = ((toAqmEntrySize(1) & IX_QMGR_ENTRY_SIZE_MASK) <<
967 IX_QMGR_Q_CONFIG_ESIZE_OFFSET)
968 | ((toAqmBufferSize(qi->qSizeInWords) & IX_QMGR_SIZE_MASK) <<
969 IX_QMGR_Q_CONFIG_BSIZE_OFFSET);
970
971 /* baseAddress, calculated relative to start address */
972 baseAddress = sc->aqmFreeSramAddress;
867 IX_QMGR_QUELOWSTAT_BITS_PER_Q;
868
869 /* Calculate the which status word to check from the qId,
870 * 8 Qs status per word
871 */
872 qi->statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
873
874 qi->statusCheckValue <<= shiftVal;

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965 /* Build config register */
966 qCfg = ((toAqmEntrySize(1) & IX_QMGR_ENTRY_SIZE_MASK) <<
967 IX_QMGR_Q_CONFIG_ESIZE_OFFSET)
968 | ((toAqmBufferSize(qi->qSizeInWords) & IX_QMGR_SIZE_MASK) <<
969 IX_QMGR_Q_CONFIG_BSIZE_OFFSET);
970
971 /* baseAddress, calculated relative to start address */
972 baseAddress = sc->aqmFreeSramAddress;
973
973
974 /* base address must be word-aligned */
975 KASSERT((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) == 0,
976 ("address not word-aligned"));
977
978 /* Now convert to a 16 word pointer as required by QUECONFIG register */
979 baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
980 qCfg |= baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET;
981

--- 20 unchanged lines hidden (view full) ---

1002 */
1003 off = IX_QMGR_INT0SRCSELREG0_OFFSET +
1004 ((qId / IX_QMGR_INTSRC_NUM_QUE_PER_WORD) * sizeof(uint32_t));
1005
1006 v = aqm_reg_read(sc, off);
1007 if (off == IX_QMGR_INT0SRCSELREG0_OFFSET && qId == 0) {
1008 /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */
1009 v |= 0x7;
974 /* base address must be word-aligned */
975 KASSERT((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) == 0,
976 ("address not word-aligned"));
977
978 /* Now convert to a 16 word pointer as required by QUECONFIG register */
979 baseAddress >>= IX_QMGR_BASE_ADDR_16_WORD_SHIFT;
980 qCfg |= baseAddress << IX_QMGR_Q_CONFIG_BADDR_OFFSET;
981

--- 20 unchanged lines hidden (view full) ---

1002 */
1003 off = IX_QMGR_INT0SRCSELREG0_OFFSET +
1004 ((qId / IX_QMGR_INTSRC_NUM_QUE_PER_WORD) * sizeof(uint32_t));
1005
1006 v = aqm_reg_read(sc, off);
1007 if (off == IX_QMGR_INT0SRCSELREG0_OFFSET && qId == 0) {
1008 /* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */
1009 v |= 0x7;
1010 } else {
1010 } else {
1011 const uint32_t bpq = 32 / IX_QMGR_INTSRC_NUM_QUE_PER_WORD;
1012 uint32_t mask;
1013 int qshift;
1014
1015 qshift = (qId & (IX_QMGR_INTSRC_NUM_QUE_PER_WORD-1)) * bpq;
1016 mask = ((1 << bpq) - 1) << qshift; /* q's status mask */
1017
1018 /* merge sourceId */

--- 41 unchanged lines hidden (view full) ---

1060 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG0_OFFSET,
1061 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1062 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG1_OFFSET,
1063 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1064 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG2_OFFSET,
1065 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1066 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG3_OFFSET,
1067 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1011 const uint32_t bpq = 32 / IX_QMGR_INTSRC_NUM_QUE_PER_WORD;
1012 uint32_t mask;
1013 int qshift;
1014
1015 qshift = (qId & (IX_QMGR_INTSRC_NUM_QUE_PER_WORD-1)) * bpq;
1016 mask = ((1 << bpq) - 1) << qshift; /* q's status mask */
1017
1018 /* merge sourceId */

--- 41 unchanged lines hidden (view full) ---

1060 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG0_OFFSET,
1061 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1062 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG1_OFFSET,
1063 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1064 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG2_OFFSET,
1065 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1066 aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG3_OFFSET,
1067 IX_QMGR_INT0SRCSELREG_RESET_VALUE);
1068
1068
1069 /* Reset queue interrupt enable register 0..1 */
1070 aqm_reg_write(sc, IX_QMGR_QUEIEREG0_OFFSET,
1071 IX_QMGR_QUEIEREG_RESET_VALUE);
1072 aqm_reg_write(sc, IX_QMGR_QUEIEREG1_OFFSET,
1073 IX_QMGR_QUEIEREG_RESET_VALUE);
1074
1075 /* Reset queue interrupt register 0..1 */
1076 aqm_reg_write(sc, IX_QMGR_QINTREG0_OFFSET, IX_QMGR_QINTREG_RESET_VALUE);

--- 29 unchanged lines hidden --- 		1069 /* Reset queue interrupt enable register 0..1 */
1070 aqm_reg_write(sc, IX_QMGR_QUEIEREG0_OFFSET,
1071 IX_QMGR_QUEIEREG_RESET_VALUE);
1072 aqm_reg_write(sc, IX_QMGR_QUEIEREG1_OFFSET,
1073 IX_QMGR_QUEIEREG_RESET_VALUE);
1074
1075 /* Reset queue interrupt register 0..1 */
1076 aqm_reg_write(sc, IX_QMGR_QINTREG0_OFFSET, IX_QMGR_QINTREG_RESET_VALUE);

--- 29 unchanged lines hidden ---