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ti_gpio.c (278216) ti_gpio.c (283276)
1/*-
2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 */
27
28/**
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
30 * here uses 0-5.
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
3 * Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 17 unchanged lines hidden (view full) ---

26 */
27
28/**
29 * Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
30 * here uses 0-5.
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/arm/ti/ti_gpio.c 278216 2015-02-04 18:35:49Z loos $");
34__FBSDID("$FreeBSD: head/sys/arm/ti/ti_gpio.c 283276 2015-05-22 03:16:18Z gonzo $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>

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47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <arm/ti/ti_cpuid.h>
52#include <arm/ti/ti_gpio.h>
53#include <arm/ti/ti_scm.h>
54#include <arm/ti/ti_prcm.h>
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/rman.h>

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47
48#include <machine/bus.h>
49#include <machine/resource.h>
50
51#include <arm/ti/ti_cpuid.h>
52#include <arm/ti/ti_gpio.h>
53#include <arm/ti/ti_scm.h>
54#include <arm/ti/ti_prcm.h>
55#include <arm/ti/ti_hwmods.h>
55
56#include <dev/fdt/fdt_common.h>
57#include <dev/gpio/gpiobusvar.h>
58#include <dev/ofw/openfirm.h>
59#include <dev/ofw/ofw_bus.h>
60#include <dev/ofw/ofw_bus_subr.h>
61
62#include "gpio_if.h"

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96#define TI_GPIO_DEBOUNCENABLE 0x0150
97#define TI_GPIO_DEBOUNCINGTIME 0x0154
98#define TI_GPIO_CLEARWKUPENA 0x0180
99#define TI_GPIO_SETWKUENA 0x0184
100#define TI_GPIO_CLEARDATAOUT 0x0190
101#define TI_GPIO_SETDATAOUT 0x0194
102
103/* Other SoC Specific definitions */
56
57#include <dev/fdt/fdt_common.h>
58#include <dev/gpio/gpiobusvar.h>
59#include <dev/ofw/openfirm.h>
60#include <dev/ofw/ofw_bus.h>
61#include <dev/ofw/ofw_bus_subr.h>
62
63#include "gpio_if.h"

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97#define TI_GPIO_DEBOUNCENABLE 0x0150
98#define TI_GPIO_DEBOUNCINGTIME 0x0154
99#define TI_GPIO_CLEARWKUPENA 0x0180
100#define TI_GPIO_SETWKUENA 0x0184
101#define TI_GPIO_CLEARDATAOUT 0x0190
102#define TI_GPIO_SETDATAOUT 0x0194
103
104/* Other SoC Specific definitions */
104#define OMAP4_MAX_GPIO_BANKS 6
105#define OMAP4_FIRST_GPIO_BANK 1
106#define OMAP4_INTR_PER_BANK 1
107#define OMAP4_GPIO_REV 0x50600801
105#define OMAP4_FIRST_GPIO_BANK 1
106#define OMAP4_INTR_PER_BANK 1
107#define OMAP4_GPIO_REV 0x50600801
108#define AM335X_MAX_GPIO_BANKS 4
109#define AM335X_FIRST_GPIO_BANK 0
110#define AM335X_INTR_PER_BANK 2
111#define AM335X_GPIO_REV 0x50600801
112#define PINS_PER_BANK 32
108#define AM335X_FIRST_GPIO_BANK 0
109#define AM335X_INTR_PER_BANK 2
110#define AM335X_GPIO_REV 0x50600801
111#define PINS_PER_BANK 32
113#define TI_GPIO_BANK(p) ((p) / PINS_PER_BANK)
114#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
115
112#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
113
116static struct ti_gpio_softc *ti_gpio_sc = NULL;
117static int ti_gpio_detach(device_t);
118
119static u_int
114static int ti_gpio_detach(device_t);
115
116static u_int
120ti_max_gpio_banks(void)
121{
122 switch(ti_chip()) {
123#ifdef SOC_OMAP4
124 case CHIP_OMAP_4:
125 return (OMAP4_MAX_GPIO_BANKS);
126#endif
127#ifdef SOC_TI_AM335X
128 case CHIP_AM335X:
129 return (AM335X_MAX_GPIO_BANKS);
130#endif
131 }
132 return (0);
133}
134
135static u_int
136ti_max_gpio_intrs(void)
137{
138 switch(ti_chip()) {
139#ifdef SOC_OMAP4
140 case CHIP_OMAP_4:
141 return (OMAP4_MAX_GPIO_BANKS * OMAP4_INTR_PER_BANK);
142#endif
143#ifdef SOC_TI_AM335X
144 case CHIP_AM335X:
145 return (AM335X_MAX_GPIO_BANKS * AM335X_INTR_PER_BANK);
146#endif
147 }
148 return (0);
149}
150
151static u_int
152ti_first_gpio_bank(void)
153{
154 switch(ti_chip()) {
155#ifdef SOC_OMAP4
156 case CHIP_OMAP_4:
157 return (OMAP4_FIRST_GPIO_BANK);
158#endif
159#ifdef SOC_TI_AM335X

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176 case CHIP_AM335X:
177 return (AM335X_GPIO_REV);
178#endif
179 }
180 return (0);
181}
182
183/**
117ti_first_gpio_bank(void)
118{
119 switch(ti_chip()) {
120#ifdef SOC_OMAP4
121 case CHIP_OMAP_4:
122 return (OMAP4_FIRST_GPIO_BANK);
123#endif
124#ifdef SOC_TI_AM335X

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141 case CHIP_AM335X:
142 return (AM335X_GPIO_REV);
143#endif
144 }
145 return (0);
146}
147
148/**
184 * ti_gpio_mem_spec - Resource specification used when allocating resources
185 * ti_gpio_irq_spec - Resource specification used when allocating resources
186 *
187 * This driver module can have up to six independent memory regions, each
188 * region typically controls 32 GPIO pins.
189 *
190 * On OMAP3 and OMAP4 there is only one physical interrupt line per bank,
191 * but there are two set of registers which control the interrupt delivery
192 * to internal subsystems. The first set of registers control the
193 * interrupts delivery to the MPU and the second set control the
194 * interrupts delivery to the DSP.
195 *
196 * On AM335x there are two physical interrupt lines for each GPIO module.
197 * Each interrupt line is controlled by a set of registers.
198 */
199static struct resource_spec ti_gpio_mem_spec[] = {
200 { SYS_RES_MEMORY, 0, RF_ACTIVE },
201 { SYS_RES_MEMORY, 1, RF_ACTIVE | RF_OPTIONAL },
202 { SYS_RES_MEMORY, 2, RF_ACTIVE | RF_OPTIONAL },
203 { SYS_RES_MEMORY, 3, RF_ACTIVE | RF_OPTIONAL },
204#if !defined(SOC_TI_AM335X)
205 { SYS_RES_MEMORY, 4, RF_ACTIVE | RF_OPTIONAL },
206 { SYS_RES_MEMORY, 5, RF_ACTIVE | RF_OPTIONAL },
207#endif
208 { -1, 0, 0 }
209};
210static struct resource_spec ti_gpio_irq_spec[] = {
211 { SYS_RES_IRQ, 0, RF_ACTIVE },
212 { SYS_RES_IRQ, 1, RF_ACTIVE | RF_OPTIONAL },
213 { SYS_RES_IRQ, 2, RF_ACTIVE | RF_OPTIONAL },
214 { SYS_RES_IRQ, 3, RF_ACTIVE | RF_OPTIONAL },
215 { SYS_RES_IRQ, 4, RF_ACTIVE | RF_OPTIONAL },
216 { SYS_RES_IRQ, 5, RF_ACTIVE | RF_OPTIONAL },
217#if defined(SOC_TI_AM335X)
218 { SYS_RES_IRQ, 6, RF_ACTIVE | RF_OPTIONAL },
219 { SYS_RES_IRQ, 7, RF_ACTIVE | RF_OPTIONAL },
220#endif
221 { -1, 0, 0 }
222};
223
224/**
225 * Macros for driver mutex locking
226 */
227#define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
228#define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
229#define TI_GPIO_LOCK_INIT(_sc) \
230 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
231 "ti_gpio", MTX_SPIN)
232#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)

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239 * @bank: The bank to read from
240 * @off: The offset of a register from the GPIO register address range
241 *
242 *
243 * RETURNS:
244 * 32-bit value read from the register.
245 */
246static inline uint32_t
149 * Macros for driver mutex locking
150 */
151#define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
152#define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
153#define TI_GPIO_LOCK_INIT(_sc) \
154 mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
155 "ti_gpio", MTX_SPIN)
156#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)

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163 * @bank: The bank to read from
164 * @off: The offset of a register from the GPIO register address range
165 *
166 *
167 * RETURNS:
168 * 32-bit value read from the register.
169 */
170static inline uint32_t
247ti_gpio_read_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off)
171ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
248{
172{
249 return (bus_read_4(sc->sc_mem_res[bank], off));
173 return (bus_read_4(sc->sc_mem_res, off));
250}
251
252/**
253 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
254 * @sc: GPIO device context
255 * @bank: The bank to write to
256 * @off: The offset of a register from the GPIO register address range
257 * @val: The value to write into the register
258 *
259 * RETURNS:
260 * nothing
261 */
262static inline void
174}
175
176/**
177 * ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
178 * @sc: GPIO device context
179 * @bank: The bank to write to
180 * @off: The offset of a register from the GPIO register address range
181 * @val: The value to write into the register
182 *
183 * RETURNS:
184 * nothing
185 */
186static inline void
263ti_gpio_write_4(struct ti_gpio_softc *sc, unsigned int bank, bus_size_t off,
187ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
264 uint32_t val)
265{
188 uint32_t val)
189{
266 bus_write_4(sc->sc_mem_res[bank], off, val);
190 bus_write_4(sc->sc_mem_res, off, val);
267}
268
269static inline void
191}
192
193static inline void
270ti_gpio_intr_clr(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
194ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
271{
272
273 /* We clear both set of registers. */
195{
196
197 /* We clear both set of registers. */
274 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_0, mask);
275 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_CLR_1, mask);
198 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
199 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
276}
277
278static inline void
200}
201
202static inline void
279ti_gpio_intr_set(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
203ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
280{
281
282 /*
283 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
284 * also activate only the first interrupt.
285 */
204{
205
206 /*
207 * On OMAP4 we unmask only the MPU interrupt and on AM335x we
208 * also activate only the first interrupt.
209 */
286 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_SET_0, mask);
210 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
287}
288
289static inline void
211}
212
213static inline void
290ti_gpio_intr_ack(struct ti_gpio_softc *sc, unsigned int bank, uint32_t mask)
214ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
291{
292
293 /*
294 * Acknowledge the interrupt on both registers even if we use only
295 * the first one.
296 */
215{
216
217 /*
218 * Acknowledge the interrupt on both registers even if we use only
219 * the first one.
220 */
297 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_0, mask);
298 ti_gpio_write_4(sc, bank, TI_GPIO_IRQSTATUS_1, mask);
221 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
222 ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
299}
300
301static inline uint32_t
223}
224
225static inline uint32_t
302ti_gpio_intr_status(struct ti_gpio_softc *sc, unsigned int bank)
226ti_gpio_intr_status(struct ti_gpio_softc *sc)
303{
304 uint32_t reg;
305
306 /* Get the status from both registers. */
227{
228 uint32_t reg;
229
230 /* Get the status from both registers. */
307 reg = ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_0);
308 reg |= ti_gpio_read_4(sc, bank, TI_GPIO_IRQSTATUS_1);
231 reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
232 reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
309
310 return (reg);
311}
312
313static device_t
314ti_gpio_get_bus(device_t dev)
315{
316 struct ti_gpio_softc *sc;

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332 *
333 * RETURNS:
334 * Returns 0 on success otherwise an error code
335 */
336static int
337ti_gpio_pin_max(device_t dev, int *maxpin)
338{
339
233
234 return (reg);
235}
236
237static device_t
238ti_gpio_get_bus(device_t dev)
239{
240 struct ti_gpio_softc *sc;

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256 *
257 * RETURNS:
258 * Returns 0 on success otherwise an error code
259 */
260static int
261ti_gpio_pin_max(device_t dev, int *maxpin)
262{
263
340 *maxpin = ti_max_gpio_banks() * PINS_PER_BANK - 1;
264 *maxpin = PINS_PER_BANK - 1;
341
342 return (0);
343}
344
345static int
346ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
347{
348
265
266 return (0);
267}
268
269static int
270ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
271{
272
349 if (pin >= sc->sc_maxpin ||
350 TI_GPIO_BANK(pin) >= ti_max_gpio_banks() ||
351 sc->sc_mem_res[TI_GPIO_BANK(pin)] == NULL) {
273 if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
352 return (EINVAL);
274 return (EINVAL);
353 }
354
355 return (0);
356}
357
358/**
359 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
360 * @dev: gpio device handle
361 * @pin: the number of the pin

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484 /* Set the GPIO mode and state */
485 TI_GPIO_LOCK(sc);
486 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
487 TI_GPIO_UNLOCK(sc);
488 return (EINVAL);
489 }
490
491 /* If configuring as an output set the "output enable" bit */
275
276 return (0);
277}
278
279/**
280 * ti_gpio_pin_getcaps - Gets the capabilties of a given pin
281 * @dev: gpio device handle
282 * @pin: the number of the pin

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405 /* Set the GPIO mode and state */
406 TI_GPIO_LOCK(sc);
407 if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
408 TI_GPIO_UNLOCK(sc);
409 return (EINVAL);
410 }
411
412 /* If configuring as an output set the "output enable" bit */
492 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE);
413 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
493 if (flags & GPIO_PIN_INPUT)
494 oe |= TI_GPIO_MASK(pin);
495 else
496 oe &= ~TI_GPIO_MASK(pin);
414 if (flags & GPIO_PIN_INPUT)
415 oe |= TI_GPIO_MASK(pin);
416 else
417 oe &= ~TI_GPIO_MASK(pin);
497 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE, oe);
418 ti_gpio_write_4(sc, TI_GPIO_OE, oe);
498 TI_GPIO_UNLOCK(sc);
499
500 return (0);
501}
502
503/**
504 * ti_gpio_pin_set - Sets the current level on a GPIO pin
505 * @dev: gpio device handle

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524 if (ti_gpio_valid_pin(sc, pin) != 0)
525 return (EINVAL);
526
527 TI_GPIO_LOCK(sc);
528 if (value == GPIO_PIN_LOW)
529 reg = TI_GPIO_CLEARDATAOUT;
530 else
531 reg = TI_GPIO_SETDATAOUT;
419 TI_GPIO_UNLOCK(sc);
420
421 return (0);
422}
423
424/**
425 * ti_gpio_pin_set - Sets the current level on a GPIO pin
426 * @dev: gpio device handle

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445 if (ti_gpio_valid_pin(sc, pin) != 0)
446 return (EINVAL);
447
448 TI_GPIO_LOCK(sc);
449 if (value == GPIO_PIN_LOW)
450 reg = TI_GPIO_CLEARDATAOUT;
451 else
452 reg = TI_GPIO_SETDATAOUT;
532 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin));
453 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
533 TI_GPIO_UNLOCK(sc);
534
535 return (0);
536}
537
538/**
539 * ti_gpio_pin_get - Gets the current level on a GPIO pin
540 * @dev: gpio device handle

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560 if (ti_gpio_valid_pin(sc, pin) != 0)
561 return (EINVAL);
562
563 /*
564 * Return data from output latch when set as output and from the
565 * input register otherwise.
566 */
567 TI_GPIO_LOCK(sc);
454 TI_GPIO_UNLOCK(sc);
455
456 return (0);
457}
458
459/**
460 * ti_gpio_pin_get - Gets the current level on a GPIO pin
461 * @dev: gpio device handle

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481 if (ti_gpio_valid_pin(sc, pin) != 0)
482 return (EINVAL);
483
484 /*
485 * Return data from output latch when set as output and from the
486 * input register otherwise.
487 */
488 TI_GPIO_LOCK(sc);
568 oe = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_OE);
489 oe = ti_gpio_read_4(sc, TI_GPIO_OE);
569 if (oe & TI_GPIO_MASK(pin))
570 reg = TI_GPIO_DATAIN;
571 else
572 reg = TI_GPIO_DATAOUT;
490 if (oe & TI_GPIO_MASK(pin))
491 reg = TI_GPIO_DATAIN;
492 else
493 reg = TI_GPIO_DATAOUT;
573 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), reg);
494 val = ti_gpio_read_4(sc, reg);
574 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
575 TI_GPIO_UNLOCK(sc);
576
577 return (0);
578}
579
580/**
581 * ti_gpio_pin_toggle - Toggles a given GPIO pin

--- 14 unchanged lines hidden (view full) ---

596 uint32_t reg, val;
597
598 sc = device_get_softc(dev);
599 if (ti_gpio_valid_pin(sc, pin) != 0)
600 return (EINVAL);
601
602 /* Toggle the pin */
603 TI_GPIO_LOCK(sc);
495 *value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
496 TI_GPIO_UNLOCK(sc);
497
498 return (0);
499}
500
501/**
502 * ti_gpio_pin_toggle - Toggles a given GPIO pin

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517 uint32_t reg, val;
518
519 sc = device_get_softc(dev);
520 if (ti_gpio_valid_pin(sc, pin) != 0)
521 return (EINVAL);
522
523 /* Toggle the pin */
524 TI_GPIO_LOCK(sc);
604 val = ti_gpio_read_4(sc, TI_GPIO_BANK(pin), TI_GPIO_DATAOUT);
525 val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
605 if (val & TI_GPIO_MASK(pin))
606 reg = TI_GPIO_CLEARDATAOUT;
607 else
608 reg = TI_GPIO_SETDATAOUT;
526 if (val & TI_GPIO_MASK(pin))
527 reg = TI_GPIO_CLEARDATAOUT;
528 else
529 reg = TI_GPIO_SETDATAOUT;
609 ti_gpio_write_4(sc, TI_GPIO_BANK(pin), reg, TI_GPIO_MASK(pin));
530 ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
610 TI_GPIO_UNLOCK(sc);
611
612 return (0);
613}
614
615/**
616 * ti_gpio_intr - ISR for all GPIO modules
617 * @arg: the soft context pointer

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626 int bank_last, irq;
627 struct intr_event *event;
628 struct ti_gpio_softc *sc;
629 uint32_t reg;
630
631 sc = (struct ti_gpio_softc *)arg;
632 bank_last = -1;
633 reg = 0; /* squelch bogus gcc warning */
531 TI_GPIO_UNLOCK(sc);
532
533 return (0);
534}
535
536/**
537 * ti_gpio_intr - ISR for all GPIO modules
538 * @arg: the soft context pointer

--- 8 unchanged lines hidden (view full) ---

547 int bank_last, irq;
548 struct intr_event *event;
549 struct ti_gpio_softc *sc;
550 uint32_t reg;
551
552 sc = (struct ti_gpio_softc *)arg;
553 bank_last = -1;
554 reg = 0; /* squelch bogus gcc warning */
555 reg = ti_gpio_intr_status(sc);
634 for (irq = 0; irq < sc->sc_maxpin; irq++) {
556 for (irq = 0; irq < sc->sc_maxpin; irq++) {
635
636 /* Read interrupt status only once for each bank. */
637 if (TI_GPIO_BANK(irq) != bank_last) {
638 reg = ti_gpio_intr_status(sc, TI_GPIO_BANK(irq));
639 bank_last = TI_GPIO_BANK(irq);
640 }
641 if ((reg & TI_GPIO_MASK(irq)) == 0)
642 continue;
643 event = sc->sc_events[irq];
644 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
645 intr_event_handle(event, NULL);
646 else
647 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq);
648 /* Ack the IRQ Status bit. */
557 if ((reg & TI_GPIO_MASK(irq)) == 0)
558 continue;
559 event = sc->sc_events[irq];
560 if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
561 intr_event_handle(event, NULL);
562 else
563 device_printf(sc->sc_dev, "Stray IRQ %d\n", irq);
564 /* Ack the IRQ Status bit. */
649 ti_gpio_intr_ack(sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq));
565 ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq));
650 }
651
652 return (FILTER_HANDLED);
653}
654
655static int
566 }
567
568 return (FILTER_HANDLED);
569}
570
571static int
656ti_gpio_attach_intr(device_t dev)
572ti_gpio_bank_init(device_t dev)
657{
573{
658 int i;
659 struct ti_gpio_softc *sc;
660
661 sc = device_get_softc(dev);
662 for (i = 0; i < ti_max_gpio_intrs(); i++) {
663 if (sc->sc_irq_res[i] == NULL)
664 break;
665
666 /*
667 * Register our interrupt filter for each of the IRQ resources.
668 */
669 if (bus_setup_intr(dev, sc->sc_irq_res[i],
670 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
671 &sc->sc_irq_hdl[i]) != 0) {
672 device_printf(dev,
673 "WARNING: unable to register interrupt filter\n");
674 return (-1);
675 }
676 }
677
678 return (0);
679}
680
681static int
682ti_gpio_detach_intr(device_t dev)
683{
684 int i;
685 struct ti_gpio_softc *sc;
686
687 /* Teardown our interrupt filters. */
688 sc = device_get_softc(dev);
689 for (i = 0; i < ti_max_gpio_intrs(); i++) {
690 if (sc->sc_irq_res[i] == NULL)
691 break;
692
693 if (sc->sc_irq_hdl[i]) {
694 bus_teardown_intr(dev, sc->sc_irq_res[i],
695 sc->sc_irq_hdl[i]);
696 }
697 }
698
699 return (0);
700}
701
702static int
703ti_gpio_bank_init(device_t dev, int bank)
704{
705 int pin;
706 struct ti_gpio_softc *sc;
707 uint32_t flags, reg_oe, rev;
574 int pin;
575 struct ti_gpio_softc *sc;
576 uint32_t flags, reg_oe, rev;
577 clk_ident_t clk;
708
709 sc = device_get_softc(dev);
710
711 /* Enable the interface and functional clocks for the module. */
578
579 sc = device_get_softc(dev);
580
581 /* Enable the interface and functional clocks for the module. */
712 ti_prcm_clk_enable(GPIO0_CLK + ti_first_gpio_bank() + bank);
582 clk = ti_hwmods_get_clock(dev);
583 if (clk == INVALID_CLK_IDENT) {
584 device_printf(dev, "failed to get device id based on ti,hwmods\n");
585 return (EINVAL);
586 }
713
587
588 sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
589 ti_prcm_clk_enable(clk);
590
714 /*
715 * Read the revision number of the module. TI don't publish the
716 * actual revision numbers, so instead the values have been
717 * determined by experimentation.
718 */
591 /*
592 * Read the revision number of the module. TI don't publish the
593 * actual revision numbers, so instead the values have been
594 * determined by experimentation.
595 */
719 rev = ti_gpio_read_4(sc, bank, TI_GPIO_REVISION);
596 rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
720
721 /* Check the revision. */
722 if (rev != ti_gpio_rev()) {
723 device_printf(dev, "Warning: could not determine the revision "
597
598 /* Check the revision. */
599 if (rev != ti_gpio_rev()) {
600 device_printf(dev, "Warning: could not determine the revision "
724 "of GPIO module %d (revision:0x%08x)\n", bank, rev);
601 "of GPIO module (revision:0x%08x)\n", rev);
725 return (EINVAL);
726 }
727
728 /* Disable interrupts for all pins. */
602 return (EINVAL);
603 }
604
605 /* Disable interrupts for all pins. */
729 ti_gpio_intr_clr(sc, bank, 0xffffffff);
606 ti_gpio_intr_clr(sc, 0xffffffff);
730
731 /* Init OE register based on pads configuration. */
732 reg_oe = 0xffffffff;
733 for (pin = 0; pin < PINS_PER_BANK; pin++) {
607
608 /* Init OE register based on pads configuration. */
609 reg_oe = 0xffffffff;
610 for (pin = 0; pin < PINS_PER_BANK; pin++) {
734 TI_GPIO_GET_FLAGS(dev, PINS_PER_BANK * bank + pin, &flags);
611 TI_GPIO_GET_FLAGS(dev, pin, &flags);
735 if (flags & GPIO_PIN_OUTPUT)
736 reg_oe &= ~(1UL << pin);
737 }
612 if (flags & GPIO_PIN_OUTPUT)
613 reg_oe &= ~(1UL << pin);
614 }
738 ti_gpio_write_4(sc, bank, TI_GPIO_OE, reg_oe);
615 ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
739
740 return (0);
741}
742
743/**
744 * ti_gpio_attach - attach function for the driver
745 * @dev: gpio device handle
746 *

--- 8 unchanged lines hidden (view full) ---

755 */
756static int
757ti_gpio_attach(device_t dev)
758{
759 struct ti_gpio_softc *sc;
760 unsigned int i;
761 int err;
762
616
617 return (0);
618}
619
620/**
621 * ti_gpio_attach - attach function for the driver
622 * @dev: gpio device handle
623 *

--- 8 unchanged lines hidden (view full) ---

632 */
633static int
634ti_gpio_attach(device_t dev)
635{
636 struct ti_gpio_softc *sc;
637 unsigned int i;
638 int err;
639
763 if (ti_gpio_sc != NULL)
764 return (ENXIO);
765
766 ti_gpio_sc = sc = device_get_softc(dev);
640 sc = device_get_softc(dev);
767 sc->sc_dev = dev;
768 TI_GPIO_LOCK_INIT(sc);
769 ti_gpio_pin_max(dev, &sc->sc_maxpin);
770 sc->sc_maxpin++;
771
641 sc->sc_dev = dev;
642 TI_GPIO_LOCK_INIT(sc);
643 ti_gpio_pin_max(dev, &sc->sc_maxpin);
644 sc->sc_maxpin++;
645
772 /* There are up to 6 different GPIO register sets located in different
773 * memory areas on the chip. The memory range should have been set for
774 * the driver when it was added as a child.
775 */
776 if (bus_alloc_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res) != 0) {
646 sc->sc_mem_rid = 0;
647 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
648 &sc->sc_mem_rid, RF_ACTIVE);
649 if (!sc->sc_mem_res) {
777 device_printf(dev, "Error: could not allocate mem resources\n");
778 ti_gpio_detach(dev);
779 return (ENXIO);
780 }
781
650 device_printf(dev, "Error: could not allocate mem resources\n");
651 ti_gpio_detach(dev);
652 return (ENXIO);
653 }
654
782 /* Request the IRQ resources */
783 if (bus_alloc_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res) != 0) {
655 sc->sc_irq_rid = 0;
656 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
657 &sc->sc_irq_rid, RF_ACTIVE);
658 if (!sc->sc_irq_res) {
784 device_printf(dev, "Error: could not allocate irq resources\n");
785 ti_gpio_detach(dev);
786 return (ENXIO);
787 }
788
659 device_printf(dev, "Error: could not allocate irq resources\n");
660 ti_gpio_detach(dev);
661 return (ENXIO);
662 }
663
789 /* Setup the IRQ resources */
790 if (ti_gpio_attach_intr(dev) != 0) {
791 device_printf(dev, "Error: could not setup irq handlers\n");
664 /*
665 * Register our interrupt filter for each of the IRQ resources.
666 */
667 if (bus_setup_intr(dev, sc->sc_irq_res,
668 INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
669 &sc->sc_irq_hdl) != 0) {
670 device_printf(dev,
671 "WARNING: unable to register interrupt filter\n");
792 ti_gpio_detach(dev);
793 return (ENXIO);
794 }
795
796 /*
797 * Initialize the interrupt settings. The default is active-low
798 * interrupts.
799 */

--- 6 unchanged lines hidden (view full) ---

806 for (i = 0; i < sc->sc_maxpin; i++) {
807 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
808 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
809 }
810
811 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin,
812 M_DEVBUF, M_WAITOK | M_ZERO);
813
672 ti_gpio_detach(dev);
673 return (ENXIO);
674 }
675
676 /*
677 * Initialize the interrupt settings. The default is active-low
678 * interrupts.
679 */

--- 6 unchanged lines hidden (view full) ---

686 for (i = 0; i < sc->sc_maxpin; i++) {
687 sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
688 sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
689 }
690
691 sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin,
692 M_DEVBUF, M_WAITOK | M_ZERO);
693
694 sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin,
695 M_DEVBUF, M_WAITOK | M_ZERO);
696
814 /* We need to go through each block and ensure the clocks are running and
815 * the module is enabled. It might be better to do this only when the
816 * pins are configured which would result in less power used if the GPIO
817 * pins weren't used ...
818 */
697 /* We need to go through each block and ensure the clocks are running and
698 * the module is enabled. It might be better to do this only when the
699 * pins are configured which would result in less power used if the GPIO
700 * pins weren't used ...
701 */
819 for (i = 0; i < ti_max_gpio_banks(); i++) {
820 if (sc->sc_mem_res[i] != NULL) {
821 /* Initialize the GPIO module. */
822 err = ti_gpio_bank_init(dev, i);
823 if (err != 0) {
824 ti_gpio_detach(dev);
825 return (err);
826 }
702 if (sc->sc_mem_res != NULL) {
703 /* Initialize the GPIO module. */
704 err = ti_gpio_bank_init(dev);
705 if (err != 0) {
706 ti_gpio_detach(dev);
707 return (err);
827 }
828 }
708 }
709 }
710
829 sc->sc_busdev = gpiobus_attach_bus(dev);
830 if (sc->sc_busdev == NULL) {
831 ti_gpio_detach(dev);
832 return (ENXIO);
833 }
834
835 return (0);
836}

--- 10 unchanged lines hidden (view full) ---

847 *
848 * RETURNS:
849 * Always returns 0
850 */
851static int
852ti_gpio_detach(device_t dev)
853{
854 struct ti_gpio_softc *sc = device_get_softc(dev);
711 sc->sc_busdev = gpiobus_attach_bus(dev);
712 if (sc->sc_busdev == NULL) {
713 ti_gpio_detach(dev);
714 return (ENXIO);
715 }
716
717 return (0);
718}

--- 10 unchanged lines hidden (view full) ---

729 *
730 * RETURNS:
731 * Always returns 0
732 */
733static int
734ti_gpio_detach(device_t dev)
735{
736 struct ti_gpio_softc *sc = device_get_softc(dev);
855 unsigned int i;
856
857 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
858
859 /* Disable all interrupts */
737
738 KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
739
740 /* Disable all interrupts */
860 for (i = 0; i < ti_max_gpio_banks(); i++) {
861 if (sc->sc_mem_res[i] != NULL)
862 ti_gpio_intr_clr(sc, i, 0xffffffff);
863 }
741 if (sc->sc_mem_res != NULL)
742 ti_gpio_intr_clr(sc, 0xffffffff);
864 gpiobus_detach_bus(dev);
865 if (sc->sc_events)
866 free(sc->sc_events, M_DEVBUF);
743 gpiobus_detach_bus(dev);
744 if (sc->sc_events)
745 free(sc->sc_events, M_DEVBUF);
746 if (sc->sc_mask_args)
747 free(sc->sc_mask_args, M_DEVBUF);
867 if (sc->sc_irq_polarity)
868 free(sc->sc_irq_polarity, M_DEVBUF);
869 if (sc->sc_irq_trigger)
870 free(sc->sc_irq_trigger, M_DEVBUF);
871 /* Release the memory and IRQ resources. */
748 if (sc->sc_irq_polarity)
749 free(sc->sc_irq_polarity, M_DEVBUF);
750 if (sc->sc_irq_trigger)
751 free(sc->sc_irq_trigger, M_DEVBUF);
752 /* Release the memory and IRQ resources. */
872 ti_gpio_detach_intr(dev);
873 bus_release_resources(dev, ti_gpio_irq_spec, sc->sc_irq_res);
874 bus_release_resources(dev, ti_gpio_mem_spec, sc->sc_mem_res);
753 if (sc->sc_irq_hdl) {
754 bus_teardown_intr(dev, sc->sc_irq_res,
755 sc->sc_irq_hdl);
756 }
757 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
758 sc->sc_irq_res);
759 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
760 sc->sc_mem_res);
875 TI_GPIO_LOCK_DESTROY(sc);
876
877 return (0);
878}
879
880static uint32_t
881ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
882{

--- 12 unchanged lines hidden (view full) ---

895 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
896 return (TI_GPIO_RISINGDETECT);
897 }
898
899 return (0);
900}
901
902static void
761 TI_GPIO_LOCK_DESTROY(sc);
762
763 return (0);
764}
765
766static uint32_t
767ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
768{

--- 12 unchanged lines hidden (view full) ---

781 else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
782 return (TI_GPIO_RISINGDETECT);
783 }
784
785 return (0);
786}
787
788static void
903ti_gpio_mask_irq(void *source)
789ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq)
904{
790{
905 int irq;
906 uint32_t reg, val;
907
791 uint32_t reg, val;
792
908 irq = (int)source;
909 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0)
793 if (ti_gpio_valid_pin(sc, irq) != 0)
910 return;
911
794 return;
795
912 TI_GPIO_LOCK(ti_gpio_sc);
913 ti_gpio_intr_clr(ti_gpio_sc, TI_GPIO_BANK(irq), TI_GPIO_MASK(irq));
914 reg = ti_gpio_intr_reg(ti_gpio_sc, irq);
796 TI_GPIO_LOCK(sc);
797 ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq));
798 reg = ti_gpio_intr_reg(sc, irq);
915 if (reg != 0) {
799 if (reg != 0) {
916 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg);
800 val = ti_gpio_read_4(sc, reg);
917 val &= ~TI_GPIO_MASK(irq);
801 val &= ~TI_GPIO_MASK(irq);
918 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val);
802 ti_gpio_write_4(sc, reg, val);
919 }
803 }
920 TI_GPIO_UNLOCK(ti_gpio_sc);
804 TI_GPIO_UNLOCK(sc);
921}
922
923static void
805}
806
807static void
924ti_gpio_unmask_irq(void *source)
808ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq)
925{
809{
926 int irq;
927 uint32_t reg, val;
928
810 uint32_t reg, val;
811
929 irq = (int)source;
930 if (ti_gpio_valid_pin(ti_gpio_sc, irq) != 0)
812 if (ti_gpio_valid_pin(sc, irq) != 0)
931 return;
932
813 return;
814
933 TI_GPIO_LOCK(ti_gpio_sc);
934 reg = ti_gpio_intr_reg(ti_gpio_sc, irq);
815 TI_GPIO_LOCK(sc);
816 reg = ti_gpio_intr_reg(sc, irq);
935 if (reg != 0) {
817 if (reg != 0) {
936 val = ti_gpio_read_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg);
818 val = ti_gpio_read_4(sc, reg);
937 val |= TI_GPIO_MASK(irq);
819 val |= TI_GPIO_MASK(irq);
938 ti_gpio_write_4(ti_gpio_sc, TI_GPIO_BANK(irq), reg, val);
939 ti_gpio_intr_set(ti_gpio_sc, TI_GPIO_BANK(irq),
940 TI_GPIO_MASK(irq));
820 ti_gpio_write_4(sc, reg, val);
821 ti_gpio_intr_set(sc, TI_GPIO_MASK(irq));
941 }
822 }
942 TI_GPIO_UNLOCK(ti_gpio_sc);
823 TI_GPIO_UNLOCK(sc);
943}
944
824}
825
826static void
827ti_gpio_mask_irq(void *source)
828{
829 struct ti_gpio_mask_arg *arg = source;
830
831 ti_gpio_mask_irq_internal(arg->softc, arg->pin);
832}
833
834static void
835ti_gpio_unmask_irq(void *source)
836{
837 struct ti_gpio_mask_arg *arg = source;
838
839 ti_gpio_unmask_irq_internal(arg->softc, arg->pin);
840}
841
945static int
946ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid,
947 struct resource *res)
948{
949 int pin;
950
951 if (type != SYS_RES_IRQ)
952 return (ENXIO);

--- 42 unchanged lines hidden (view full) ---

995 * avoid losing interrupts.
996 */
997 oldreg = ti_gpio_intr_reg(sc, irq);
998 sc->sc_irq_trigger[irq] = trig;
999 sc->sc_irq_polarity[irq] = pol;
1000 reg = ti_gpio_intr_reg(sc, irq);
1001 if (reg != 0) {
1002 /* Apply the new settings. */
842static int
843ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid,
844 struct resource *res)
845{
846 int pin;
847
848 if (type != SYS_RES_IRQ)
849 return (ENXIO);

--- 42 unchanged lines hidden (view full) ---

892 * avoid losing interrupts.
893 */
894 oldreg = ti_gpio_intr_reg(sc, irq);
895 sc->sc_irq_trigger[irq] = trig;
896 sc->sc_irq_polarity[irq] = pol;
897 reg = ti_gpio_intr_reg(sc, irq);
898 if (reg != 0) {
899 /* Apply the new settings. */
1003 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), reg);
900 val = ti_gpio_read_4(sc, reg);
1004 val |= TI_GPIO_MASK(irq);
901 val |= TI_GPIO_MASK(irq);
1005 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), reg, val);
902 ti_gpio_write_4(sc, reg, val);
1006 }
1007 if (reg != oldreg && oldreg != 0) {
1008 /* Remove the old settings. */
903 }
904 if (reg != oldreg && oldreg != 0) {
905 /* Remove the old settings. */
1009 val = ti_gpio_read_4(sc, TI_GPIO_BANK(irq), oldreg);
906 val = ti_gpio_read_4(sc, oldreg);
1010 val &= ~TI_GPIO_MASK(irq);
907 val &= ~TI_GPIO_MASK(irq);
1011 ti_gpio_write_4(sc, TI_GPIO_BANK(irq), oldreg, val);
908 ti_gpio_write_4(sc, oldreg, val);
1012 }
1013 TI_GPIO_UNLOCK(sc);
1014
1015 return (0);
1016}
1017
1018static int
1019ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires,

--- 6 unchanged lines hidden (view full) ---

1026
1027 sc = device_get_softc(dev);
1028 pin = rman_get_start(ires);
1029 if (ti_gpio_valid_pin(sc, pin) != 0)
1030 panic("%s: bad pin %d", __func__, pin);
1031
1032 event = sc->sc_events[pin];
1033 if (event == NULL) {
909 }
910 TI_GPIO_UNLOCK(sc);
911
912 return (0);
913}
914
915static int
916ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires,

--- 6 unchanged lines hidden (view full) ---

923
924 sc = device_get_softc(dev);
925 pin = rman_get_start(ires);
926 if (ti_gpio_valid_pin(sc, pin) != 0)
927 panic("%s: bad pin %d", __func__, pin);
928
929 event = sc->sc_events[pin];
930 if (event == NULL) {
1034 error = intr_event_create(&event, (void *)(uintptr_t)pin, 0,
931 sc->sc_mask_args[pin].softc = sc;
932 sc->sc_mask_args[pin].pin = pin;
933 error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0,
1035 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL,
1036 "gpio%d pin%d:", device_get_unit(dev), pin);
1037 if (error != 0)
1038 return (error);
1039 sc->sc_events[pin] = event;
1040 }
1041 intr_event_add_handler(event, device_get_nameunit(child), filt,
1042 handler, arg, intr_priority(flags), flags, cookiep);

--- 65 unchanged lines hidden --- 		934 pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL,
935 "gpio%d pin%d:", device_get_unit(dev), pin);
936 if (error != 0)
937 return (error);
938 sc->sc_events[pin] = event;
939 }
940 intr_event_add_handler(event, device_get_nameunit(child), filt,
941 handler, arg, intr_priority(flags), flags, cookiep);

--- 65 unchanged lines hidden ---