| tegra_pcie.c (331888) | tegra_pcie.c (332010) |
|---|---|
| 1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 11 unchanged lines hidden (view full) --- 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> |
| 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_pcie.c 331888 2018-04-02 21:38:50Z gonzo $"); | 28__FBSDID("$FreeBSD: stable/11/sys/arm/nvidia/tegra_pcie.c 332010 2018-04-04 11:30:20Z mmel $"); |
| 29 30/* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 225 unchanged lines hidden (view full) --- 262 u_int flags; 263}; 264 265struct tegra_pcib_port { 266 int enabled; 267 int port_idx; /* chip port index */ 268 int num_lanes; /* number of lanes */ 269 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ | 29 30/* 31 * Nvidia Integrated PCI/PCI-Express controller driver. 32 */ 33 34#include <sys/param.h> 35#include <sys/systm.h> 36#include <sys/bus.h> --- 225 unchanged lines hidden (view full) --- 262 u_int flags; 263}; 264 265struct tegra_pcib_port { 266 int enabled; 267 int port_idx; /* chip port index */ 268 int num_lanes; /* number of lanes */ 269 bus_size_t afi_pex_ctrl; /* offset of afi_pex_ctrl */ |
| 270 phy_t phy; /* port phy */ |
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| 270 271 /* Config space properties. */ 272 bus_addr_t rp_base_addr; /* PA of config window */ 273 bus_size_t rp_size; /* size of config window */ 274 bus_space_handle_t cfg_handle; /* handle of config window */ 275}; 276 277#define TEGRA_PCIB_MAX_PORTS 3 --- 9 unchanged lines hidden (view full) --- 287 struct resource *msi_irq_res; 288 void *intr_cookie; 289 void *msi_intr_cookie; 290 291 struct ofw_pci_range mem_range; 292 struct ofw_pci_range pref_mem_range; 293 struct ofw_pci_range io_range; 294 | 271 272 /* Config space properties. */ 273 bus_addr_t rp_base_addr; /* PA of config window */ 274 bus_size_t rp_size; /* size of config window */ 275 bus_space_handle_t cfg_handle; /* handle of config window */ 276}; 277 278#define TEGRA_PCIB_MAX_PORTS 3 --- 9 unchanged lines hidden (view full) --- 288 struct resource *msi_irq_res; 289 void *intr_cookie; 290 void *msi_intr_cookie; 291 292 struct ofw_pci_range mem_range; 293 struct ofw_pci_range pref_mem_range; 294 struct ofw_pci_range io_range; 295 |
| 295 phy_t phy; | |
| 296 clk_t clk_pex; 297 clk_t clk_afi; 298 clk_t clk_pll_e; 299 clk_t clk_cml; 300 hwreset_t hwreset_pex; 301 hwreset_t hwreset_afi; 302 hwreset_t hwreset_pcie_x; 303 regulator_t supply_avddio_pex; --- 652 unchanged lines hidden (view full) --- 956 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 957 port->num_lanes); 958 goto fail; 959 } 960 961 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 962 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 963 | 296 clk_t clk_pex; 297 clk_t clk_afi; 298 clk_t clk_pll_e; 299 clk_t clk_cml; 300 hwreset_t hwreset_pex; 301 hwreset_t hwreset_afi; 302 hwreset_t hwreset_pcie_x; 303 regulator_t supply_avddio_pex; --- 652 unchanged lines hidden (view full) --- 956 device_printf(sc->dev, "Invalid nvidia,num-lanes: %d\n", 957 port->num_lanes); 958 goto fail; 959 } 960 961 port->afi_pex_ctrl = tegra_pcib_pex_ctrl(sc, port->port_idx); 962 sc->lanes_cfg |= port->num_lanes << (4 * port->port_idx); 963 |
| 964 /* Phy. */ 965 rv = phy_get_by_ofw_name(sc->dev, node, "pcie-0", &port->phy); 966 if (rv != 0) { 967 device_printf(sc->dev, 968 "Cannot get 'pcie-0' phy for port %d\n", 969 port->port_idx); 970 goto fail; 971 } 972 |
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| 964 return (port); 965fail: 966 free(port, M_DEVBUF); 967 return (NULL); 968} 969 970 971static int --- 88 unchanged lines hidden (view full) --- 1060 return (ENXIO); 1061 } 1062 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1063 if (rv != 0) { 1064 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1065 return (ENXIO); 1066 } 1067 | 973 return (port); 974fail: 975 free(port, M_DEVBUF); 976 return (NULL); 977} 978 979 980static int --- 88 unchanged lines hidden (view full) --- 1069 return (ENXIO); 1070 } 1071 rv = clk_get_by_ofw_name(sc->dev, 0, "cml", &sc->clk_cml); 1072 if (rv != 0) { 1073 device_printf(sc->dev, "Cannot get 'cml' clock\n"); 1074 return (ENXIO); 1075 } 1076 |
| 1068 /* Phy. */ 1069 rv = phy_get_by_ofw_name(sc->dev, 0, "pcie", &sc->phy); 1070 if (rv != 0) { 1071 device_printf(sc->dev, "Cannot get 'pcie' phy\n"); 1072 return (ENXIO); 1073 } 1074 | |
| 1075 /* Ports */ 1076 sc->num_ports = 0; 1077 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1078 port = tegra_pcib_parse_port(sc, child); 1079 if (port == NULL) { 1080 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1081 return (ENXIO); 1082 } --- 218 unchanged lines hidden (view full) --- 1301 } 1302 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1303 1304 /* Enable Gen2 support. */ 1305 reg = AFI_RD4(sc, AFI_FUSE); 1306 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1307 AFI_WR4(sc, AFI_FUSE, reg); 1308 | 1077 /* Ports */ 1078 sc->num_ports = 0; 1079 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 1080 port = tegra_pcib_parse_port(sc, child); 1081 if (port == NULL) { 1082 device_printf(sc->dev, "Cannot parse PCIe port node\n"); 1083 return (ENXIO); 1084 } --- 218 unchanged lines hidden (view full) --- 1303 } 1304 AFI_WR4(sc, AFI_PCIE_CONFIG, reg); 1305 1306 /* Enable Gen2 support. */ 1307 reg = AFI_RD4(sc, AFI_FUSE); 1308 reg &= ~AFI_FUSE_PCIE_T0_GEN2_DIS; 1309 AFI_WR4(sc, AFI_FUSE, reg); 1310 |
| 1309 /* Enable PCIe phy. */ 1310 rv = phy_enable(sc->dev, sc->phy); 1311 if (rv != 0) { 1312 device_printf(sc->dev, "Cannot enable phy\n"); 1313 return (rv); | 1311 for (i = 0; i < TEGRA_PCIB_MAX_PORTS; i++) { 1312 if (sc->ports[i] != NULL) { 1313 rv = phy_enable(sc->dev, sc->ports[i]->phy); 1314 if (rv != 0) { 1315 device_printf(sc->dev, 1316 "Cannot enable phy for port %d\n", 1317 sc->ports[i]->port_idx); 1318 return (rv); 1319 } 1320 } |
| 1314 } 1315 | 1321 } 1322 |
| 1323 |
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| 1316 rv = hwreset_deassert(sc->hwreset_pcie_x); 1317 if (rv != 0) { 1318 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1319 return (rv); 1320 } 1321 1322 /* Enable config space. */ 1323 reg = AFI_RD4(sc, AFI_CONFIGURATION); --- 305 unchanged lines hidden --- | 1324 rv = hwreset_deassert(sc->hwreset_pcie_x); 1325 if (rv != 0) { 1326 device_printf(sc->dev, "Cannot unreset 'pci_x' reset\n"); 1327 return (rv); 1328 } 1329 1330 /* Enable config space. */ 1331 reg = AFI_RD4(sc, AFI_CONFIGURATION); --- 305 unchanged lines hidden --- |