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atomic.h (241080) atomic.h (245135)
1/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
2
3/*-
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
7 * All rights reserved.
8 *

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28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
1/* $NetBSD: atomic.h,v 1.1 2002/10/19 12:22:34 bsh Exp $ */
2
3/*-
4 * Copyright (C) 2003-2004 Olivier Houchard
5 * Copyright (C) 1994-1997 Mark Brinicombe
6 * Copyright (C) 1994 Brini
7 * All rights reserved.
8 *

--- 19 unchanged lines hidden (view full) ---

28 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
31 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
33 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
34 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * $FreeBSD: head/sys/arm/include/atomic.h 241080 2012-10-01 05:12:17Z andrew $
36 * $FreeBSD: head/sys/arm/include/atomic.h 245135 2013-01-07 20:36:51Z gonzo $
37 */
38
39#ifndef _MACHINE_ATOMIC_H_
40#define _MACHINE_ATOMIC_H_
41
42#include <sys/types.h>
43
44#ifndef _KERNEL
45#include <machine/sysarch.h>
46#else
47#include <machine/cpuconf.h>
48#endif
49
37 */
38
39#ifndef _MACHINE_ATOMIC_H_
40#define _MACHINE_ATOMIC_H_
41
42#include <sys/types.h>
43
44#ifndef _KERNEL
45#include <machine/sysarch.h>
46#else
47#include <machine/cpuconf.h>
48#endif
49
50#define mb()
51#define wmb()
52#define rmb()
50#if defined (__ARM_ARCH_7__) || defined (__ARM_ARCH_7A__)
51#define isb() __asm __volatile("isb" : : : "memory")
52#define dsb() __asm __volatile("dsb" : : : "memory")
53#define dmb() __asm __volatile("dmb" : : : "memory")
54#elif defined (__ARM_ARCH_6__) || defined (__ARM_ARCH_6J__) || \
55 defined (__ARM_ARCH_6K__) || defined (__ARM_ARCH_6Z__) || \
56 defined (__ARM_ARCH_6ZK__)
57#define isb() __asm __volatile("mcr p15, 0, %0, c7, c5, 4" : : "r" (0) : "memory")
58#define dsb() __asm __volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0) : "memory")
59#define dmb() __asm __volatile("mcr p15, 0, %0, c7, c10, 5" : : "r" (0) : "memory")
60#else
61#define isb()
62#define dsb()
63#define dmb()
64#endif
53
65
66#define mb() dmb()
67#define wmb() dmb()
68#define rmb() dmb()
69
54#ifndef I32_bit
55#define I32_bit (1 << 7) /* IRQ disable */
56#endif
57#ifndef F32_bit
58#define F32_bit (1 << 6) /* FIQ disable */
59#endif
60
61/*

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70#ifndef I32_bit
71#define I32_bit (1 << 7) /* IRQ disable */
72#endif
73#ifndef F32_bit
74#define F32_bit (1 << 6) /* FIQ disable */
75#endif
76
77/*

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