36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/malloc.h>
43#include <sys/rman.h>
44#include <sys/timeet.h>
45#include <sys/timetc.h>
46
47#include <dev/sound/pcm/sound.h>
48#include <dev/sound/chip.h>
49#include <mixer_if.h>
50
51#include <dev/fdt/fdt_common.h>
52#include <dev/ofw/openfirm.h>
53#include <dev/ofw/ofw_bus.h>
54#include <dev/ofw/ofw_bus_subr.h>
55
56#include <machine/bus.h>
57#include <machine/cpu.h>
58#include <machine/intr.h>
59
60#include <arm/freescale/imx/imx6_sdma.h>
61#include <arm/freescale/imx/imx6_anatopvar.h>
62#include <arm/freescale/imx/imx_ccmvar.h>
63
64#define READ4(_sc, _reg) \
65 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
66#define WRITE4(_sc, _reg, _val) \
67 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
68
69#define SSI_NCHANNELS 1
70
71/* i.MX6 SSI registers */
72
73#define SSI_STX0 0x00 /* Transmit Data Register n */
74#define SSI_STX1 0x04 /* Transmit Data Register n */
75#define SSI_SRX0 0x08 /* Receive Data Register n */
76#define SSI_SRX1 0x0C /* Receive Data Register n */
77#define SSI_SCR 0x10 /* Control Register */
78#define SCR_I2S_MODE_S 5 /* I2S Mode Select. */
79#define SCR_I2S_MODE_M 0x3
80#define SCR_SYN (1 << 4)
81#define SCR_NET (1 << 3) /* Network mode */
82#define SCR_RE (1 << 2) /* Receive Enable. */
83#define SCR_TE (1 << 1) /* Transmit Enable. */
84#define SCR_SSIEN (1 << 0) /* SSI Enable */
85#define SSI_SISR 0x14 /* Interrupt Status Register */
86#define SSI_SIER 0x18 /* Interrupt Enable Register */
87#define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */
88#define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */
89#define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */
90#define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */
91#define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */
92#define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */
93#define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */
94#define SSI_STCR 0x1C /* Transmit Configuration Register */
95#define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */
96#define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */
97#define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */
98#define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */
99#define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */
100#define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */
101#define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */
102#define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */
103#define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */
104#define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */
105#define SSI_SRCR 0x20 /* Receive Configuration Register */
106#define SSI_STCCR 0x24 /* Transmit Clock Control Register */
107#define STCCR_DIV2 (1 << 18) /* Divide By 2. */
108#define STCCR_PSR (1 << 17) /* Divide clock by 8. */
109#define WL3_WL0_S 13
110#define WL3_WL0_M 0xf
111#define DC4_DC0_S 8
112#define DC4_DC0_M 0x1f
113#define PM7_PM0_S 0
114#define PM7_PM0_M 0xff
115#define SSI_SRCCR 0x28 /* Receive Clock Control Register */
116#define SSI_SFCSR 0x2C /* FIFO Control/Status Register */
117#define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */
118#define SFCSR_RFWM1_M 0xf
119#define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */
120#define SFCSR_TFWM1_M 0xf
121#define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */
122#define SFCSR_RFWM0_M 0xf
123#define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */
124#define SFCSR_TFWM0_M 0xf
125#define SSI_SACNT 0x38 /* AC97 Control Register */
126#define SSI_SACADD 0x3C /* AC97 Command Address Register */
127#define SSI_SACDAT 0x40 /* AC97 Command Data Register */
128#define SSI_SATAG 0x44 /* AC97 Tag Register */
129#define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */
130#define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */
131#define SSI_SACCST 0x50 /* AC97 Channel Status Register */
132#define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */
133#define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */
134
135static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
136
137uint32_t ssi_dma_intr(void *arg, int chn);
138
139struct ssi_rate {
140 uint32_t speed;
141 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
142 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
143 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
144 /* More dividers to configure can be added here */
145};
146
147static struct ssi_rate rate_map[] = {
148 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
149 /* TODO: add more frequences */
150 { 0, 0 },
151};
152
153/*
154 * i.MX6 example bit clock formula
155 *
156 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
157 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
158 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
159 * | | | | | | | | | | |
160 * Fref ------/ | | | | | | | | | |
161 * PLL4 div select -/ | | | | | | | | |
162 * PLL4 num --------------/ | | | | | | | |
163 * PLL4 denom -------------------/ | | | | | | |
164 * PLL4 post div ---------------------/ | | | | | |
165 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | |
166 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | |
167 * SSI PM7_PM0_S ---------------------------------/ | | |
168 * SSI Fixed divider ---------------------------------/ | |
169 * SSI DIV2 ----------------------------------------------/ |
170 * SSI PSR (prescaler /1 or /8) ------------------------------/
171 *
172 * MCLK (Master clock) depends on DAC, usually BCLK * 4
173 */
174
175struct sc_info {
176 struct resource *res[2];
177 bus_space_tag_t bst;
178 bus_space_handle_t bsh;
179 device_t dev;
180 struct mtx *lock;
181 void *ih;
182 int pos;
183 int dma_size;
184 bus_dma_tag_t dma_tag;
185 bus_dmamap_t dma_map;
186 bus_addr_t buf_base_phys;
187 uint32_t *buf_base;
188 struct sdma_conf *conf;
189 struct ssi_rate *sr;
190 struct sdma_softc *sdma_sc;
191 int sdma_ev_rx;
192 int sdma_ev_tx;
193 int sdma_channel;
194};
195
196/* Channel registers */
197struct sc_chinfo {
198 struct snd_dbuf *buffer;
199 struct pcm_channel *channel;
200 struct sc_pcminfo *parent;
201
202 /* Channel information */
203 uint32_t dir;
204 uint32_t format;
205
206 /* Flags */
207 uint32_t run;
208};
209
210/* PCM device private data */
211struct sc_pcminfo {
212 device_t dev;
213 uint32_t (*ih)(struct sc_pcminfo *scp);
214 uint32_t chnum;
215 struct sc_chinfo chan[SSI_NCHANNELS];
216 struct sc_info *sc;
217};
218
219static struct resource_spec ssi_spec[] = {
220 { SYS_RES_MEMORY, 0, RF_ACTIVE },
221 { SYS_RES_IRQ, 0, RF_ACTIVE },
222 { -1, 0 }
223};
224
225static int setup_dma(struct sc_pcminfo *scp);
226static void setup_ssi(struct sc_info *);
227static void ssi_configure_clock(struct sc_info *);
228
229/*
230 * Mixer interface.
231 */
232
233static int
234ssimixer_init(struct snd_mixer *m)
235{
236 struct sc_pcminfo *scp;
237 struct sc_info *sc;
238 int mask;
239
240 scp = mix_getdevinfo(m);
241 sc = scp->sc;
242
243 if (sc == NULL)
244 return -1;
245
246 mask = SOUND_MASK_PCM;
247 mask |= SOUND_MASK_VOLUME;
248
249 snd_mtxlock(sc->lock);
250 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
251 mix_setdevs(m, mask);
252 snd_mtxunlock(sc->lock);
253
254 return (0);
255}
256
257static int
258ssimixer_set(struct snd_mixer *m, unsigned dev,
259 unsigned left, unsigned right)
260{
261 struct sc_pcminfo *scp;
262
263 scp = mix_getdevinfo(m);
264
265 /* Here we can configure hardware volume on our DAC */
266
267#if 1
268 device_printf(scp->dev, "ssimixer_set() %d %d\n",
269 left, right);
270#endif
271
272 return (0);
273}
274
275static kobj_method_t ssimixer_methods[] = {
276 KOBJMETHOD(mixer_init, ssimixer_init),
277 KOBJMETHOD(mixer_set, ssimixer_set),
278 KOBJMETHOD_END
279};
280MIXER_DECLARE(ssimixer);
281
282
283/*
284 * Channel interface.
285 */
286
287static void *
288ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
289 struct pcm_channel *c, int dir)
290{
291 struct sc_pcminfo *scp;
292 struct sc_chinfo *ch;
293 struct sc_info *sc;
294
295 scp = (struct sc_pcminfo *)devinfo;
296 sc = scp->sc;
297
298 snd_mtxlock(sc->lock);
299 ch = &scp->chan[0];
300 ch->dir = dir;
301 ch->run = 0;
302 ch->buffer = b;
303 ch->channel = c;
304 ch->parent = scp;
305 snd_mtxunlock(sc->lock);
306
307 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
308 device_printf(scp->dev, "Can't setup sndbuf.\n");
309 return NULL;
310 }
311
312 return ch;
313}
314
315static int
316ssichan_free(kobj_t obj, void *data)
317{
318 struct sc_chinfo *ch = data;
319 struct sc_pcminfo *scp = ch->parent;
320 struct sc_info *sc = scp->sc;
321
322#if 0
323 device_printf(scp->dev, "ssichan_free()\n");
324#endif
325
326 snd_mtxlock(sc->lock);
327 /* TODO: free channel buffer */
328 snd_mtxunlock(sc->lock);
329
330 return (0);
331}
332
333static int
334ssichan_setformat(kobj_t obj, void *data, uint32_t format)
335{
336 struct sc_chinfo *ch = data;
337
338 ch->format = format;
339
340 return (0);
341}
342
343static uint32_t
344ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
345{
346 struct sc_pcminfo *scp;
347 struct sc_chinfo *ch;
348 struct ssi_rate *sr;
349 struct sc_info *sc;
350 int threshold;
351 int i;
352
353 ch = data;
354 scp = ch->parent;
355 sc = scp->sc;
356
357 sr = NULL;
358
359 /* First look for equal frequency. */
360 for (i = 0; rate_map[i].speed != 0; i++) {
361 if (rate_map[i].speed == speed)
362 sr = &rate_map[i];
363 }
364
365 /* If no match, just find nearest. */
366 if (sr == NULL) {
367 for (i = 0; rate_map[i].speed != 0; i++) {
368 sr = &rate_map[i];
369 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
370 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
371 if (speed < threshold)
372 break;
373 }
374 }
375
376 sc->sr = sr;
377
378 ssi_configure_clock(sc);
379
380 return (sr->speed);
381}
382
383static void
384ssi_configure_clock(struct sc_info *sc)
385{
386 struct ssi_rate *sr;
387
388 sr = sc->sr;
389
390 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
391
392 /* Configure other dividers here, if any */
393}
394
395static uint32_t
396ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
397{
398 struct sc_chinfo *ch = data;
399 struct sc_pcminfo *scp = ch->parent;
400 struct sc_info *sc = scp->sc;
401
402 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
403
404 setup_dma(scp);
405
406 return (sndbuf_getblksz(ch->buffer));
407}
408
409uint32_t
410ssi_dma_intr(void *arg, int chn)
411{
412 struct sc_pcminfo *scp;
413 struct sdma_conf *conf;
414 struct sc_chinfo *ch;
415 struct sc_info *sc;
416 int bufsize;
417
418 scp = arg;
419 ch = &scp->chan[0];
420 sc = scp->sc;
421 conf = sc->conf;
422
423 bufsize = sndbuf_getsize(ch->buffer);
424
425 sc->pos += conf->period;
426 if (sc->pos >= bufsize)
427 sc->pos -= bufsize;
428
429 if (ch->run)
430 chn_intr(ch->channel);
431
432 return (0);
433}
434
435static int
436find_sdma_controller(struct sc_info *sc)
437{
438 struct sdma_softc *sdma_sc;
439 phandle_t node, sdma_node;
440 device_t sdma_dev;
441 int dts_value[8];
442 int len;
443
444 if ((node = ofw_bus_get_node(sc->dev)) == -1)
445 return (ENXIO);
446
447 if ((len = OF_getproplen(node, "dmas")) <= 0)
448 return (ENXIO);
449
450 OF_getprop(node, "dmas", &dts_value, len);
451
452 sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]);
453 sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]);
454
455 sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0]));
456
457 sdma_sc = NULL;
458
459 sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
460 if (sdma_dev)
461 sdma_sc = device_get_softc(sdma_dev);
462
463 if (sdma_sc == NULL) {
464 device_printf(sc->dev, "No sDMA found. Can't operate\n");
465 return (ENXIO);
| 36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/malloc.h>
43#include <sys/rman.h>
44#include <sys/timeet.h>
45#include <sys/timetc.h>
46
47#include <dev/sound/pcm/sound.h>
48#include <dev/sound/chip.h>
49#include <mixer_if.h>
50
51#include <dev/fdt/fdt_common.h>
52#include <dev/ofw/openfirm.h>
53#include <dev/ofw/ofw_bus.h>
54#include <dev/ofw/ofw_bus_subr.h>
55
56#include <machine/bus.h>
57#include <machine/cpu.h>
58#include <machine/intr.h>
59
60#include <arm/freescale/imx/imx6_sdma.h>
61#include <arm/freescale/imx/imx6_anatopvar.h>
62#include <arm/freescale/imx/imx_ccmvar.h>
63
64#define READ4(_sc, _reg) \
65 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
66#define WRITE4(_sc, _reg, _val) \
67 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
68
69#define SSI_NCHANNELS 1
70
71/* i.MX6 SSI registers */
72
73#define SSI_STX0 0x00 /* Transmit Data Register n */
74#define SSI_STX1 0x04 /* Transmit Data Register n */
75#define SSI_SRX0 0x08 /* Receive Data Register n */
76#define SSI_SRX1 0x0C /* Receive Data Register n */
77#define SSI_SCR 0x10 /* Control Register */
78#define SCR_I2S_MODE_S 5 /* I2S Mode Select. */
79#define SCR_I2S_MODE_M 0x3
80#define SCR_SYN (1 << 4)
81#define SCR_NET (1 << 3) /* Network mode */
82#define SCR_RE (1 << 2) /* Receive Enable. */
83#define SCR_TE (1 << 1) /* Transmit Enable. */
84#define SCR_SSIEN (1 << 0) /* SSI Enable */
85#define SSI_SISR 0x14 /* Interrupt Status Register */
86#define SSI_SIER 0x18 /* Interrupt Enable Register */
87#define SIER_RDMAE (1 << 22) /* Receive DMA Enable. */
88#define SIER_RIE (1 << 21) /* Receive Interrupt Enable. */
89#define SIER_TDMAE (1 << 20) /* Transmit DMA Enable. */
90#define SIER_TIE (1 << 19) /* Transmit Interrupt Enable. */
91#define SIER_TDE0IE (1 << 12) /* Transmit Data Register Empty 0. */
92#define SIER_TUE0IE (1 << 8) /* Transmitter Underrun Error 0. */
93#define SIER_TFE0IE (1 << 0) /* Transmit FIFO Empty 0 IE. */
94#define SSI_STCR 0x1C /* Transmit Configuration Register */
95#define STCR_TXBIT0 (1 << 9) /* Transmit Bit 0 shift MSB/LSB */
96#define STCR_TFEN1 (1 << 8) /* Transmit FIFO Enable 1. */
97#define STCR_TFEN0 (1 << 7) /* Transmit FIFO Enable 0. */
98#define STCR_TFDIR (1 << 6) /* Transmit Frame Direction. */
99#define STCR_TXDIR (1 << 5) /* Transmit Clock Direction. */
100#define STCR_TSHFD (1 << 4) /* Transmit Shift Direction. */
101#define STCR_TSCKP (1 << 3) /* Transmit Clock Polarity. */
102#define STCR_TFSI (1 << 2) /* Transmit Frame Sync Invert. */
103#define STCR_TFSL (1 << 1) /* Transmit Frame Sync Length. */
104#define STCR_TEFS (1 << 0) /* Transmit Early Frame Sync. */
105#define SSI_SRCR 0x20 /* Receive Configuration Register */
106#define SSI_STCCR 0x24 /* Transmit Clock Control Register */
107#define STCCR_DIV2 (1 << 18) /* Divide By 2. */
108#define STCCR_PSR (1 << 17) /* Divide clock by 8. */
109#define WL3_WL0_S 13
110#define WL3_WL0_M 0xf
111#define DC4_DC0_S 8
112#define DC4_DC0_M 0x1f
113#define PM7_PM0_S 0
114#define PM7_PM0_M 0xff
115#define SSI_SRCCR 0x28 /* Receive Clock Control Register */
116#define SSI_SFCSR 0x2C /* FIFO Control/Status Register */
117#define SFCSR_RFWM1_S 20 /* Receive FIFO Empty WaterMark 1 */
118#define SFCSR_RFWM1_M 0xf
119#define SFCSR_TFWM1_S 16 /* Transmit FIFO Empty WaterMark 1 */
120#define SFCSR_TFWM1_M 0xf
121#define SFCSR_RFWM0_S 4 /* Receive FIFO Empty WaterMark 0 */
122#define SFCSR_RFWM0_M 0xf
123#define SFCSR_TFWM0_S 0 /* Transmit FIFO Empty WaterMark 0 */
124#define SFCSR_TFWM0_M 0xf
125#define SSI_SACNT 0x38 /* AC97 Control Register */
126#define SSI_SACADD 0x3C /* AC97 Command Address Register */
127#define SSI_SACDAT 0x40 /* AC97 Command Data Register */
128#define SSI_SATAG 0x44 /* AC97 Tag Register */
129#define SSI_STMSK 0x48 /* Transmit Time Slot Mask Register */
130#define SSI_SRMSK 0x4C /* Receive Time Slot Mask Register */
131#define SSI_SACCST 0x50 /* AC97 Channel Status Register */
132#define SSI_SACCEN 0x54 /* AC97 Channel Enable Register */
133#define SSI_SACCDIS 0x58 /* AC97 Channel Disable Register */
134
135static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
136
137uint32_t ssi_dma_intr(void *arg, int chn);
138
139struct ssi_rate {
140 uint32_t speed;
141 uint32_t mfi; /* PLL4 Multiplication Factor Integer */
142 uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
143 uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
144 /* More dividers to configure can be added here */
145};
146
147static struct ssi_rate rate_map[] = {
148 { 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
149 /* TODO: add more frequences */
150 { 0, 0 },
151};
152
153/*
154 * i.MX6 example bit clock formula
155 *
156 * BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
157 * (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
158 * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^
159 * | | | | | | | | | | |
160 * Fref ------/ | | | | | | | | | |
161 * PLL4 div select -/ | | | | | | | | |
162 * PLL4 num --------------/ | | | | | | | |
163 * PLL4 denom -------------------/ | | | | | | |
164 * PLL4 post div ---------------------/ | | | | | |
165 * CCM ssi pre div (CCM_CS1CDR) ----------/ | | | | |
166 * CCM ssi post div (CCM_CS1CDR) -------------/ | | | |
167 * SSI PM7_PM0_S ---------------------------------/ | | |
168 * SSI Fixed divider ---------------------------------/ | |
169 * SSI DIV2 ----------------------------------------------/ |
170 * SSI PSR (prescaler /1 or /8) ------------------------------/
171 *
172 * MCLK (Master clock) depends on DAC, usually BCLK * 4
173 */
174
175struct sc_info {
176 struct resource *res[2];
177 bus_space_tag_t bst;
178 bus_space_handle_t bsh;
179 device_t dev;
180 struct mtx *lock;
181 void *ih;
182 int pos;
183 int dma_size;
184 bus_dma_tag_t dma_tag;
185 bus_dmamap_t dma_map;
186 bus_addr_t buf_base_phys;
187 uint32_t *buf_base;
188 struct sdma_conf *conf;
189 struct ssi_rate *sr;
190 struct sdma_softc *sdma_sc;
191 int sdma_ev_rx;
192 int sdma_ev_tx;
193 int sdma_channel;
194};
195
196/* Channel registers */
197struct sc_chinfo {
198 struct snd_dbuf *buffer;
199 struct pcm_channel *channel;
200 struct sc_pcminfo *parent;
201
202 /* Channel information */
203 uint32_t dir;
204 uint32_t format;
205
206 /* Flags */
207 uint32_t run;
208};
209
210/* PCM device private data */
211struct sc_pcminfo {
212 device_t dev;
213 uint32_t (*ih)(struct sc_pcminfo *scp);
214 uint32_t chnum;
215 struct sc_chinfo chan[SSI_NCHANNELS];
216 struct sc_info *sc;
217};
218
219static struct resource_spec ssi_spec[] = {
220 { SYS_RES_MEMORY, 0, RF_ACTIVE },
221 { SYS_RES_IRQ, 0, RF_ACTIVE },
222 { -1, 0 }
223};
224
225static int setup_dma(struct sc_pcminfo *scp);
226static void setup_ssi(struct sc_info *);
227static void ssi_configure_clock(struct sc_info *);
228
229/*
230 * Mixer interface.
231 */
232
233static int
234ssimixer_init(struct snd_mixer *m)
235{
236 struct sc_pcminfo *scp;
237 struct sc_info *sc;
238 int mask;
239
240 scp = mix_getdevinfo(m);
241 sc = scp->sc;
242
243 if (sc == NULL)
244 return -1;
245
246 mask = SOUND_MASK_PCM;
247 mask |= SOUND_MASK_VOLUME;
248
249 snd_mtxlock(sc->lock);
250 pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
251 mix_setdevs(m, mask);
252 snd_mtxunlock(sc->lock);
253
254 return (0);
255}
256
257static int
258ssimixer_set(struct snd_mixer *m, unsigned dev,
259 unsigned left, unsigned right)
260{
261 struct sc_pcminfo *scp;
262
263 scp = mix_getdevinfo(m);
264
265 /* Here we can configure hardware volume on our DAC */
266
267#if 1
268 device_printf(scp->dev, "ssimixer_set() %d %d\n",
269 left, right);
270#endif
271
272 return (0);
273}
274
275static kobj_method_t ssimixer_methods[] = {
276 KOBJMETHOD(mixer_init, ssimixer_init),
277 KOBJMETHOD(mixer_set, ssimixer_set),
278 KOBJMETHOD_END
279};
280MIXER_DECLARE(ssimixer);
281
282
283/*
284 * Channel interface.
285 */
286
287static void *
288ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
289 struct pcm_channel *c, int dir)
290{
291 struct sc_pcminfo *scp;
292 struct sc_chinfo *ch;
293 struct sc_info *sc;
294
295 scp = (struct sc_pcminfo *)devinfo;
296 sc = scp->sc;
297
298 snd_mtxlock(sc->lock);
299 ch = &scp->chan[0];
300 ch->dir = dir;
301 ch->run = 0;
302 ch->buffer = b;
303 ch->channel = c;
304 ch->parent = scp;
305 snd_mtxunlock(sc->lock);
306
307 if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
308 device_printf(scp->dev, "Can't setup sndbuf.\n");
309 return NULL;
310 }
311
312 return ch;
313}
314
315static int
316ssichan_free(kobj_t obj, void *data)
317{
318 struct sc_chinfo *ch = data;
319 struct sc_pcminfo *scp = ch->parent;
320 struct sc_info *sc = scp->sc;
321
322#if 0
323 device_printf(scp->dev, "ssichan_free()\n");
324#endif
325
326 snd_mtxlock(sc->lock);
327 /* TODO: free channel buffer */
328 snd_mtxunlock(sc->lock);
329
330 return (0);
331}
332
333static int
334ssichan_setformat(kobj_t obj, void *data, uint32_t format)
335{
336 struct sc_chinfo *ch = data;
337
338 ch->format = format;
339
340 return (0);
341}
342
343static uint32_t
344ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
345{
346 struct sc_pcminfo *scp;
347 struct sc_chinfo *ch;
348 struct ssi_rate *sr;
349 struct sc_info *sc;
350 int threshold;
351 int i;
352
353 ch = data;
354 scp = ch->parent;
355 sc = scp->sc;
356
357 sr = NULL;
358
359 /* First look for equal frequency. */
360 for (i = 0; rate_map[i].speed != 0; i++) {
361 if (rate_map[i].speed == speed)
362 sr = &rate_map[i];
363 }
364
365 /* If no match, just find nearest. */
366 if (sr == NULL) {
367 for (i = 0; rate_map[i].speed != 0; i++) {
368 sr = &rate_map[i];
369 threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
370 ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
371 if (speed < threshold)
372 break;
373 }
374 }
375
376 sc->sr = sr;
377
378 ssi_configure_clock(sc);
379
380 return (sr->speed);
381}
382
383static void
384ssi_configure_clock(struct sc_info *sc)
385{
386 struct ssi_rate *sr;
387
388 sr = sc->sr;
389
390 pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
391
392 /* Configure other dividers here, if any */
393}
394
395static uint32_t
396ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
397{
398 struct sc_chinfo *ch = data;
399 struct sc_pcminfo *scp = ch->parent;
400 struct sc_info *sc = scp->sc;
401
402 sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
403
404 setup_dma(scp);
405
406 return (sndbuf_getblksz(ch->buffer));
407}
408
409uint32_t
410ssi_dma_intr(void *arg, int chn)
411{
412 struct sc_pcminfo *scp;
413 struct sdma_conf *conf;
414 struct sc_chinfo *ch;
415 struct sc_info *sc;
416 int bufsize;
417
418 scp = arg;
419 ch = &scp->chan[0];
420 sc = scp->sc;
421 conf = sc->conf;
422
423 bufsize = sndbuf_getsize(ch->buffer);
424
425 sc->pos += conf->period;
426 if (sc->pos >= bufsize)
427 sc->pos -= bufsize;
428
429 if (ch->run)
430 chn_intr(ch->channel);
431
432 return (0);
433}
434
435static int
436find_sdma_controller(struct sc_info *sc)
437{
438 struct sdma_softc *sdma_sc;
439 phandle_t node, sdma_node;
440 device_t sdma_dev;
441 int dts_value[8];
442 int len;
443
444 if ((node = ofw_bus_get_node(sc->dev)) == -1)
445 return (ENXIO);
446
447 if ((len = OF_getproplen(node, "dmas")) <= 0)
448 return (ENXIO);
449
450 OF_getprop(node, "dmas", &dts_value, len);
451
452 sc->sdma_ev_rx = fdt32_to_cpu(dts_value[1]);
453 sc->sdma_ev_tx = fdt32_to_cpu(dts_value[5]);
454
455 sdma_node = OF_node_from_xref(fdt32_to_cpu(dts_value[0]));
456
457 sdma_sc = NULL;
458
459 sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
460 if (sdma_dev)
461 sdma_sc = device_get_softc(sdma_dev);
462
463 if (sdma_sc == NULL) {
464 device_printf(sc->dev, "No sDMA found. Can't operate\n");
465 return (ENXIO);
|
467
468 sc->sdma_sc = sdma_sc;
469
470 return (0);
471};
472
473static int
474setup_dma(struct sc_pcminfo *scp)
475{
476 struct sdma_conf *conf;
477 struct sc_chinfo *ch;
478 struct sc_info *sc;
479 int fmt;
480
481 ch = &scp->chan[0];
482 sc = scp->sc;
483 conf = sc->conf;
484
485 conf->ih = ssi_dma_intr;
486 conf->ih_user = scp;
487 conf->saddr = sc->buf_base_phys;
488 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
489 conf->event = sc->sdma_ev_tx; /* SDMA TX event */
490 conf->period = sndbuf_getblksz(ch->buffer);
491 conf->num_bd = sndbuf_getblkcnt(ch->buffer);
492
493 /*
494 * Word Length
495 * Can be 32, 24, 16 or 8 for sDMA.
496 *
497 * SSI supports 24 at max.
498 */
499
500 fmt = sndbuf_getfmt(ch->buffer);
501
502 if (fmt & AFMT_16BIT) {
503 conf->word_length = 16;
504 conf->command = CMD_2BYTES;
505 } else if (fmt & AFMT_24BIT) {
506 conf->word_length = 24;
507 conf->command = CMD_3BYTES;
508 } else {
509 device_printf(sc->dev, "Unknown format\n");
510 return (-1);
511 }
512
513 return (0);
514}
515
516static int
517ssi_start(struct sc_pcminfo *scp)
518{
519 struct sc_info *sc;
520 int reg;
521
522 sc = scp->sc;
523
524 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
525 device_printf(sc->dev, "Can't configure sDMA\n");
526 return (-1);
527 }
528
529 /* Enable DMA interrupt */
530 reg = (SIER_TDMAE);
531 WRITE4(sc, SSI_SIER, reg);
532
533 sdma_start(sc->sdma_channel);
534
535 return (0);
536}
537
538static int
539ssi_stop(struct sc_pcminfo *scp)
540{
541 struct sc_info *sc;
542 int reg;
543
544 sc = scp->sc;
545
546 reg = READ4(sc, SSI_SIER);
547 reg &= ~(SIER_TDMAE);
548 WRITE4(sc, SSI_SIER, reg);
549
550 sdma_stop(sc->sdma_channel);
551
552 bzero(sc->buf_base, sc->dma_size);
553
554 return (0);
555}
556
557static int
558ssichan_trigger(kobj_t obj, void *data, int go)
559{
560 struct sc_pcminfo *scp;
561 struct sc_chinfo *ch;
562 struct sc_info *sc;
563
564 ch = data;
565 scp = ch->parent;
566 sc = scp->sc;
567
568 snd_mtxlock(sc->lock);
569
570 switch (go) {
571 case PCMTRIG_START:
572#if 0
573 device_printf(scp->dev, "trigger start\n");
574#endif
575 ch->run = 1;
576
577 ssi_start(scp);
578
579 break;
580
581 case PCMTRIG_STOP:
582 case PCMTRIG_ABORT:
583#if 0
584 device_printf(scp->dev, "trigger stop or abort\n");
585#endif
586 ch->run = 0;
587
588 ssi_stop(scp);
589
590 break;
591 }
592
593 snd_mtxunlock(sc->lock);
594
595 return (0);
596}
597
598static uint32_t
599ssichan_getptr(kobj_t obj, void *data)
600{
601 struct sc_pcminfo *scp;
602 struct sc_chinfo *ch;
603 struct sc_info *sc;
604
605 ch = data;
606 scp = ch->parent;
607 sc = scp->sc;
608
609 return (sc->pos);
610}
611
612static uint32_t ssi_pfmt[] = {
613 SND_FORMAT(AFMT_S24_LE, 2, 0),
614 0
615};
616
617static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
618
619static struct pcmchan_caps *
620ssichan_getcaps(kobj_t obj, void *data)
621{
622
623 return (&ssi_pcaps);
624}
625
626static kobj_method_t ssichan_methods[] = {
627 KOBJMETHOD(channel_init, ssichan_init),
628 KOBJMETHOD(channel_free, ssichan_free),
629 KOBJMETHOD(channel_setformat, ssichan_setformat),
630 KOBJMETHOD(channel_setspeed, ssichan_setspeed),
631 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
632 KOBJMETHOD(channel_trigger, ssichan_trigger),
633 KOBJMETHOD(channel_getptr, ssichan_getptr),
634 KOBJMETHOD(channel_getcaps, ssichan_getcaps),
635 KOBJMETHOD_END
636};
637CHANNEL_DECLARE(ssichan);
638
639static int
640ssi_probe(device_t dev)
641{
642
643 if (!ofw_bus_status_okay(dev))
644 return (ENXIO);
645
646 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
647 return (ENXIO);
648
649 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
650 return (BUS_PROBE_DEFAULT);
651}
652
653static void
654ssi_intr(void *arg)
655{
656 struct sc_pcminfo *scp;
657 struct sc_chinfo *ch;
658 struct sc_info *sc;
659
660 scp = arg;
661 sc = scp->sc;
662 ch = &scp->chan[0];
663
664 /* We don't use SSI interrupt */
665#if 0
666 device_printf(sc->dev, "SSI Intr 0x%08x\n",
667 READ4(sc, SSI_SISR));
668#endif
669}
670
671static void
672setup_ssi(struct sc_info *sc)
673{
674 int reg;
675
676 reg = READ4(sc, SSI_STCCR);
677 reg &= ~(WL3_WL0_M << WL3_WL0_S);
678 reg |= (0xb << WL3_WL0_S); /* 24 bit */
679 reg &= ~(DC4_DC0_M << DC4_DC0_S);
680 reg |= (1 << DC4_DC0_S); /* 2 words per frame */
681 reg &= ~(STCCR_DIV2); /* Divide by 1 */
682 reg &= ~(STCCR_PSR); /* Divide by 1 */
683 reg &= ~(PM7_PM0_M << PM7_PM0_S);
684 reg |= (1 << PM7_PM0_S); /* Divide by 2 */
685 WRITE4(sc, SSI_STCCR, reg);
686
687 reg = READ4(sc, SSI_SFCSR);
688 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
689 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
690 WRITE4(sc, SSI_SFCSR, reg);
691
692 reg = READ4(sc, SSI_STCR);
693 reg |= (STCR_TFEN0);
694 reg &= ~(STCR_TFEN1);
695 reg &= ~(STCR_TSHFD); /* MSB */
696 reg |= (STCR_TXBIT0);
697 reg |= (STCR_TXDIR | STCR_TFDIR);
698 reg |= (STCR_TSCKP); /* falling edge */
699 reg |= (STCR_TFSI);
700 reg &= ~(STCR_TFSI); /* active high frame sync */
701 reg &= ~(STCR_TFSL);
702 reg |= STCR_TEFS;
703 WRITE4(sc, SSI_STCR, reg);
704
705 reg = READ4(sc, SSI_SCR);
706 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
707 reg |= (SCR_SSIEN | SCR_TE);
708 reg |= (SCR_NET);
709 reg |= (SCR_SYN);
710 WRITE4(sc, SSI_SCR, reg);
711}
712
713static void
714ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
715{
716 bus_addr_t *addr;
717
718 if (err)
719 return;
720
721 addr = (bus_addr_t*)arg;
722 *addr = segs[0].ds_addr;
723}
724
725static int
726ssi_attach(device_t dev)
727{
728 char status[SND_STATUSLEN];
729 struct sc_pcminfo *scp;
730 struct sc_info *sc;
731 int err;
732
733 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
734 sc->dev = dev;
735 sc->sr = &rate_map[0];
736 sc->pos = 0;
737 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
738
739 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
740 if (sc->lock == NULL) {
741 device_printf(dev, "Cant create mtx\n");
742 return (ENXIO);
743 }
744
745 if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
746 device_printf(dev, "could not allocate resources\n");
747 return (ENXIO);
748 }
749
750 /* Memory interface */
751 sc->bst = rman_get_bustag(sc->res[0]);
752 sc->bsh = rman_get_bushandle(sc->res[0]);
753
754 /* SDMA */
755 if (find_sdma_controller(sc)) {
756 device_printf(dev, "could not find active SDMA\n");
757 return (ENXIO);
758 }
759
760 /* Setup PCM */
761 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
762 scp->sc = sc;
763 scp->dev = dev;
764
765 /*
766 * Maximum possible DMA buffer.
767 * Will be used partialy to match 24 bit word.
768 */
769 sc->dma_size = 131072;
770
771 /*
772 * Must use dma_size boundary as modulo feature required.
773 * Modulo feature allows setup circular buffer.
774 */
775
776 err = bus_dma_tag_create(
777 bus_get_dma_tag(sc->dev),
778 4, sc->dma_size, /* alignment, boundary */
779 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
780 BUS_SPACE_MAXADDR, /* highaddr */
781 NULL, NULL, /* filter, filterarg */
782 sc->dma_size, 1, /* maxsize, nsegments */
783 sc->dma_size, 0, /* maxsegsize, flags */
784 NULL, NULL, /* lockfunc, lockarg */
785 &sc->dma_tag);
786
787 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
788 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
789 if (err) {
790 device_printf(dev, "cannot allocate framebuffer\n");
791 return (ENXIO);
792 }
793
794 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
795 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
796 if (err) {
797 device_printf(dev, "cannot load DMA map\n");
798 return (ENXIO);
799 }
800
801 bzero(sc->buf_base, sc->dma_size);
802
803 /* Setup interrupt handler */
804 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
805 NULL, ssi_intr, scp, &sc->ih);
806 if (err) {
807 device_printf(dev, "Unable to alloc interrupt resource.\n");
808 return (ENXIO);
809 }
810
811 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
812
813 err = pcm_register(dev, scp, 1, 0);
814 if (err) {
815 device_printf(dev, "Can't register pcm.\n");
816 return (ENXIO);
817 }
818
819 scp->chnum = 0;
820 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
821 scp->chnum++;
822
823 snprintf(status, SND_STATUSLEN, "at simplebus");
824 pcm_setstatus(dev, status);
825
826 mixer_init(dev, &ssimixer_class, scp);
827 setup_ssi(sc);
828
829 imx_ccm_ssi_configure(dev);
830
831 sc->sdma_channel = sdma_alloc();
832 if (sc->sdma_channel < 0) {
833 device_printf(sc->dev, "Can't get sDMA channel\n");
834 return (1);
835 }
836
837 return (0);
838}
839
840static device_method_t ssi_pcm_methods[] = {
841 DEVMETHOD(device_probe, ssi_probe),
842 DEVMETHOD(device_attach, ssi_attach),
843 { 0, 0 }
844};
845
846static driver_t ssi_pcm_driver = {
847 "pcm",
848 ssi_pcm_methods,
849 PCM_SOFTC_SIZE,
850};
851
852DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
853MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
854MODULE_VERSION(ssi, 1);
| 467
468 sc->sdma_sc = sdma_sc;
469
470 return (0);
471};
472
473static int
474setup_dma(struct sc_pcminfo *scp)
475{
476 struct sdma_conf *conf;
477 struct sc_chinfo *ch;
478 struct sc_info *sc;
479 int fmt;
480
481 ch = &scp->chan[0];
482 sc = scp->sc;
483 conf = sc->conf;
484
485 conf->ih = ssi_dma_intr;
486 conf->ih_user = scp;
487 conf->saddr = sc->buf_base_phys;
488 conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
489 conf->event = sc->sdma_ev_tx; /* SDMA TX event */
490 conf->period = sndbuf_getblksz(ch->buffer);
491 conf->num_bd = sndbuf_getblkcnt(ch->buffer);
492
493 /*
494 * Word Length
495 * Can be 32, 24, 16 or 8 for sDMA.
496 *
497 * SSI supports 24 at max.
498 */
499
500 fmt = sndbuf_getfmt(ch->buffer);
501
502 if (fmt & AFMT_16BIT) {
503 conf->word_length = 16;
504 conf->command = CMD_2BYTES;
505 } else if (fmt & AFMT_24BIT) {
506 conf->word_length = 24;
507 conf->command = CMD_3BYTES;
508 } else {
509 device_printf(sc->dev, "Unknown format\n");
510 return (-1);
511 }
512
513 return (0);
514}
515
516static int
517ssi_start(struct sc_pcminfo *scp)
518{
519 struct sc_info *sc;
520 int reg;
521
522 sc = scp->sc;
523
524 if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
525 device_printf(sc->dev, "Can't configure sDMA\n");
526 return (-1);
527 }
528
529 /* Enable DMA interrupt */
530 reg = (SIER_TDMAE);
531 WRITE4(sc, SSI_SIER, reg);
532
533 sdma_start(sc->sdma_channel);
534
535 return (0);
536}
537
538static int
539ssi_stop(struct sc_pcminfo *scp)
540{
541 struct sc_info *sc;
542 int reg;
543
544 sc = scp->sc;
545
546 reg = READ4(sc, SSI_SIER);
547 reg &= ~(SIER_TDMAE);
548 WRITE4(sc, SSI_SIER, reg);
549
550 sdma_stop(sc->sdma_channel);
551
552 bzero(sc->buf_base, sc->dma_size);
553
554 return (0);
555}
556
557static int
558ssichan_trigger(kobj_t obj, void *data, int go)
559{
560 struct sc_pcminfo *scp;
561 struct sc_chinfo *ch;
562 struct sc_info *sc;
563
564 ch = data;
565 scp = ch->parent;
566 sc = scp->sc;
567
568 snd_mtxlock(sc->lock);
569
570 switch (go) {
571 case PCMTRIG_START:
572#if 0
573 device_printf(scp->dev, "trigger start\n");
574#endif
575 ch->run = 1;
576
577 ssi_start(scp);
578
579 break;
580
581 case PCMTRIG_STOP:
582 case PCMTRIG_ABORT:
583#if 0
584 device_printf(scp->dev, "trigger stop or abort\n");
585#endif
586 ch->run = 0;
587
588 ssi_stop(scp);
589
590 break;
591 }
592
593 snd_mtxunlock(sc->lock);
594
595 return (0);
596}
597
598static uint32_t
599ssichan_getptr(kobj_t obj, void *data)
600{
601 struct sc_pcminfo *scp;
602 struct sc_chinfo *ch;
603 struct sc_info *sc;
604
605 ch = data;
606 scp = ch->parent;
607 sc = scp->sc;
608
609 return (sc->pos);
610}
611
612static uint32_t ssi_pfmt[] = {
613 SND_FORMAT(AFMT_S24_LE, 2, 0),
614 0
615};
616
617static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
618
619static struct pcmchan_caps *
620ssichan_getcaps(kobj_t obj, void *data)
621{
622
623 return (&ssi_pcaps);
624}
625
626static kobj_method_t ssichan_methods[] = {
627 KOBJMETHOD(channel_init, ssichan_init),
628 KOBJMETHOD(channel_free, ssichan_free),
629 KOBJMETHOD(channel_setformat, ssichan_setformat),
630 KOBJMETHOD(channel_setspeed, ssichan_setspeed),
631 KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
632 KOBJMETHOD(channel_trigger, ssichan_trigger),
633 KOBJMETHOD(channel_getptr, ssichan_getptr),
634 KOBJMETHOD(channel_getcaps, ssichan_getcaps),
635 KOBJMETHOD_END
636};
637CHANNEL_DECLARE(ssichan);
638
639static int
640ssi_probe(device_t dev)
641{
642
643 if (!ofw_bus_status_okay(dev))
644 return (ENXIO);
645
646 if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
647 return (ENXIO);
648
649 device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
650 return (BUS_PROBE_DEFAULT);
651}
652
653static void
654ssi_intr(void *arg)
655{
656 struct sc_pcminfo *scp;
657 struct sc_chinfo *ch;
658 struct sc_info *sc;
659
660 scp = arg;
661 sc = scp->sc;
662 ch = &scp->chan[0];
663
664 /* We don't use SSI interrupt */
665#if 0
666 device_printf(sc->dev, "SSI Intr 0x%08x\n",
667 READ4(sc, SSI_SISR));
668#endif
669}
670
671static void
672setup_ssi(struct sc_info *sc)
673{
674 int reg;
675
676 reg = READ4(sc, SSI_STCCR);
677 reg &= ~(WL3_WL0_M << WL3_WL0_S);
678 reg |= (0xb << WL3_WL0_S); /* 24 bit */
679 reg &= ~(DC4_DC0_M << DC4_DC0_S);
680 reg |= (1 << DC4_DC0_S); /* 2 words per frame */
681 reg &= ~(STCCR_DIV2); /* Divide by 1 */
682 reg &= ~(STCCR_PSR); /* Divide by 1 */
683 reg &= ~(PM7_PM0_M << PM7_PM0_S);
684 reg |= (1 << PM7_PM0_S); /* Divide by 2 */
685 WRITE4(sc, SSI_STCCR, reg);
686
687 reg = READ4(sc, SSI_SFCSR);
688 reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
689 reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
690 WRITE4(sc, SSI_SFCSR, reg);
691
692 reg = READ4(sc, SSI_STCR);
693 reg |= (STCR_TFEN0);
694 reg &= ~(STCR_TFEN1);
695 reg &= ~(STCR_TSHFD); /* MSB */
696 reg |= (STCR_TXBIT0);
697 reg |= (STCR_TXDIR | STCR_TFDIR);
698 reg |= (STCR_TSCKP); /* falling edge */
699 reg |= (STCR_TFSI);
700 reg &= ~(STCR_TFSI); /* active high frame sync */
701 reg &= ~(STCR_TFSL);
702 reg |= STCR_TEFS;
703 WRITE4(sc, SSI_STCR, reg);
704
705 reg = READ4(sc, SSI_SCR);
706 reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
707 reg |= (SCR_SSIEN | SCR_TE);
708 reg |= (SCR_NET);
709 reg |= (SCR_SYN);
710 WRITE4(sc, SSI_SCR, reg);
711}
712
713static void
714ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
715{
716 bus_addr_t *addr;
717
718 if (err)
719 return;
720
721 addr = (bus_addr_t*)arg;
722 *addr = segs[0].ds_addr;
723}
724
725static int
726ssi_attach(device_t dev)
727{
728 char status[SND_STATUSLEN];
729 struct sc_pcminfo *scp;
730 struct sc_info *sc;
731 int err;
732
733 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
734 sc->dev = dev;
735 sc->sr = &rate_map[0];
736 sc->pos = 0;
737 sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
738
739 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
740 if (sc->lock == NULL) {
741 device_printf(dev, "Cant create mtx\n");
742 return (ENXIO);
743 }
744
745 if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
746 device_printf(dev, "could not allocate resources\n");
747 return (ENXIO);
748 }
749
750 /* Memory interface */
751 sc->bst = rman_get_bustag(sc->res[0]);
752 sc->bsh = rman_get_bushandle(sc->res[0]);
753
754 /* SDMA */
755 if (find_sdma_controller(sc)) {
756 device_printf(dev, "could not find active SDMA\n");
757 return (ENXIO);
758 }
759
760 /* Setup PCM */
761 scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
762 scp->sc = sc;
763 scp->dev = dev;
764
765 /*
766 * Maximum possible DMA buffer.
767 * Will be used partialy to match 24 bit word.
768 */
769 sc->dma_size = 131072;
770
771 /*
772 * Must use dma_size boundary as modulo feature required.
773 * Modulo feature allows setup circular buffer.
774 */
775
776 err = bus_dma_tag_create(
777 bus_get_dma_tag(sc->dev),
778 4, sc->dma_size, /* alignment, boundary */
779 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
780 BUS_SPACE_MAXADDR, /* highaddr */
781 NULL, NULL, /* filter, filterarg */
782 sc->dma_size, 1, /* maxsize, nsegments */
783 sc->dma_size, 0, /* maxsegsize, flags */
784 NULL, NULL, /* lockfunc, lockarg */
785 &sc->dma_tag);
786
787 err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
788 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
789 if (err) {
790 device_printf(dev, "cannot allocate framebuffer\n");
791 return (ENXIO);
792 }
793
794 err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
795 sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
796 if (err) {
797 device_printf(dev, "cannot load DMA map\n");
798 return (ENXIO);
799 }
800
801 bzero(sc->buf_base, sc->dma_size);
802
803 /* Setup interrupt handler */
804 err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
805 NULL, ssi_intr, scp, &sc->ih);
806 if (err) {
807 device_printf(dev, "Unable to alloc interrupt resource.\n");
808 return (ENXIO);
809 }
810
811 pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
812
813 err = pcm_register(dev, scp, 1, 0);
814 if (err) {
815 device_printf(dev, "Can't register pcm.\n");
816 return (ENXIO);
817 }
818
819 scp->chnum = 0;
820 pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
821 scp->chnum++;
822
823 snprintf(status, SND_STATUSLEN, "at simplebus");
824 pcm_setstatus(dev, status);
825
826 mixer_init(dev, &ssimixer_class, scp);
827 setup_ssi(sc);
828
829 imx_ccm_ssi_configure(dev);
830
831 sc->sdma_channel = sdma_alloc();
832 if (sc->sdma_channel < 0) {
833 device_printf(sc->dev, "Can't get sDMA channel\n");
834 return (1);
835 }
836
837 return (0);
838}
839
840static device_method_t ssi_pcm_methods[] = {
841 DEVMETHOD(device_probe, ssi_probe),
842 DEVMETHOD(device_attach, ssi_attach),
843 { 0, 0 }
844};
845
846static driver_t ssi_pcm_driver = {
847 "pcm",
848 ssi_pcm_methods,
849 PCM_SOFTC_SIZE,
850};
851
852DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
853MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
854MODULE_VERSION(ssi, 1);
|