| at91_st.c (237115) | at91_st.c (237130) |
|---|---|
| 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2005 Olivier Houchard. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. --- 10 unchanged lines hidden (view full) --- 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> |
| 27__FBSDID("$FreeBSD: head/sys/arm/at91/at91_st.c 237115 2012-06-15 06:38:55Z imp $"); | 27__FBSDID("$FreeBSD: head/sys/arm/at91/at91_st.c 237130 2012-06-15 08:37:50Z imp $"); |
| 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/kernel.h> 32#include <sys/module.h> 33#include <sys/time.h> 34#include <sys/bus.h> 35#include <sys/resource.h> --- 43 unchanged lines hidden (view full) --- 79 at91st_get_timecount, /* get_timecount */ 80 NULL, /* no poll_pps */ 81 0xfffffu, /* counter_mask */ 82 32768, /* frequency */ 83 "AT91RM9200 timer", /* name */ 84 1000 /* quality */ 85}; 86 | 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/kernel.h> 32#include <sys/module.h> 33#include <sys/time.h> 34#include <sys/bus.h> 35#include <sys/resource.h> --- 43 unchanged lines hidden (view full) --- 79 at91st_get_timecount, /* get_timecount */ 80 NULL, /* no poll_pps */ 81 0xfffffu, /* counter_mask */ 82 32768, /* frequency */ 83 "AT91RM9200 timer", /* name */ 84 1000 /* quality */ 85}; 86 |
| 87static void 88at91st_delay(int n) 89{ 90 uint32_t start, end, cur; 91 92 start = st_crtr(); 93 n = (n * 1000) / 32768; 94 if (n <= 0) 95 n = 1; 96 end = (start + n) & ST_CRTR_MASK; 97 cur = start; 98 if (start > end) { 99 while (cur >= start || cur < end) 100 cur = st_crtr(); 101 } else { 102 while (cur < end) 103 cur = st_crtr(); 104 } 105} 106 107static void 108at91st_cpu_reset(void) 109{ 110 /* 111 * Reset the CPU by programmig the watchdog timer to reset the 112 * CPU after 128 'slow' clocks, or about ~4ms. Loop until 113 * the reset happens for safety. 114 */ 115 WR4(ST_WDMR, ST_WDMR_RSTEN | 2); 116 WR4(ST_CR, ST_CR_WDRST); 117 while (1) 118 continue; 119} 120 |
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| 87static int 88at91st_probe(device_t dev) 89{ 90 91 device_set_desc(dev, "ST"); 92 return (0); 93} 94 --- 12 unchanged lines hidden (view full) --- 107 * Real time counter increments every clock cycle, need to set before 108 * initializing clocks so that DELAY works. 109 */ 110 WR4(ST_RTMR, 1); 111 /* Disable all interrupts */ 112 WR4(ST_IDR, 0xffffffff); 113 /* disable watchdog timer */ 114 WR4(ST_WDMR, 0); | 121static int 122at91st_probe(device_t dev) 123{ 124 125 device_set_desc(dev, "ST"); 126 return (0); 127} 128 --- 12 unchanged lines hidden (view full) --- 141 * Real time counter increments every clock cycle, need to set before 142 * initializing clocks so that DELAY works. 143 */ 144 WR4(ST_RTMR, 1); 145 /* Disable all interrupts */ 146 WR4(ST_IDR, 0xffffffff); 147 /* disable watchdog timer */ 148 WR4(ST_WDMR, 0); |
| 149 soc_data.delay = at91st_delay; 150 soc_data.reset = at91st_cpu_reset; // XXX kinda late to be setting this... |
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| 115 116 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list, 117 at91st_watchdog, dev, 0); 118 119 device_printf(dev, 120 "watchdog registered, timeout intervall max. 64 sec\n"); 121 122 at91st_initclocks(timer_softc); --- 93 unchanged lines hidden (view full) --- 216 clock_intr, NULL, NULL, &ih); 217 218 WR4(ST_PIMR, rel_value); 219 220 /* Enable PITS interrupts. */ 221 WR4(ST_IER, ST_SR_PITS); 222 tc_init(&at91st_timecounter); 223} | 151 152 timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list, 153 at91st_watchdog, dev, 0); 154 155 device_printf(dev, 156 "watchdog registered, timeout intervall max. 64 sec\n"); 157 158 at91st_initclocks(timer_softc); --- 93 unchanged lines hidden (view full) --- 252 clock_intr, NULL, NULL, &ih); 253 254 WR4(ST_PIMR, rel_value); 255 256 /* Enable PITS interrupts. */ 257 WR4(ST_IER, ST_SR_PITS); 258 tc_init(&at91st_timecounter); 259} |
| 224 225void 226DELAY(int n) 227{ 228 uint32_t start, end, cur; 229 230 start = st_crtr(); 231 n = (n * 1000) / 32768; 232 if (n <= 0) 233 n = 1; 234 end = (start + n) & ST_CRTR_MASK; 235 cur = start; 236 if (start > end) { 237 while (cur >= start || cur < end) 238 cur = st_crtr(); 239 } else { 240 while (cur < end) 241 cur = st_crtr(); 242 } 243} 244 245void 246cpu_reset(void) 247{ 248 /* 249 * Reset the CPU by programmig the watchdog timer to reset the 250 * CPU after 128 'slow' clocks, or about ~4ms. Loop until 251 * the reset happens for safety. 252 */ 253 WR4(ST_WDMR, ST_WDMR_RSTEN | 2); 254 WR4(ST_CR, ST_CR_WDRST); 255 while (1) 256 continue; 257} | |