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at91_mci.c (194015) at91_mci.c (213496)
1/*-
2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
1/*-
2 * Copyright (c) 2006 Bernd Walter. All rights reserved.
3 * Copyright (c) 2006 M. Warner Losh. All rights reserved.
4 * Copyright (c) 2010 Greg Ansley. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the

--- 8 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the

--- 8 unchanged lines hidden (view full) ---

21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/arm/at91/at91_mci.c 194015 2009-06-11 17:05:13Z avg $");
29__FBSDID("$FreeBSD: head/sys/arm/at91/at91_mci.c 213496 2010-10-06 22:25:21Z cognet $");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bio.h>
33#include <sys/bus.h>
34#include <sys/conf.h>
35#include <sys/endian.h>
36#include <sys/kernel.h>
37#include <sys/kthread.h>
38#include <sys/lock.h>
39#include <sys/malloc.h>
40#include <sys/module.h>
41#include <sys/mutex.h>
42#include <sys/queue.h>
43#include <sys/resource.h>
44#include <sys/rman.h>
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bio.h>
34#include <sys/bus.h>
35#include <sys/conf.h>
36#include <sys/endian.h>
37#include <sys/kernel.h>
38#include <sys/kthread.h>
39#include <sys/lock.h>
40#include <sys/malloc.h>
41#include <sys/module.h>
42#include <sys/mutex.h>
43#include <sys/queue.h>
44#include <sys/resource.h>
45#include <sys/rman.h>
46#include <sys/sysctl.h>
45#include <sys/time.h>
46#include <sys/timetc.h>
47#include <sys/watchdog.h>
48
49#include <machine/bus.h>
50#include <machine/cpu.h>
51#include <machine/cpufunc.h>
52#include <machine/resource.h>
53#include <machine/frame.h>
54#include <machine/intr.h>
47#include <sys/time.h>
48#include <sys/timetc.h>
49#include <sys/watchdog.h>
50
51#include <machine/bus.h>
52#include <machine/cpu.h>
53#include <machine/cpufunc.h>
54#include <machine/resource.h>
55#include <machine/frame.h>
56#include <machine/intr.h>
55#include <arm/at91/at91rm92reg.h>
57
56#include <arm/at91/at91var.h>
57#include <arm/at91/at91_mcireg.h>
58#include <arm/at91/at91_pdcreg.h>
58#include <arm/at91/at91var.h>
59#include <arm/at91/at91_mcireg.h>
60#include <arm/at91/at91_pdcreg.h>
61
59#include <dev/mmc/bridge.h>
60#include <dev/mmc/mmcreg.h>
61#include <dev/mmc/mmcbrvar.h>
62
63#include "mmcbr_if.h"
64
62#include <dev/mmc/bridge.h>
63#include <dev/mmc/mmcreg.h>
64#include <dev/mmc/mmcbrvar.h>
65
66#include "mmcbr_if.h"
67
68#include "opt_at91.h"
69
65#define BBSZ 512
66
67struct at91_mci_softc {
68 void *intrhand; /* Interrupt handle */
69 device_t dev;
70 int sc_cap;
71#define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
70#define BBSZ 512
71
72struct at91_mci_softc {
73 void *intrhand; /* Interrupt handle */
74 device_t dev;
75 int sc_cap;
76#define CAP_HAS_4WIRE 1 /* Has 4 wire bus */
72#define CAP_NEEDS_BOUNCE 2 /* broken hardware needing bounce */
77#define CAP_NEEDS_BYTESWAP 2 /* broken hardware needing bounce */
73 int flags;
78 int flags;
79 int has_4wire;
74#define CMD_STARTED 1
75#define STOP_STARTED 2
76 struct resource *irq_res; /* IRQ resource */
77 struct resource *mem_res; /* Memory resource */
78 struct mtx sc_mtx;
79 bus_dma_tag_t dmatag;
80 bus_dmamap_t map;
81 int mapped;
82 struct mmc_host host;
83 int bus_busy;
84 struct mmc_request *req;
85 struct mmc_command *curcmd;
86 char bounce_buffer[BBSZ];
87};
88
89static inline uint32_t
90RD4(struct at91_mci_softc *sc, bus_size_t off)
91{
80#define CMD_STARTED 1
81#define STOP_STARTED 2
82 struct resource *irq_res; /* IRQ resource */
83 struct resource *mem_res; /* Memory resource */
84 struct mtx sc_mtx;
85 bus_dma_tag_t dmatag;
86 bus_dmamap_t map;
87 int mapped;
88 struct mmc_host host;
89 int bus_busy;
90 struct mmc_request *req;
91 struct mmc_command *curcmd;
92 char bounce_buffer[BBSZ];
93};
94
95static inline uint32_t
96RD4(struct at91_mci_softc *sc, bus_size_t off)
97{
92 return bus_read_4(sc->mem_res, off);
98 return (bus_read_4(sc->mem_res, off));
93}
94
95static inline void
96WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
97{
98 bus_write_4(sc->mem_res, off, val);
99}
100

--- 34 unchanged lines hidden (view full) ---

135at91_mci_init(device_t dev)
136{
137 struct at91_mci_softc *sc = device_get_softc(dev);
138
139 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */
140 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
141 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
142 WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX
99}
100
101static inline void
102WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val)
103{
104 bus_write_4(sc->mem_res, off, val);
105}
106

--- 34 unchanged lines hidden (view full) ---

141at91_mci_init(device_t dev)
142{
143 struct at91_mci_softc *sc = device_get_softc(dev);
144
145 WR4(sc, MCI_CR, MCI_CR_MCIEN); /* Enable controller */
146 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */
147 WR4(sc, MCI_DTOR, MCI_DTOR_DTOMUL_1M | 1);
148 WR4(sc, MCI_MR, 0x834a); // XXX GROSS HACK FROM LINUX
149#ifndef AT91_MCI_SLOT_B
143 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
150 WR4(sc, MCI_SDCR, 0); /* SLOT A, 1 bit bus */
151#else
152 /* XXX Really should add second "unit" but nobody using using
153 * a two slot card that we know of. XXX */
154 WR4(sc, MCI_SDCR, 1); /* SLOT B, 1 bit bus */
155#endif
144}
145
146static void
147at91_mci_fini(device_t dev)
148{
149 struct at91_mci_softc *sc = device_get_softc(dev);
150
151 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */

--- 8 unchanged lines hidden (view full) ---

160 device_set_desc(dev, "MCI mmc/sd host bridge");
161 return (0);
162}
163
164static int
165at91_mci_attach(device_t dev)
166{
167 struct at91_mci_softc *sc = device_get_softc(dev);
156}
157
158static void
159at91_mci_fini(device_t dev)
160{
161 struct at91_mci_softc *sc = device_get_softc(dev);
162
163 WR4(sc, MCI_IDR, 0xffffffff); /* Turn off interrupts */

--- 8 unchanged lines hidden (view full) ---

172 device_set_desc(dev, "MCI mmc/sd host bridge");
173 return (0);
174}
175
176static int
177at91_mci_attach(device_t dev)
178{
179 struct at91_mci_softc *sc = device_get_softc(dev);
168 int err;
180 struct sysctl_ctx_list *sctx;
181 struct sysctl_oid *soid;
169 device_t child;
182 device_t child;
183 int err;
170
171 sc->dev = dev;
184
185 sc->dev = dev;
172 sc->sc_cap = CAP_NEEDS_BOUNCE;
186
187 sc->sc_cap = 0;
188 if (at91_is_rm92())
189 sc->sc_cap |= CAP_NEEDS_BYTESWAP;
173 err = at91_mci_activate(dev);
174 if (err)
175 goto out;
176
177 AT91_MCI_LOCK_INIT(sc);
178
179 /*
180 * Allocate DMA tags and maps

--- 15 unchanged lines hidden (view full) ---

196 * Activate the interrupt
197 */
198 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
199 NULL, at91_mci_intr, sc, &sc->intrhand);
200 if (err) {
201 AT91_MCI_LOCK_DESTROY(sc);
202 goto out;
203 }
190 err = at91_mci_activate(dev);
191 if (err)
192 goto out;
193
194 AT91_MCI_LOCK_INIT(sc);
195
196 /*
197 * Allocate DMA tags and maps

--- 15 unchanged lines hidden (view full) ---

213 * Activate the interrupt
214 */
215 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
216 NULL, at91_mci_intr, sc, &sc->intrhand);
217 if (err) {
218 AT91_MCI_LOCK_DESTROY(sc);
219 goto out;
220 }
221
222 sctx = device_get_sysctl_ctx(dev);
223 soid = device_get_sysctl_tree(dev);
224 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "4wire",
225 CTLFLAG_RW, &sc->has_4wire, 0, "has 4 wire SD Card bus");
226
227#ifdef AT91_MCI_HAS_4WIRE
228 sc->has_4wire = 1;
229#endif
230 if (sc->has_4wire)
231 sc->sc_cap |= CAP_HAS_4WIRE;
232
233 sc->host.f_min = at91_master_clock / 512;
204 sc->host.f_min = 375000;
234 sc->host.f_min = 375000;
205 sc->host.f_max = at91_master_clock / 2; /* Typically 30MHz */
235 sc->host.f_max = at91_master_clock / 2;
236 if (sc->host.f_max > 50000000)
237 sc->host.f_max = 50000000; /* Limit to 50MHz */
238
206 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
239 sc->host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
240 sc->host.caps = 0;
207 if (sc->sc_cap & CAP_HAS_4WIRE)
241 if (sc->sc_cap & CAP_HAS_4WIRE)
208 sc->host.caps = MMC_CAP_4_BIT_DATA;
209 else
210 sc->host.caps = 0;
242 sc->host.caps |= MMC_CAP_4_BIT_DATA;
211 child = device_add_child(dev, "mmc", 0);
212 device_set_ivars(dev, &sc->host);
213 err = bus_generic_attach(dev);
214out:;
215 if (err)
216 at91_mci_deactivate(dev);
217 return (err);
218}

--- 13 unchanged lines hidden (view full) ---

232 int rid;
233
234 sc = device_get_softc(dev);
235 rid = 0;
236 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
237 RF_ACTIVE);
238 if (sc->mem_res == NULL)
239 goto errout;
243 child = device_add_child(dev, "mmc", 0);
244 device_set_ivars(dev, &sc->host);
245 err = bus_generic_attach(dev);
246out:;
247 if (err)
248 at91_mci_deactivate(dev);
249 return (err);
250}

--- 13 unchanged lines hidden (view full) ---

264 int rid;
265
266 sc = device_get_softc(dev);
267 rid = 0;
268 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
269 RF_ACTIVE);
270 if (sc->mem_res == NULL)
271 goto errout;
272
240 rid = 0;
241 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
242 RF_ACTIVE);
243 if (sc->irq_res == NULL)
244 goto errout;
273 rid = 0;
274 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
275 RF_ACTIVE);
276 if (sc->irq_res == NULL)
277 goto errout;
278
245 return (0);
246errout:
247 at91_mci_deactivate(dev);
248 return (ENOMEM);
249}
250
251static void
252at91_mci_deactivate(device_t dev)

--- 58 unchanged lines hidden (view full) ---

311
312static void
313at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
314{
315 uint32_t cmdr, ier = 0, mr;
316 uint32_t *src, *dst;
317 int i;
318 struct mmc_data *data;
279 return (0);
280errout:
281 at91_mci_deactivate(dev);
282 return (ENOMEM);
283}
284
285static void
286at91_mci_deactivate(device_t dev)

--- 58 unchanged lines hidden (view full) ---

345
346static void
347at91_mci_start_cmd(struct at91_mci_softc *sc, struct mmc_command *cmd)
348{
349 uint32_t cmdr, ier = 0, mr;
350 uint32_t *src, *dst;
351 int i;
352 struct mmc_data *data;
319 struct mmc_request *req;
320 void *vaddr;
321 bus_addr_t paddr;
322
323 sc->curcmd = cmd;
324 data = cmd->data;
325 cmdr = cmd->opcode;
353 void *vaddr;
354 bus_addr_t paddr;
355
356 sc->curcmd = cmd;
357 data = cmd->data;
358 cmdr = cmd->opcode;
326 req = cmd->mrq;
359
360 /* XXX Upper layers don't always set this */
361 cmd->mrq = sc->req;
362
327 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
328 cmdr |= MCI_CMDR_RSPTYP_NO;
329 else {
330 /* Allow big timeout for responses */
331 cmdr |= MCI_CMDR_MAXLAT;
332 if (cmd->flags & MMC_RSP_136)
333 cmdr |= MCI_CMDR_RSPTYP_136;
334 else

--- 24 unchanged lines hidden (view full) ---

359 // PDC until we're ready.
360 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
361 WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
362 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
363 if (cmdr & MCI_CMDR_TRCMD_START) {
364 if (cmdr & MCI_CMDR_TRDIR)
365 vaddr = cmd->data->data;
366 else {
363 if (MMC_RSP(cmd->flags) == MMC_RSP_NONE)
364 cmdr |= MCI_CMDR_RSPTYP_NO;
365 else {
366 /* Allow big timeout for responses */
367 cmdr |= MCI_CMDR_MAXLAT;
368 if (cmd->flags & MMC_RSP_136)
369 cmdr |= MCI_CMDR_RSPTYP_136;
370 else

--- 24 unchanged lines hidden (view full) ---

395 // PDC until we're ready.
396 mr = RD4(sc, MCI_MR) & ~MCI_MR_BLKLEN;
397 WR4(sc, MCI_MR, mr | (data->len << 16) | MCI_MR_PDCMODE);
398 WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS | PDC_PTCR_TXTDIS);
399 if (cmdr & MCI_CMDR_TRCMD_START) {
400 if (cmdr & MCI_CMDR_TRDIR)
401 vaddr = cmd->data->data;
402 else {
367 if (sc->sc_cap & CAP_NEEDS_BOUNCE) {
368 vaddr = sc->bounce_buffer;
369 src = (uint32_t *)cmd->data->data;
370 dst = (uint32_t *)vaddr;
403 /* Use bounce buffer even if we don't need
404 * byteswap, since buffer may straddle a page
405 * boundry, and we don't handle multi-segment
406 * transfers in hardware.
407 * (page issues seen from 'bsdlabel -w' which
408 * uses raw geom access to the volume).
409 * Greg Ansley (gja (at) ansley.com)
410 */
411 vaddr = sc->bounce_buffer;
412 src = (uint32_t *)cmd->data->data;
413 dst = (uint32_t *)vaddr;
414 if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
371 for (i = 0; i < data->len / 4; i++)
372 dst[i] = bswap32(src[i]);
415 for (i = 0; i < data->len / 4; i++)
416 dst[i] = bswap32(src[i]);
373 }
374 else
375 vaddr = cmd->data->data;
417 } else
418 memcpy(dst, src, data->len);
376 }
377 data->xfer_len = 0;
378 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
379 at91_mci_getaddr, &paddr, 0) != 0) {
419 }
420 data->xfer_len = 0;
421 if (bus_dmamap_load(sc->dmatag, sc->map, vaddr, data->len,
422 at91_mci_getaddr, &paddr, 0) != 0) {
380 if (req->cmd->flags & STOP_STARTED)
381 req->stop->error = MMC_ERR_NO_MEMORY;
382 else
383 req->cmd->error = MMC_ERR_NO_MEMORY;
423 cmd->error = MMC_ERR_NO_MEMORY;
384 sc->req = NULL;
385 sc->curcmd = NULL;
424 sc->req = NULL;
425 sc->curcmd = NULL;
386 req->done(req);
426 cmd->mrq->done(cmd->mrq);
387 return;
388 }
389 sc->mapped++;
390 if (cmdr & MCI_CMDR_TRDIR) {
391 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
392 WR4(sc, PDC_RPR, paddr);
393 WR4(sc, PDC_RCR, data->len / 4);
394 ier = MCI_SR_ENDRX;

--- 51 unchanged lines hidden (view full) ---

446 struct at91_mci_softc *sc = device_get_softc(brdev);
447
448 AT91_MCI_LOCK(sc);
449 // XXX do we want to be able to queue up multiple commands?
450 // XXX sounds like a good idea, but all protocols are sync, so
451 // XXX maybe the idea is naive...
452 if (sc->req != NULL) {
453 AT91_MCI_UNLOCK(sc);
427 return;
428 }
429 sc->mapped++;
430 if (cmdr & MCI_CMDR_TRDIR) {
431 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_PREREAD);
432 WR4(sc, PDC_RPR, paddr);
433 WR4(sc, PDC_RCR, data->len / 4);
434 ier = MCI_SR_ENDRX;

--- 51 unchanged lines hidden (view full) ---

486 struct at91_mci_softc *sc = device_get_softc(brdev);
487
488 AT91_MCI_LOCK(sc);
489 // XXX do we want to be able to queue up multiple commands?
490 // XXX sounds like a good idea, but all protocols are sync, so
491 // XXX maybe the idea is naive...
492 if (sc->req != NULL) {
493 AT91_MCI_UNLOCK(sc);
454 return EBUSY;
494 return (EBUSY);
455 }
456 sc->req = req;
457 sc->flags = 0;
458 at91_mci_start(sc);
459 AT91_MCI_UNLOCK(sc);
460 return (0);
461}
462

--- 35 unchanged lines hidden (view full) ---

498 uint32_t *walker;
499 struct mmc_command *cmd;
500 int i, len;
501
502 cmd = sc->curcmd;
503 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
504 bus_dmamap_unload(sc->dmatag, sc->map);
505 sc->mapped--;
495 }
496 sc->req = req;
497 sc->flags = 0;
498 at91_mci_start(sc);
499 AT91_MCI_UNLOCK(sc);
500 return (0);
501}
502

--- 35 unchanged lines hidden (view full) ---

538 uint32_t *walker;
539 struct mmc_command *cmd;
540 int i, len;
541
542 cmd = sc->curcmd;
543 bus_dmamap_sync(sc->dmatag, sc->map, BUS_DMASYNC_POSTREAD);
544 bus_dmamap_unload(sc->dmatag, sc->map);
545 sc->mapped--;
506 if (sc->sc_cap & CAP_NEEDS_BOUNCE) {
546 if (sc->sc_cap & CAP_NEEDS_BYTESWAP) {
507 walker = (uint32_t *)cmd->data->data;
508 len = cmd->data->len / 4;
509 for (i = 0; i < len; i++)
510 walker[i] = bswap32(walker[i]);
511 }
512 // Finish up the sequence...
513 WR4(sc, MCI_IDR, MCI_SR_ENDRX);
514 WR4(sc, MCI_IER, MCI_SR_RXBUFF);

--- 133 unchanged lines hidden (view full) ---

648 break;
649 case MMCBR_IVAR_POWER_MODE:
650 *(int *)result = sc->host.ios.power_mode;
651 break;
652 case MMCBR_IVAR_VDD:
653 *(int *)result = sc->host.ios.vdd;
654 break;
655 case MMCBR_IVAR_CAPS:
547 walker = (uint32_t *)cmd->data->data;
548 len = cmd->data->len / 4;
549 for (i = 0; i < len; i++)
550 walker[i] = bswap32(walker[i]);
551 }
552 // Finish up the sequence...
553 WR4(sc, MCI_IDR, MCI_SR_ENDRX);
554 WR4(sc, MCI_IER, MCI_SR_RXBUFF);

--- 133 unchanged lines hidden (view full) ---

688 break;
689 case MMCBR_IVAR_POWER_MODE:
690 *(int *)result = sc->host.ios.power_mode;
691 break;
692 case MMCBR_IVAR_VDD:
693 *(int *)result = sc->host.ios.vdd;
694 break;
695 case MMCBR_IVAR_CAPS:
696 if (sc->has_4wire) {
697 sc->sc_cap |= CAP_HAS_4WIRE;
698 sc->host.caps |= MMC_CAP_4_BIT_DATA;
699 } else {
700 sc->sc_cap &= ~CAP_HAS_4WIRE;
701 sc->host.caps &= ~MMC_CAP_4_BIT_DATA;
702 }
656 *(int *)result = sc->host.caps;
657 break;
658 case MMCBR_IVAR_MAX_DATA:
659 *(int *)result = 1;
660 break;
661 }
662 return (0);
663}

--- 73 unchanged lines hidden --- 		703 *(int *)result = sc->host.caps;
704 break;
705 case MMCBR_IVAR_MAX_DATA:
706 *(int *)result = 1;
707 break;
708 }
709 return (0);
710}

--- 73 unchanged lines hidden ---