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at91_machdep.c (236524) at91_machdep.c (236658)
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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39 * Machine dependant functions for kernel setup
40 *
41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include <sys/cdefs.h>
47__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 236524 2012-06-03 18:34:32Z imp $");
47__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 236658 2012-06-06 06:19:52Z imp $");
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>

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227 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
228 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
229 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
230 }
231
232 return (1 << (cols + rows + banks + bw));
233}
234
48
49#define _ARM32_BUS_DMA_PRIVATE
50#include <sys/param.h>
51#include <sys/systm.h>
52#include <sys/sysproto.h>
53#include <sys/signalvar.h>
54#include <sys/imgact.h>
55#include <sys/kernel.h>

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227 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
228 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
229 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
230 }
231
232 return (1 << (cols + rows + banks + bw));
233}
234
235const char *soc_type_name[] = {
236 [AT91_T_CAP9] = "at91cap9",
237 [AT91_T_RM9200] = "at91rm9200",
238 [AT91_T_SAM9260] = "at91sam9260",
239 [AT91_T_SAM9261] = "at91sam9261",
240 [AT91_T_SAM9263] = "at91sam9263",
241 [AT91_T_SAM9G10] = "at91sam9g10",
242 [AT91_T_SAM9G20] = "at91sam9g20",
243 [AT91_T_SAM9G45] = "at91sam9g45",
244 [AT91_T_SAM9N12] = "at91sam9n12",
245 [AT91_T_SAM9RL] = "at91sam9rl",
246 [AT91_T_SAM9X5] = "at91sam9x5",
247 [AT91_T_NONE] = "UNKNOWN"
248};
249
250const char *soc_subtype_name[] = {
251 [AT91_ST_NONE] = "UNKNOWN",
252 [AT91_ST_RM9200_BGA] = "at91rm9200_bga",
253 [AT91_ST_RM9200_PQFP] = "at91rm9200_pqfp",
254 [AT91_ST_SAM9XE] = "at91sam9xe",
255 [AT91_ST_SAM9G45] = "at91sam9g45",
256 [AT91_ST_SAM9M10] = "at91sam9m10",
257 [AT91_ST_SAM9G46] = "at91sam9g46",
258 [AT91_ST_SAM9M11] = "at91sam9m11",
259 [AT91_ST_SAM9G15] = "at91sam9g15",
260 [AT91_ST_SAM9G25] = "at91sam9g25",
261 [AT91_ST_SAM9G35] = "at91sam9g35",
262 [AT91_ST_SAM9X25] = "at91sam9x25",
263 [AT91_ST_SAM9X35] = "at91sam9x35",
264};
265
266#define AT91_DBGU0 0x0ffff200 /* Most */
267#define AT91_DBGU1 0x0fffee00 /* SAM9263, CAP9, and SAM9G45 */
268
269struct at91_soc_info soc_data;
270
271/*
272 * Read the SoC ID from the CIDR register and try to match it against the
273 * values we know. If we find a good one, we return true. If not, we
274 * return false. When we find a good one, we also find the subtype
275 * and CPU family.
276 */
277static int
278at91_try_id(uint32_t dbgu_base)
279{
280 uint32_t socid;
281
282 soc_data.cidr = *(volatile uint32_t *)(AT91_BASE + dbgu_base + DBGU_C1R);
283 socid = soc_data.cidr & ~AT91_CPU_VERSION_MASK;
284
285 soc_data.type = AT91_T_NONE;
286 soc_data.subtype = AT91_ST_NONE;
287 soc_data.family = (soc_data.cidr & AT91_CPU_FAMILY_MASK) >> 20;
288 soc_data.exid = *(volatile uint32_t *)(AT91_BASE + dbgu_base + DBGU_C2R);
289
290 switch (socid) {
291 case AT91_CPU_CAP9:
292 soc_data.type = AT91_T_CAP9;
293 break;
294 case AT91_CPU_RM9200:
295 soc_data.type = AT91_T_RM9200;
296 break;
297 case AT91_CPU_SAM9XE128:
298 case AT91_CPU_SAM9XE256:
299 case AT91_CPU_SAM9XE512:
300 case AT91_CPU_SAM9260:
301 soc_data.type = AT91_T_SAM9260;
302 if (soc_data.family == AT91_FAMILY_SAM9XE)
303 soc_data.subtype = AT91_ST_SAM9XE;
304 break;
305 case AT91_CPU_SAM9261:
306 soc_data.type = AT91_T_SAM9261;
307 break;
308 case AT91_CPU_SAM9263:
309 soc_data.type = AT91_T_SAM9263;
310 break;
311 case AT91_CPU_SAM9G10:
312 soc_data.type = AT91_T_SAM9G10;
313 break;
314 case AT91_CPU_SAM9G20:
315 soc_data.type = AT91_T_SAM9G20;
316 break;
317 case AT91_CPU_SAM9G45:
318 soc_data.type = AT91_T_SAM9G45;
319 break;
320 case AT91_CPU_SAM9N12:
321 soc_data.type = AT91_T_SAM9N12;
322 break;
323 case AT91_CPU_SAM9RL64:
324 soc_data.type = AT91_T_SAM9RL;
325 break;
326 case AT91_CPU_SAM9X5:
327 soc_data.type = AT91_T_SAM9X5;
328 break;
329 default:
330 return 0;
331 }
332
333 switch (soc_data.type) {
334 case AT91_T_SAM9G45:
335 switch (soc_data.exid) {
336 case AT91_EXID_SAM9G45:
337 soc_data.subtype = AT91_ST_SAM9G45;
338 break;
339 case AT91_EXID_SAM9G46:
340 soc_data.subtype = AT91_ST_SAM9G46;
341 break;
342 case AT91_EXID_SAM9M10:
343 soc_data.subtype = AT91_ST_SAM9M10;
344 break;
345 case AT91_EXID_SAM9M11:
346 soc_data.subtype = AT91_ST_SAM9M11;
347 break;
348 }
349 break;
350 case AT91_T_SAM9X5:
351 switch (soc_data.exid) {
352 case AT91_EXID_SAM9G15:
353 soc_data.subtype = AT91_ST_SAM9G15;
354 break;
355 case AT91_EXID_SAM9G25:
356 soc_data.subtype = AT91_ST_SAM9G25;
357 break;
358 case AT91_EXID_SAM9G35:
359 soc_data.subtype = AT91_ST_SAM9G35;
360 break;
361 case AT91_EXID_SAM9X25:
362 soc_data.subtype = AT91_ST_SAM9X25;
363 break;
364 case AT91_EXID_SAM9X35:
365 soc_data.subtype = AT91_ST_SAM9X35;
366 break;
367 }
368 break;
369 default:
370 break;
371 }
372 snprintf(soc_data.name, sizeof(soc_data.name), "%s%s%s", soc_type_name[soc_data.type],
373 soc_data.subtype == AT91_ST_NONE ? "" : " subtype ",
374 soc_data.subtype == AT91_ST_NONE ? "" : soc_subtype_name[soc_data.subtype]);
375 return 1;
376}
377
378static void
379at91_soc_id(void)
380{
381 if (!at91_try_id(AT91_DBGU0))
382 at91_try_id(AT91_DBGU1);
383}
384
235void *
236initarm(struct arm_boot_params *abp)
237{
238 struct pv_addr kernel_l1pt;
239 struct pv_addr dpcpu;
240 int loop, i;
241 u_int l1pagetable;
242 vm_offset_t freemempos;

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350 }
351
352 pmap_devmap_bootstrap(l1pagetable, at91_devmap);
353 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
354 setttb(kernel_l1pt.pv_pa);
355 cpu_tlb_flushID();
356 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
357
385void *
386initarm(struct arm_boot_params *abp)
387{
388 struct pv_addr kernel_l1pt;
389 struct pv_addr dpcpu;
390 int loop, i;
391 u_int l1pagetable;
392 vm_offset_t freemempos;

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500 }
501
502 pmap_devmap_bootstrap(l1pagetable, at91_devmap);
503 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
504 setttb(kernel_l1pt.pv_pa);
505 cpu_tlb_flushID();
506 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
507
508 at91_soc_id();
509
358 /* Initialize all the clocks, so that the console can work */
359 at91_pmc_init_clock();
360
510 /* Initialize all the clocks, so that the console can work */
511 at91_pmc_init_clock();
512
361 /* Get chip id so device drivers know about differences */
362 at91_chip_id = *(uint32_t *)(AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
363
364 cninit();
365
366 memsize = board_init();
367 physmem = memsize / PAGE_SIZE;
368
369 /*
370 * Pages were allocated during the secondary bootstrap for the
371 * stacks for different CPU modes.

--- 74 unchanged lines hidden --- 		513 cninit();
514
515 memsize = board_init();
516 physmem = memsize / PAGE_SIZE;
517
518 /*
519 * Pages were allocated during the secondary bootstrap for the
520 * stacks for different CPU modes.

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