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at91_machdep.c (198872) at91_machdep.c (213496)
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include "opt_msgbuf.h"
47
48#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1994-1998 Mark Brinicombe.
3 * Copyright (c) 1994 Brini.
4 * All rights reserved.
5 *
6 * This code is derived from software written for Brini by Mark Brinicombe
7 *
8 * Redistribution and use in source and binary forms, with or without

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41 * This file needs a lot of work.
42 *
43 * Created : 17/09/94
44 */
45
46#include "opt_msgbuf.h"
47
48#include <sys/cdefs.h>
49__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 198872 2009-11-04 04:41:03Z alc $");
49__FBSDID("$FreeBSD: head/sys/arm/at91/at91_machdep.c 213496 2010-10-06 22:25:21Z cognet $");
50
51#define _ARM32_BUS_DMA_PRIVATE
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysproto.h>
55#include <sys/signalvar.h>
56#include <sys/imgact.h>
57#include <sys/kernel.h>

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85#include <machine/undefined.h>
86#include <machine/machdep.h>
87#include <machine/metadata.h>
88#include <machine/armreg.h>
89#include <machine/bus.h>
90#include <sys/reboot.h>
91
92#include <arm/at91/at91board.h>
50
51#define _ARM32_BUS_DMA_PRIVATE
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/sysproto.h>
55#include <sys/signalvar.h>
56#include <sys/imgact.h>
57#include <sys/kernel.h>

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85#include <machine/undefined.h>
86#include <machine/machdep.h>
87#include <machine/metadata.h>
88#include <machine/armreg.h>
89#include <machine/bus.h>
90#include <sys/reboot.h>
91
92#include <arm/at91/at91board.h>
93#include <arm/at91/at91var.h>
93#include <arm/at91/at91rm92reg.h>
94#include <arm/at91/at91rm92reg.h>
94#include <arm/at91/at91_piovar.h>
95#include <arm/at91/at91_pio_rm9200.h>
95#include <arm/at91/at91sam9g20reg.h>
96#include <arm/at91/at91board.h>
96
97#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
98#define KERNEL_PT_KERN 1
99#define KERNEL_PT_KERN_NUM 22
100#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
101#define KERNEL_PT_AFKERNEL_NUM 5
102
103/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */

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135struct pv_addr kernelstack;
136
137static void *boot_arg1;
138static void *boot_arg2;
139
140static struct trapframe proc0_tf;
141
142/* Static device mappings. */
97
98#define KERNEL_PT_SYS 0 /* Page table for mapping proc0 zero page */
99#define KERNEL_PT_KERN 1
100#define KERNEL_PT_KERN_NUM 22
101#define KERNEL_PT_AFKERNEL KERNEL_PT_KERN + KERNEL_PT_KERN_NUM /* L2 table for mapping after kernel */
102#define KERNEL_PT_AFKERNEL_NUM 5
103
104/* this should be evenly divisable by PAGE_SIZE / L2_TABLE_SIZE_REAL (or 4) */

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136struct pv_addr kernelstack;
137
138static void *boot_arg1;
139static void *boot_arg2;
140
141static struct trapframe proc0_tf;
142
143/* Static device mappings. */
143static const struct pmap_devmap at91rm9200_devmap[] = {
144const struct pmap_devmap at91_devmap[] = {
144 /*
145 * Map the on-board devices VA == PA so that we can access them
146 * with the MMU on or off.
147 */
148 {
149 /*
150 * This at least maps the interrupt controller, the UART
151 * and the timer. Other devices should use newbus to
152 * map their memory anyway.
153 */
154 0xdff00000,
155 0xfff00000,
145 /*
146 * Map the on-board devices VA == PA so that we can access them
147 * with the MMU on or off.
148 */
149 {
150 /*
151 * This at least maps the interrupt controller, the UART
152 * and the timer. Other devices should use newbus to
153 * map their memory anyway.
154 */
155 0xdff00000,
156 0xfff00000,
156 0x100000,
157 0x00100000,
157 VM_PROT_READ|VM_PROT_WRITE,
158 PTE_NOCACHE,
159 },
158 VM_PROT_READ|VM_PROT_WRITE,
159 PTE_NOCACHE,
160 },
160 /*
161 * We can't just map the OHCI registers VA == PA, because
162 * AT91RM92_OHCI_BASE belongs to the userland address space.
161 /* We can't just map the OHCI registers VA == PA, because
162 * AT91xx_xxx_BASE belongs to the userland address space.
163 * We could just choose a different virtual address, but a better
164 * solution would probably be to just use pmap_mapdev() to allocate
165 * KVA, as we don't need the OHCI controller before the vm
166 * initialization is done. However, the AT91 resource allocation
167 * system doesn't know how to use pmap_mapdev() yet.
163 * We could just choose a different virtual address, but a better
164 * solution would probably be to just use pmap_mapdev() to allocate
165 * KVA, as we don't need the OHCI controller before the vm
166 * initialization is done. However, the AT91 resource allocation
167 * system doesn't know how to use pmap_mapdev() yet.
168 * Care must be taken to ensure PA and VM address do not overlap
169 * between entries.
168 */
169 {
170 /*
171 * Add the ohci controller, and anything else that might be
172 * on this chip select for a VA/PA mapping.
173 */
170 */
171 {
172 /*
173 * Add the ohci controller, and anything else that might be
174 * on this chip select for a VA/PA mapping.
175 */
176 /* Internal Memory 1MB */
174 AT91RM92_OHCI_BASE,
175 AT91RM92_OHCI_PA_BASE,
177 AT91RM92_OHCI_BASE,
178 AT91RM92_OHCI_PA_BASE,
176 AT91RM92_OHCI_SIZE,
179 0x00100000,
177 VM_PROT_READ|VM_PROT_WRITE,
178 PTE_NOCACHE,
179 },
180 {
180 VM_PROT_READ|VM_PROT_WRITE,
181 PTE_NOCACHE,
182 },
183 {
181 /* CompactFlash controller. */
184 /* CompactFlash controller. Portion of EBI CS4 1MB */
182 AT91RM92_CF_BASE,
183 AT91RM92_CF_PA_BASE,
185 AT91RM92_CF_BASE,
186 AT91RM92_CF_PA_BASE,
184 AT91RM92_CF_SIZE,
187 0x00100000,
185 VM_PROT_READ|VM_PROT_WRITE,
186 PTE_NOCACHE,
187 },
188 VM_PROT_READ|VM_PROT_WRITE,
189 PTE_NOCACHE,
190 },
191 /* The next two should be good for the 9260, 9261 and 9G20 since
192 * addresses mapping is the same. */
188 {
193 {
189 0,
190 0,
191 0,
192 0,
193 0,
194 }
194 /* Internal Memory 1MB */
195 AT91SAM9G20_OHCI_BASE,
196 AT91SAM9G20_OHCI_PA_BASE,
197 0x00100000,
198 VM_PROT_READ|VM_PROT_WRITE,
199 PTE_NOCACHE,
200 },
201 {
202 /* EBI CS3 256MB */
203 AT91SAM9G20_NAND_BASE,
204 AT91SAM9G20_NAND_PA_BASE,
205 AT91SAM9G20_NAND_SIZE,
206 VM_PROT_READ|VM_PROT_WRITE,
207 PTE_NOCACHE,
208 },
209 { 0, 0, 0, 0, 0, }
195};
196
197long
198at91_ramsize(void)
199{
210};
211
212long
213at91_ramsize(void)
214{
200 uint32_t *SDRAMC = (uint32_t *)(AT91RM92_BASE + AT91RM92_SDRAMC_BASE);
215 uint32_t *SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
201 uint32_t cr, mr;
202 int banks, rows, cols, bw;
203
216 uint32_t cr, mr;
217 int banks, rows, cols, bw;
218
204 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
205 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
206 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
207 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
208 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
209 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
219 if (at91_is_rm92()) {
220 SDRAMC = (uint32_t *)(AT91_BASE + AT91RM92_SDRAMC_BASE);
221 cr = SDRAMC[AT91RM92_SDRAMC_CR / 4];
222 mr = SDRAMC[AT91RM92_SDRAMC_MR / 4];
223 banks = (cr & AT91RM92_SDRAMC_CR_NB_4) ? 2 : 1;
224 rows = ((cr & AT91RM92_SDRAMC_CR_NR_MASK) >> 2) + 11;
225 cols = (cr & AT91RM92_SDRAMC_CR_NC_MASK) + 8;
226 bw = (mr & AT91RM92_SDRAMC_MR_DBW_16) ? 1 : 2;
227 } else {
228 /* This should be good for the 9260, 9261 and 9G20 as addresses
229 * and registers are the same */
230 SDRAMC = (uint32_t *)(AT91_BASE + AT91SAM9G20_SDRAMC_BASE);
231 cr = SDRAMC[AT91SAM9G20_SDRAMC_CR / 4];
232 mr = SDRAMC[AT91SAM9G20_SDRAMC_MR / 4];
233 banks = (cr & AT91SAM9G20_SDRAMC_CR_NB_4) ? 2 : 1;
234 rows = ((cr & AT91SAM9G20_SDRAMC_CR_NR_MASK) >> 2) + 11;
235 cols = (cr & AT91SAM9G20_SDRAMC_CR_NC_MASK) + 8;
236 bw = (cr & AT91SAM9G20_SDRAMC_CR_DBW_16) ? 1 : 2;
237 }
238
210 return (1 << (cols + rows + banks + bw));
211}
212
213void *
214initarm(void *arg, void *arg2)
215{
216 struct pv_addr kernel_l1pt;
217 struct pv_addr dpcpu;

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321 MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
322
323 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
324 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
325 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
326 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
327 }
328
239 return (1 << (cols + rows + banks + bw));
240}
241
242void *
243initarm(void *arg, void *arg2)
244{
245 struct pv_addr kernel_l1pt;
246 struct pv_addr dpcpu;

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350 MSGBUF_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
351
352 for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
353 pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
354 kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
355 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
356 }
357
329 pmap_devmap_bootstrap(l1pagetable, at91rm9200_devmap);
358 pmap_devmap_bootstrap(l1pagetable, at91_devmap);
330 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
331 setttb(kernel_l1pt.pv_pa);
332 cpu_tlb_flushID();
333 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
359 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
360 setttb(kernel_l1pt.pv_pa);
361 cpu_tlb_flushID();
362 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
363
334 cninit();
364 cninit();
365
366 /* Get chip id so device drivers know about differences */
367 at91_chip_id = *(volatile uint32_t *)
368 (AT91_BASE + AT91_DBGU_BASE + DBGU_C1R);
369
335 memsize = board_init();
370 memsize = board_init();
371
372 printf("memsize = %d\n", memsize);
336 physmem = memsize / PAGE_SIZE;
337
338 /*
339 * Pages were allocated during the secondary bootstrap for the
340 * stacks for different CPU modes.
341 * We must now set the r13 registers in the different CPU modes to
342 * point to these stacks.
343 * Since the ARM stacks use STMFD etc. we must set r13 to the top end

--- 73 unchanged lines hidden --- 		373 physmem = memsize / PAGE_SIZE;
374
375 /*
376 * Pages were allocated during the secondary bootstrap for the
377 * stacks for different CPU modes.
378 * We must now set the r13 registers in the different CPU modes to
379 * point to these stacks.
380 * Since the ARM stacks use STMFD etc. we must set r13 to the top end

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