1/* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */
2
3/*-
4 * Copyright (c) 2004 Olivier Houchard
5 * Copyright (c) 1994-1998 Mark Brinicombe.
6 * Copyright (c) 1994 Brini.
7 * All rights reserved.
8 *
9 * This code is derived from software written for Brini by Mark Brinicombe
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Mark Brinicombe
22 * for the NetBSD Project.
23 * 4. The name of the company nor the name of the author may be used to
24 * endorse or promote products derived from this software without specific
25 * prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * Created : 17/09/94
42 * Updated : 18/04/01 updated for new wscons
43 */
44
45#include "opt_compat.h"
46#include "opt_ddb.h"
47#include "opt_platform.h"
48#include "opt_sched.h"
49#include "opt_timer.h"
50
51#include <sys/cdefs.h>
| 1/* $NetBSD: arm32_machdep.c,v 1.44 2004/03/24 15:34:47 atatat Exp $ */
2
3/*-
4 * Copyright (c) 2004 Olivier Houchard
5 * Copyright (c) 1994-1998 Mark Brinicombe.
6 * Copyright (c) 1994 Brini.
7 * All rights reserved.
8 *
9 * This code is derived from software written for Brini by Mark Brinicombe
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by Mark Brinicombe
22 * for the NetBSD Project.
23 * 4. The name of the company nor the name of the author may be used to
24 * endorse or promote products derived from this software without specific
25 * prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
30 * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * SUCH DAMAGE.
38 *
39 * Machine dependant functions for kernel setup
40 *
41 * Created : 17/09/94
42 * Updated : 18/04/01 updated for new wscons
43 */
44
45#include "opt_compat.h"
46#include "opt_ddb.h"
47#include "opt_platform.h"
48#include "opt_sched.h"
49#include "opt_timer.h"
50
51#include <sys/cdefs.h>
|
52__FBSDID("$FreeBSD: head/sys/arm/arm/machdep.c 283033 2015-05-17 17:03:37Z ian $");
| 52__FBSDID("$FreeBSD: head/sys/arm/arm/machdep.c 283366 2015-05-24 12:20:11Z andrew $");
|
53
54#include <sys/param.h>
55#include <sys/proc.h>
56#include <sys/systm.h>
57#include <sys/bio.h>
58#include <sys/buf.h>
59#include <sys/bus.h>
60#include <sys/cons.h>
61#include <sys/cpu.h>
62#include <sys/exec.h>
63#include <sys/imgact.h>
64#include <sys/kdb.h>
65#include <sys/kernel.h>
66#include <sys/ktr.h>
67#include <sys/linker.h>
68#include <sys/lock.h>
69#include <sys/malloc.h>
70#include <sys/msgbuf.h>
71#include <sys/mutex.h>
72#include <sys/pcpu.h>
73#include <sys/ptrace.h>
74#include <sys/rwlock.h>
75#include <sys/sched.h>
76#include <sys/signalvar.h>
77#include <sys/syscallsubr.h>
78#include <sys/sysctl.h>
79#include <sys/sysent.h>
80#include <sys/sysproto.h>
81#include <sys/uio.h>
82
83#include <vm/vm.h>
84#include <vm/pmap.h>
85#include <vm/vm_map.h>
86#include <vm/vm_object.h>
87#include <vm/vm_page.h>
88#include <vm/vm_pager.h>
89
90#include <machine/acle-compat.h>
91#include <machine/armreg.h>
92#include <machine/atags.h>
93#include <machine/cpu.h>
94#include <machine/cpuinfo.h>
95#include <machine/devmap.h>
96#include <machine/frame.h>
97#include <machine/intr.h>
98#include <machine/machdep.h>
99#include <machine/md_var.h>
100#include <machine/metadata.h>
101#include <machine/pcb.h>
102#include <machine/physmem.h>
103#include <machine/platform.h>
104#include <machine/reg.h>
105#include <machine/trap.h>
106#include <machine/undefined.h>
107#include <machine/vfp.h>
108#include <machine/vmparam.h>
109#include <machine/sysarch.h>
110
111#ifdef FDT
112#include <dev/fdt/fdt_common.h>
113#include <dev/ofw/openfirm.h>
114#endif
115
116#ifdef DDB
117#include <ddb/ddb.h>
118
119#if __ARM_ARCH >= 6
120#include <machine/cpu-v6.h>
121
122DB_SHOW_COMMAND(cp15, db_show_cp15)
123{
124 u_int reg;
125
126 reg = cp15_midr_get();
127 db_printf("Cpu ID: 0x%08x\n", reg);
128 reg = cp15_ctr_get();
129 db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
130
131 reg = cp15_sctlr_get();
132 db_printf("Ctrl: 0x%08x\n",reg);
133 reg = cp15_actlr_get();
134 db_printf("Aux Ctrl: 0x%08x\n",reg);
135
136 reg = cp15_id_pfr0_get();
137 db_printf("Processor Feat 0: 0x%08x\n", reg);
138 reg = cp15_id_pfr1_get();
139 db_printf("Processor Feat 1: 0x%08x\n", reg);
140 reg = cp15_id_dfr0_get();
141 db_printf("Debug Feat 0: 0x%08x\n", reg);
142 reg = cp15_id_afr0_get();
143 db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
144 reg = cp15_id_mmfr0_get();
145 db_printf("Memory Model Feat 0: 0x%08x\n", reg);
146 reg = cp15_id_mmfr1_get();
147 db_printf("Memory Model Feat 1: 0x%08x\n", reg);
148 reg = cp15_id_mmfr2_get();
149 db_printf("Memory Model Feat 2: 0x%08x\n", reg);
150 reg = cp15_id_mmfr3_get();
151 db_printf("Memory Model Feat 3: 0x%08x\n", reg);
152 reg = cp15_ttbr_get();
153 db_printf("TTB0: 0x%08x\n", reg);
154}
155
156DB_SHOW_COMMAND(vtop, db_show_vtop)
157{
158 u_int reg;
159
160 if (have_addr) {
161 cp15_ats1cpr_set(addr);
162 reg = cp15_par_get();
163 db_printf("Physical address reg: 0x%08x\n",reg);
164 } else
165 db_printf("show vtop <virt_addr>\n");
166}
167#endif /* __ARM_ARCH >= 6 */
168#endif /* DDB */
169
170#ifdef DEBUG
171#define debugf(fmt, args...) printf(fmt, ##args)
172#else
173#define debugf(fmt, args...)
174#endif
175
176struct pcpu __pcpu[MAXCPU];
177struct pcpu *pcpup = &__pcpu[0];
178
179static struct trapframe proc0_tf;
180uint32_t cpu_reset_address = 0;
181int cold = 1;
182vm_offset_t vector_page;
183
184int (*_arm_memcpy)(void *, void *, int, int) = NULL;
185int (*_arm_bzero)(void *, int, int) = NULL;
186int _min_memcpy_size = 0;
187int _min_bzero_size = 0;
188
189extern int *end;
190
191#ifdef FDT
192vm_paddr_t pmap_pa;
193
194#ifdef ARM_NEW_PMAP
195vm_offset_t systempage;
196vm_offset_t irqstack;
197vm_offset_t undstack;
198vm_offset_t abtstack;
199#else
200/*
201 * This is the number of L2 page tables required for covering max
202 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf,
203 * stacks etc.), uprounded to be divisible by 4.
204 */
205#define KERNEL_PT_MAX 78
206
207static struct pv_addr kernel_pt_table[KERNEL_PT_MAX];
208
209struct pv_addr systempage;
210static struct pv_addr msgbufpv;
211struct pv_addr irqstack;
212struct pv_addr undstack;
213struct pv_addr abtstack;
214static struct pv_addr kernelstack;
215#endif
216#endif
217
218#if defined(LINUX_BOOT_ABI)
219#define LBABI_MAX_BANKS 10
220
221uint32_t board_id;
222struct arm_lbabi_tag *atag_list;
223char linux_command_line[LBABI_MAX_COMMAND_LINE + 1];
224char atags[LBABI_MAX_COMMAND_LINE * 2];
225uint32_t memstart[LBABI_MAX_BANKS];
226uint32_t memsize[LBABI_MAX_BANKS];
227uint32_t membanks;
228#endif
229
230static uint32_t board_revision;
231/* hex representation of uint64_t */
232static char board_serial[32];
233
234SYSCTL_NODE(_hw, OID_AUTO, board, CTLFLAG_RD, 0, "Board attributes");
235SYSCTL_UINT(_hw_board, OID_AUTO, revision, CTLFLAG_RD,
236 &board_revision, 0, "Board revision");
237SYSCTL_STRING(_hw_board, OID_AUTO, serial, CTLFLAG_RD,
238 board_serial, 0, "Board serial");
239
240int vfp_exists;
241SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
242 &vfp_exists, 0, "Floating point support enabled");
243
244void
245board_set_serial(uint64_t serial)
246{
247
| 53
54#include <sys/param.h>
55#include <sys/proc.h>
56#include <sys/systm.h>
57#include <sys/bio.h>
58#include <sys/buf.h>
59#include <sys/bus.h>
60#include <sys/cons.h>
61#include <sys/cpu.h>
62#include <sys/exec.h>
63#include <sys/imgact.h>
64#include <sys/kdb.h>
65#include <sys/kernel.h>
66#include <sys/ktr.h>
67#include <sys/linker.h>
68#include <sys/lock.h>
69#include <sys/malloc.h>
70#include <sys/msgbuf.h>
71#include <sys/mutex.h>
72#include <sys/pcpu.h>
73#include <sys/ptrace.h>
74#include <sys/rwlock.h>
75#include <sys/sched.h>
76#include <sys/signalvar.h>
77#include <sys/syscallsubr.h>
78#include <sys/sysctl.h>
79#include <sys/sysent.h>
80#include <sys/sysproto.h>
81#include <sys/uio.h>
82
83#include <vm/vm.h>
84#include <vm/pmap.h>
85#include <vm/vm_map.h>
86#include <vm/vm_object.h>
87#include <vm/vm_page.h>
88#include <vm/vm_pager.h>
89
90#include <machine/acle-compat.h>
91#include <machine/armreg.h>
92#include <machine/atags.h>
93#include <machine/cpu.h>
94#include <machine/cpuinfo.h>
95#include <machine/devmap.h>
96#include <machine/frame.h>
97#include <machine/intr.h>
98#include <machine/machdep.h>
99#include <machine/md_var.h>
100#include <machine/metadata.h>
101#include <machine/pcb.h>
102#include <machine/physmem.h>
103#include <machine/platform.h>
104#include <machine/reg.h>
105#include <machine/trap.h>
106#include <machine/undefined.h>
107#include <machine/vfp.h>
108#include <machine/vmparam.h>
109#include <machine/sysarch.h>
110
111#ifdef FDT
112#include <dev/fdt/fdt_common.h>
113#include <dev/ofw/openfirm.h>
114#endif
115
116#ifdef DDB
117#include <ddb/ddb.h>
118
119#if __ARM_ARCH >= 6
120#include <machine/cpu-v6.h>
121
122DB_SHOW_COMMAND(cp15, db_show_cp15)
123{
124 u_int reg;
125
126 reg = cp15_midr_get();
127 db_printf("Cpu ID: 0x%08x\n", reg);
128 reg = cp15_ctr_get();
129 db_printf("Current Cache Lvl ID: 0x%08x\n",reg);
130
131 reg = cp15_sctlr_get();
132 db_printf("Ctrl: 0x%08x\n",reg);
133 reg = cp15_actlr_get();
134 db_printf("Aux Ctrl: 0x%08x\n",reg);
135
136 reg = cp15_id_pfr0_get();
137 db_printf("Processor Feat 0: 0x%08x\n", reg);
138 reg = cp15_id_pfr1_get();
139 db_printf("Processor Feat 1: 0x%08x\n", reg);
140 reg = cp15_id_dfr0_get();
141 db_printf("Debug Feat 0: 0x%08x\n", reg);
142 reg = cp15_id_afr0_get();
143 db_printf("Auxiliary Feat 0: 0x%08x\n", reg);
144 reg = cp15_id_mmfr0_get();
145 db_printf("Memory Model Feat 0: 0x%08x\n", reg);
146 reg = cp15_id_mmfr1_get();
147 db_printf("Memory Model Feat 1: 0x%08x\n", reg);
148 reg = cp15_id_mmfr2_get();
149 db_printf("Memory Model Feat 2: 0x%08x\n", reg);
150 reg = cp15_id_mmfr3_get();
151 db_printf("Memory Model Feat 3: 0x%08x\n", reg);
152 reg = cp15_ttbr_get();
153 db_printf("TTB0: 0x%08x\n", reg);
154}
155
156DB_SHOW_COMMAND(vtop, db_show_vtop)
157{
158 u_int reg;
159
160 if (have_addr) {
161 cp15_ats1cpr_set(addr);
162 reg = cp15_par_get();
163 db_printf("Physical address reg: 0x%08x\n",reg);
164 } else
165 db_printf("show vtop <virt_addr>\n");
166}
167#endif /* __ARM_ARCH >= 6 */
168#endif /* DDB */
169
170#ifdef DEBUG
171#define debugf(fmt, args...) printf(fmt, ##args)
172#else
173#define debugf(fmt, args...)
174#endif
175
176struct pcpu __pcpu[MAXCPU];
177struct pcpu *pcpup = &__pcpu[0];
178
179static struct trapframe proc0_tf;
180uint32_t cpu_reset_address = 0;
181int cold = 1;
182vm_offset_t vector_page;
183
184int (*_arm_memcpy)(void *, void *, int, int) = NULL;
185int (*_arm_bzero)(void *, int, int) = NULL;
186int _min_memcpy_size = 0;
187int _min_bzero_size = 0;
188
189extern int *end;
190
191#ifdef FDT
192vm_paddr_t pmap_pa;
193
194#ifdef ARM_NEW_PMAP
195vm_offset_t systempage;
196vm_offset_t irqstack;
197vm_offset_t undstack;
198vm_offset_t abtstack;
199#else
200/*
201 * This is the number of L2 page tables required for covering max
202 * (hypothetical) memsize of 4GB and all kernel mappings (vectors, msgbuf,
203 * stacks etc.), uprounded to be divisible by 4.
204 */
205#define KERNEL_PT_MAX 78
206
207static struct pv_addr kernel_pt_table[KERNEL_PT_MAX];
208
209struct pv_addr systempage;
210static struct pv_addr msgbufpv;
211struct pv_addr irqstack;
212struct pv_addr undstack;
213struct pv_addr abtstack;
214static struct pv_addr kernelstack;
215#endif
216#endif
217
218#if defined(LINUX_BOOT_ABI)
219#define LBABI_MAX_BANKS 10
220
221uint32_t board_id;
222struct arm_lbabi_tag *atag_list;
223char linux_command_line[LBABI_MAX_COMMAND_LINE + 1];
224char atags[LBABI_MAX_COMMAND_LINE * 2];
225uint32_t memstart[LBABI_MAX_BANKS];
226uint32_t memsize[LBABI_MAX_BANKS];
227uint32_t membanks;
228#endif
229
230static uint32_t board_revision;
231/* hex representation of uint64_t */
232static char board_serial[32];
233
234SYSCTL_NODE(_hw, OID_AUTO, board, CTLFLAG_RD, 0, "Board attributes");
235SYSCTL_UINT(_hw_board, OID_AUTO, revision, CTLFLAG_RD,
236 &board_revision, 0, "Board revision");
237SYSCTL_STRING(_hw_board, OID_AUTO, serial, CTLFLAG_RD,
238 board_serial, 0, "Board serial");
239
240int vfp_exists;
241SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
242 &vfp_exists, 0, "Floating point support enabled");
243
244void
245board_set_serial(uint64_t serial)
246{
247
|
248 snprintf(board_serial, sizeof(board_serial)-1,
| 248 snprintf(board_serial, sizeof(board_serial)-1,
|
249 "%016jx", serial);
250}
251
252void
253board_set_revision(uint32_t revision)
254{
255
256 board_revision = revision;
257}
258
259void
260sendsig(catcher, ksi, mask)
261 sig_t catcher;
262 ksiginfo_t *ksi;
263 sigset_t *mask;
264{
265 struct thread *td;
266 struct proc *p;
267 struct trapframe *tf;
268 struct sigframe *fp, frame;
269 struct sigacts *psp;
270 int onstack;
271 int sig;
272 int code;
273
274 td = curthread;
275 p = td->td_proc;
276 PROC_LOCK_ASSERT(p, MA_OWNED);
277 sig = ksi->ksi_signo;
278 code = ksi->ksi_code;
279 psp = p->p_sigacts;
280 mtx_assert(&psp->ps_mtx, MA_OWNED);
281 tf = td->td_frame;
282 onstack = sigonstack(tf->tf_usr_sp);
283
284 CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm,
285 catcher, sig);
286
287 /* Allocate and validate space for the signal handler context. */
288 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) &&
289 SIGISMEMBER(psp->ps_sigonstack, sig)) {
290 fp = (struct sigframe *)(td->td_sigstk.ss_sp +
291 td->td_sigstk.ss_size);
292#if defined(COMPAT_43)
293 td->td_sigstk.ss_flags |= SS_ONSTACK;
294#endif
295 } else
296 fp = (struct sigframe *)td->td_frame->tf_usr_sp;
297
298 /* make room on the stack */
299 fp--;
| 249 "%016jx", serial);
250}
251
252void
253board_set_revision(uint32_t revision)
254{
255
256 board_revision = revision;
257}
258
259void
260sendsig(catcher, ksi, mask)
261 sig_t catcher;
262 ksiginfo_t *ksi;
263 sigset_t *mask;
264{
265 struct thread *td;
266 struct proc *p;
267 struct trapframe *tf;
268 struct sigframe *fp, frame;
269 struct sigacts *psp;
270 int onstack;
271 int sig;
272 int code;
273
274 td = curthread;
275 p = td->td_proc;
276 PROC_LOCK_ASSERT(p, MA_OWNED);
277 sig = ksi->ksi_signo;
278 code = ksi->ksi_code;
279 psp = p->p_sigacts;
280 mtx_assert(&psp->ps_mtx, MA_OWNED);
281 tf = td->td_frame;
282 onstack = sigonstack(tf->tf_usr_sp);
283
284 CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm,
285 catcher, sig);
286
287 /* Allocate and validate space for the signal handler context. */
288 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !(onstack) &&
289 SIGISMEMBER(psp->ps_sigonstack, sig)) {
290 fp = (struct sigframe *)(td->td_sigstk.ss_sp +
291 td->td_sigstk.ss_size);
292#if defined(COMPAT_43)
293 td->td_sigstk.ss_flags |= SS_ONSTACK;
294#endif
295 } else
296 fp = (struct sigframe *)td->td_frame->tf_usr_sp;
297
298 /* make room on the stack */
299 fp--;
|
300
| 300
|
301 /* make the stack aligned */
302 fp = (struct sigframe *)STACKALIGN(fp);
303 /* Populate the siginfo frame. */
304 get_mcontext(td, &frame.sf_uc.uc_mcontext, 0);
305 frame.sf_si = ksi->ksi_info;
306 frame.sf_uc.uc_sigmask = *mask;
307 frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK )
308 ? ((onstack) ? SS_ONSTACK : 0) : SS_DISABLE;
309 frame.sf_uc.uc_stack = td->td_sigstk;
310 mtx_unlock(&psp->ps_mtx);
311 PROC_UNLOCK(td->td_proc);
312
313 /* Copy the sigframe out to the user's stack. */
314 if (copyout(&frame, fp, sizeof(*fp)) != 0) {
315 /* Process has trashed its stack. Kill it. */
316 CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp);
317 PROC_LOCK(p);
318 sigexit(td, SIGILL);
319 }
320
321 /* Translate the signal if appropriate. */
322 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
323 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
324
325 /*
326 * Build context to run handler in. We invoke the handler
327 * directly, only returning via the trampoline. Note the
328 * trampoline version numbers are coordinated with machine-
329 * dependent code in libc.
330 */
| 301 /* make the stack aligned */
302 fp = (struct sigframe *)STACKALIGN(fp);
303 /* Populate the siginfo frame. */
304 get_mcontext(td, &frame.sf_uc.uc_mcontext, 0);
305 frame.sf_si = ksi->ksi_info;
306 frame.sf_uc.uc_sigmask = *mask;
307 frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK )
308 ? ((onstack) ? SS_ONSTACK : 0) : SS_DISABLE;
309 frame.sf_uc.uc_stack = td->td_sigstk;
310 mtx_unlock(&psp->ps_mtx);
311 PROC_UNLOCK(td->td_proc);
312
313 /* Copy the sigframe out to the user's stack. */
314 if (copyout(&frame, fp, sizeof(*fp)) != 0) {
315 /* Process has trashed its stack. Kill it. */
316 CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp);
317 PROC_LOCK(p);
318 sigexit(td, SIGILL);
319 }
320
321 /* Translate the signal if appropriate. */
322 if (p->p_sysent->sv_sigtbl && sig <= p->p_sysent->sv_sigsize)
323 sig = p->p_sysent->sv_sigtbl[_SIG_IDX(sig)];
324
325 /*
326 * Build context to run handler in. We invoke the handler
327 * directly, only returning via the trampoline. Note the
328 * trampoline version numbers are coordinated with machine-
329 * dependent code in libc.
330 */
|
331
| 331
|
332 tf->tf_r0 = sig;
333 tf->tf_r1 = (register_t)&fp->sf_si;
334 tf->tf_r2 = (register_t)&fp->sf_uc;
335
336 /* the trampoline uses r5 as the uc address */
337 tf->tf_r5 = (register_t)&fp->sf_uc;
338 tf->tf_pc = (register_t)catcher;
339 tf->tf_usr_sp = (register_t)fp;
340 tf->tf_usr_lr = (register_t)(PS_STRINGS - *(p->p_sysent->sv_szsigcode));
341 /* Set the mode to enter in the signal handler */
342#if __ARM_ARCH >= 7
343 if ((register_t)catcher & 1)
344 tf->tf_spsr |= PSR_T;
345 else
346 tf->tf_spsr &= ~PSR_T;
347#endif
348
349 CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr,
350 tf->tf_usr_sp);
351
352 PROC_LOCK(p);
353 mtx_lock(&psp->ps_mtx);
354}
355
356struct kva_md_info kmi;
357
358/*
359 * arm32_vector_init:
360 *
361 * Initialize the vector page, and select whether or not to
362 * relocate the vectors.
363 *
364 * NOTE: We expect the vector page to be mapped at its expected
365 * destination.
366 */
367
368extern unsigned int page0[], page0_data[];
369void
370arm_vector_init(vm_offset_t va, int which)
371{
372 unsigned int *vectors = (int *) va;
373 unsigned int *vectors_data = vectors + (page0_data - page0);
374 int vec;
375
376 /*
377 * Loop through the vectors we're taking over, and copy the
378 * vector's insn and data word.
379 */
380 for (vec = 0; vec < ARM_NVEC; vec++) {
381 if ((which & (1 << vec)) == 0) {
382 /* Don't want to take over this vector. */
383 continue;
384 }
385 vectors[vec] = page0[vec];
386 vectors_data[vec] = page0_data[vec];
387 }
388
389 /* Now sync the vectors. */
390 cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int));
391
392 vector_page = va;
393
394 if (va == ARM_VECTORS_HIGH) {
395 /*
396 * Assume the MD caller knows what it's doing here, and
397 * really does want the vector page relocated.
398 *
399 * Note: This has to be done here (and not just in
400 * cpu_setup()) because the vector page needs to be
401 * accessible *before* cpu_startup() is called.
402 * Think ddb(9) ...
403 *
404 * NOTE: If the CPU control register is not readable,
405 * this will totally fail! We'll just assume that
406 * any system that has high vector support has a
407 * readable CPU control register, for now. If we
408 * ever encounter one that does not, we'll have to
409 * rethink this.
410 */
411 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC);
412 }
413}
414
415static void
416cpu_startup(void *dummy)
417{
418 struct pcb *pcb = thread0.td_pcb;
419 const unsigned int mbyte = 1024 * 1024;
420#ifdef ARM_TP_ADDRESS
421#ifndef ARM_CACHE_LOCK_ENABLE
422 vm_page_t m;
423#endif
424#endif
425
426 identify_arm_cpu();
427
428 vm_ksubmap_init(&kmi);
429
430 /*
431 * Display the RAM layout.
432 */
| 332 tf->tf_r0 = sig;
333 tf->tf_r1 = (register_t)&fp->sf_si;
334 tf->tf_r2 = (register_t)&fp->sf_uc;
335
336 /* the trampoline uses r5 as the uc address */
337 tf->tf_r5 = (register_t)&fp->sf_uc;
338 tf->tf_pc = (register_t)catcher;
339 tf->tf_usr_sp = (register_t)fp;
340 tf->tf_usr_lr = (register_t)(PS_STRINGS - *(p->p_sysent->sv_szsigcode));
341 /* Set the mode to enter in the signal handler */
342#if __ARM_ARCH >= 7
343 if ((register_t)catcher & 1)
344 tf->tf_spsr |= PSR_T;
345 else
346 tf->tf_spsr &= ~PSR_T;
347#endif
348
349 CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_usr_lr,
350 tf->tf_usr_sp);
351
352 PROC_LOCK(p);
353 mtx_lock(&psp->ps_mtx);
354}
355
356struct kva_md_info kmi;
357
358/*
359 * arm32_vector_init:
360 *
361 * Initialize the vector page, and select whether or not to
362 * relocate the vectors.
363 *
364 * NOTE: We expect the vector page to be mapped at its expected
365 * destination.
366 */
367
368extern unsigned int page0[], page0_data[];
369void
370arm_vector_init(vm_offset_t va, int which)
371{
372 unsigned int *vectors = (int *) va;
373 unsigned int *vectors_data = vectors + (page0_data - page0);
374 int vec;
375
376 /*
377 * Loop through the vectors we're taking over, and copy the
378 * vector's insn and data word.
379 */
380 for (vec = 0; vec < ARM_NVEC; vec++) {
381 if ((which & (1 << vec)) == 0) {
382 /* Don't want to take over this vector. */
383 continue;
384 }
385 vectors[vec] = page0[vec];
386 vectors_data[vec] = page0_data[vec];
387 }
388
389 /* Now sync the vectors. */
390 cpu_icache_sync_range(va, (ARM_NVEC * 2) * sizeof(u_int));
391
392 vector_page = va;
393
394 if (va == ARM_VECTORS_HIGH) {
395 /*
396 * Assume the MD caller knows what it's doing here, and
397 * really does want the vector page relocated.
398 *
399 * Note: This has to be done here (and not just in
400 * cpu_setup()) because the vector page needs to be
401 * accessible *before* cpu_startup() is called.
402 * Think ddb(9) ...
403 *
404 * NOTE: If the CPU control register is not readable,
405 * this will totally fail! We'll just assume that
406 * any system that has high vector support has a
407 * readable CPU control register, for now. If we
408 * ever encounter one that does not, we'll have to
409 * rethink this.
410 */
411 cpu_control(CPU_CONTROL_VECRELOC, CPU_CONTROL_VECRELOC);
412 }
413}
414
415static void
416cpu_startup(void *dummy)
417{
418 struct pcb *pcb = thread0.td_pcb;
419 const unsigned int mbyte = 1024 * 1024;
420#ifdef ARM_TP_ADDRESS
421#ifndef ARM_CACHE_LOCK_ENABLE
422 vm_page_t m;
423#endif
424#endif
425
426 identify_arm_cpu();
427
428 vm_ksubmap_init(&kmi);
429
430 /*
431 * Display the RAM layout.
432 */
|
433 printf("real memory = %ju (%ju MB)\n",
| 433 printf("real memory = %ju (%ju MB)\n",
|
434 (uintmax_t)arm32_ptob(realmem),
435 (uintmax_t)arm32_ptob(realmem) / mbyte);
436 printf("avail memory = %ju (%ju MB)\n",
437 (uintmax_t)arm32_ptob(vm_cnt.v_free_count),
438 (uintmax_t)arm32_ptob(vm_cnt.v_free_count) / mbyte);
439 if (bootverbose) {
440 arm_physmem_print_tables();
441 arm_devmap_print_table();
442 }
443
444 bufinit();
445 vm_pager_bufferinit();
446 pcb->pcb_regs.sf_sp = (u_int)thread0.td_kstack +
447 USPACE_SVC_STACK_TOP;
448 pmap_set_pcb_pagedir(pmap_kernel(), pcb);
449#ifndef ARM_NEW_PMAP
450 vector_page_setprot(VM_PROT_READ);
451 pmap_postinit();
452#endif
453#ifdef ARM_TP_ADDRESS
454#ifdef ARM_CACHE_LOCK_ENABLE
455 pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS);
456 arm_lock_cache_line(ARM_TP_ADDRESS);
457#else
458 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO);
459 pmap_kenter_user(ARM_TP_ADDRESS, VM_PAGE_TO_PHYS(m));
460#endif
461 *(uint32_t *)ARM_RAS_START = 0;
462 *(uint32_t *)ARM_RAS_END = 0xffffffff;
463#endif
464}
465
466SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
467
468/*
469 * Flush the D-cache for non-DMA I/O so that the I-cache can
470 * be made coherent later.
471 */
472void
473cpu_flush_dcache(void *ptr, size_t len)
474{
475
476 cpu_dcache_wb_range((uintptr_t)ptr, len);
477#ifdef ARM_L2_PIPT
478 cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
479#else
480 cpu_l2cache_wb_range((uintptr_t)ptr, len);
481#endif
482}
483
484/* Get current clock frequency for the given cpu id. */
485int
486cpu_est_clockrate(int cpu_id, uint64_t *rate)
487{
488
489 return (ENXIO);
490}
491
492void
493cpu_idle(int busy)
494{
| 434 (uintmax_t)arm32_ptob(realmem),
435 (uintmax_t)arm32_ptob(realmem) / mbyte);
436 printf("avail memory = %ju (%ju MB)\n",
437 (uintmax_t)arm32_ptob(vm_cnt.v_free_count),
438 (uintmax_t)arm32_ptob(vm_cnt.v_free_count) / mbyte);
439 if (bootverbose) {
440 arm_physmem_print_tables();
441 arm_devmap_print_table();
442 }
443
444 bufinit();
445 vm_pager_bufferinit();
446 pcb->pcb_regs.sf_sp = (u_int)thread0.td_kstack +
447 USPACE_SVC_STACK_TOP;
448 pmap_set_pcb_pagedir(pmap_kernel(), pcb);
449#ifndef ARM_NEW_PMAP
450 vector_page_setprot(VM_PROT_READ);
451 pmap_postinit();
452#endif
453#ifdef ARM_TP_ADDRESS
454#ifdef ARM_CACHE_LOCK_ENABLE
455 pmap_kenter_user(ARM_TP_ADDRESS, ARM_TP_ADDRESS);
456 arm_lock_cache_line(ARM_TP_ADDRESS);
457#else
458 m = vm_page_alloc(NULL, 0, VM_ALLOC_NOOBJ | VM_ALLOC_ZERO);
459 pmap_kenter_user(ARM_TP_ADDRESS, VM_PAGE_TO_PHYS(m));
460#endif
461 *(uint32_t *)ARM_RAS_START = 0;
462 *(uint32_t *)ARM_RAS_END = 0xffffffff;
463#endif
464}
465
466SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
467
468/*
469 * Flush the D-cache for non-DMA I/O so that the I-cache can
470 * be made coherent later.
471 */
472void
473cpu_flush_dcache(void *ptr, size_t len)
474{
475
476 cpu_dcache_wb_range((uintptr_t)ptr, len);
477#ifdef ARM_L2_PIPT
478 cpu_l2cache_wb_range((uintptr_t)vtophys(ptr), len);
479#else
480 cpu_l2cache_wb_range((uintptr_t)ptr, len);
481#endif
482}
483
484/* Get current clock frequency for the given cpu id. */
485int
486cpu_est_clockrate(int cpu_id, uint64_t *rate)
487{
488
489 return (ENXIO);
490}
491
492void
493cpu_idle(int busy)
494{
|
495
| 495
|
496 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", busy, curcpu);
497 spinlock_enter();
498#ifndef NO_EVENTTIMERS
499 if (!busy)
500 cpu_idleclock();
501#endif
502 if (!sched_runnable())
503 cpu_sleep(0);
504#ifndef NO_EVENTTIMERS
505 if (!busy)
506 cpu_activeclock();
507#endif
508 spinlock_exit();
509 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", busy, curcpu);
510}
511
512int
513cpu_idle_wakeup(int cpu)
514{
515
516 return (0);
517}
518
519/*
520 * Most ARM platforms don't need to do anything special to init their clocks
521 * (they get intialized during normal device attachment), and by not defining a
522 * cpu_initclocks() function they get this generic one. Any platform that needs
523 * to do something special can just provide their own implementation, which will
524 * override this one due to the weak linkage.
525 */
526void
527arm_generic_initclocks(void)
528{
529
530#ifndef NO_EVENTTIMERS
531#ifdef SMP
532 if (PCPU_GET(cpuid) == 0)
533 cpu_initclocks_bsp();
534 else
535 cpu_initclocks_ap();
536#else
537 cpu_initclocks_bsp();
538#endif
539#endif
540}
541__weak_reference(arm_generic_initclocks, cpu_initclocks);
542
543int
544fill_regs(struct thread *td, struct reg *regs)
545{
546 struct trapframe *tf = td->td_frame;
547 bcopy(&tf->tf_r0, regs->r, sizeof(regs->r));
548 regs->r_sp = tf->tf_usr_sp;
549 regs->r_lr = tf->tf_usr_lr;
550 regs->r_pc = tf->tf_pc;
551 regs->r_cpsr = tf->tf_spsr;
552 return (0);
553}
554int
555fill_fpregs(struct thread *td, struct fpreg *regs)
556{
557 bzero(regs, sizeof(*regs));
558 return (0);
559}
560
561int
562set_regs(struct thread *td, struct reg *regs)
563{
564 struct trapframe *tf = td->td_frame;
| 496 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d", busy, curcpu);
497 spinlock_enter();
498#ifndef NO_EVENTTIMERS
499 if (!busy)
500 cpu_idleclock();
501#endif
502 if (!sched_runnable())
503 cpu_sleep(0);
504#ifndef NO_EVENTTIMERS
505 if (!busy)
506 cpu_activeclock();
507#endif
508 spinlock_exit();
509 CTR2(KTR_SPARE2, "cpu_idle(%d) at %d done", busy, curcpu);
510}
511
512int
513cpu_idle_wakeup(int cpu)
514{
515
516 return (0);
517}
518
519/*
520 * Most ARM platforms don't need to do anything special to init their clocks
521 * (they get intialized during normal device attachment), and by not defining a
522 * cpu_initclocks() function they get this generic one. Any platform that needs
523 * to do something special can just provide their own implementation, which will
524 * override this one due to the weak linkage.
525 */
526void
527arm_generic_initclocks(void)
528{
529
530#ifndef NO_EVENTTIMERS
531#ifdef SMP
532 if (PCPU_GET(cpuid) == 0)
533 cpu_initclocks_bsp();
534 else
535 cpu_initclocks_ap();
536#else
537 cpu_initclocks_bsp();
538#endif
539#endif
540}
541__weak_reference(arm_generic_initclocks, cpu_initclocks);
542
543int
544fill_regs(struct thread *td, struct reg *regs)
545{
546 struct trapframe *tf = td->td_frame;
547 bcopy(&tf->tf_r0, regs->r, sizeof(regs->r));
548 regs->r_sp = tf->tf_usr_sp;
549 regs->r_lr = tf->tf_usr_lr;
550 regs->r_pc = tf->tf_pc;
551 regs->r_cpsr = tf->tf_spsr;
552 return (0);
553}
554int
555fill_fpregs(struct thread *td, struct fpreg *regs)
556{
557 bzero(regs, sizeof(*regs));
558 return (0);
559}
560
561int
562set_regs(struct thread *td, struct reg *regs)
563{
564 struct trapframe *tf = td->td_frame;
|
565
| 565
|
566 bcopy(regs->r, &tf->tf_r0, sizeof(regs->r));
567 tf->tf_usr_sp = regs->r_sp;
568 tf->tf_usr_lr = regs->r_lr;
569 tf->tf_pc = regs->r_pc;
570 tf->tf_spsr &= ~PSR_FLAGS;
571 tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS;
| 566 bcopy(regs->r, &tf->tf_r0, sizeof(regs->r));
567 tf->tf_usr_sp = regs->r_sp;
568 tf->tf_usr_lr = regs->r_lr;
569 tf->tf_pc = regs->r_pc;
570 tf->tf_spsr &= ~PSR_FLAGS;
571 tf->tf_spsr |= regs->r_cpsr & PSR_FLAGS;
|
572 return (0);
| 572 return (0);
|
573}
574
575int
576set_fpregs(struct thread *td, struct fpreg *regs)
577{
578 return (0);
579}
580
581int
582fill_dbregs(struct thread *td, struct dbreg *regs)
583{
584 return (0);
585}
586int
587set_dbregs(struct thread *td, struct dbreg *regs)
588{
589 return (0);
590}
591
592
593static int
594ptrace_read_int(struct thread *td, vm_offset_t addr, u_int32_t *v)
595{
596 struct iovec iov;
597 struct uio uio;
598
599 PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
600 iov.iov_base = (caddr_t) v;
601 iov.iov_len = sizeof(u_int32_t);
602 uio.uio_iov = &iov;
603 uio.uio_iovcnt = 1;
604 uio.uio_offset = (off_t)addr;
605 uio.uio_resid = sizeof(u_int32_t);
606 uio.uio_segflg = UIO_SYSSPACE;
607 uio.uio_rw = UIO_READ;
608 uio.uio_td = td;
609 return proc_rwmem(td->td_proc, &uio);
610}
611
612static int
613ptrace_write_int(struct thread *td, vm_offset_t addr, u_int32_t v)
614{
615 struct iovec iov;
616 struct uio uio;
617
618 PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
619 iov.iov_base = (caddr_t) &v;
620 iov.iov_len = sizeof(u_int32_t);
621 uio.uio_iov = &iov;
622 uio.uio_iovcnt = 1;
623 uio.uio_offset = (off_t)addr;
624 uio.uio_resid = sizeof(u_int32_t);
625 uio.uio_segflg = UIO_SYSSPACE;
626 uio.uio_rw = UIO_WRITE;
627 uio.uio_td = td;
628 return proc_rwmem(td->td_proc, &uio);
629}
630
631int
632ptrace_single_step(struct thread *td)
633{
634 struct proc *p;
635 int error;
| 573}
574
575int
576set_fpregs(struct thread *td, struct fpreg *regs)
577{
578 return (0);
579}
580
581int
582fill_dbregs(struct thread *td, struct dbreg *regs)
583{
584 return (0);
585}
586int
587set_dbregs(struct thread *td, struct dbreg *regs)
588{
589 return (0);
590}
591
592
593static int
594ptrace_read_int(struct thread *td, vm_offset_t addr, u_int32_t *v)
595{
596 struct iovec iov;
597 struct uio uio;
598
599 PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
600 iov.iov_base = (caddr_t) v;
601 iov.iov_len = sizeof(u_int32_t);
602 uio.uio_iov = &iov;
603 uio.uio_iovcnt = 1;
604 uio.uio_offset = (off_t)addr;
605 uio.uio_resid = sizeof(u_int32_t);
606 uio.uio_segflg = UIO_SYSSPACE;
607 uio.uio_rw = UIO_READ;
608 uio.uio_td = td;
609 return proc_rwmem(td->td_proc, &uio);
610}
611
612static int
613ptrace_write_int(struct thread *td, vm_offset_t addr, u_int32_t v)
614{
615 struct iovec iov;
616 struct uio uio;
617
618 PROC_LOCK_ASSERT(td->td_proc, MA_NOTOWNED);
619 iov.iov_base = (caddr_t) &v;
620 iov.iov_len = sizeof(u_int32_t);
621 uio.uio_iov = &iov;
622 uio.uio_iovcnt = 1;
623 uio.uio_offset = (off_t)addr;
624 uio.uio_resid = sizeof(u_int32_t);
625 uio.uio_segflg = UIO_SYSSPACE;
626 uio.uio_rw = UIO_WRITE;
627 uio.uio_td = td;
628 return proc_rwmem(td->td_proc, &uio);
629}
630
631int
632ptrace_single_step(struct thread *td)
633{
634 struct proc *p;
635 int error;
|
636
| 636
|
637 /* TODO: This needs to be updated for Thumb-2 */
638 if ((td->td_frame->tf_spsr & PSR_T) != 0)
639 return (EINVAL);
640
641 KASSERT(td->td_md.md_ptrace_instr == 0,
642 ("Didn't clear single step"));
643 p = td->td_proc;
644 PROC_UNLOCK(p);
645 error = ptrace_read_int(td, td->td_frame->tf_pc + 4,
646 &td->td_md.md_ptrace_instr);
647 if (error)
648 goto out;
649 error = ptrace_write_int(td, td->td_frame->tf_pc + 4,
650 PTRACE_BREAKPOINT);
651 if (error)
652 td->td_md.md_ptrace_instr = 0;
653 td->td_md.md_ptrace_addr = td->td_frame->tf_pc + 4;
654out:
655 PROC_LOCK(p);
656 return (error);
657}
658
659int
660ptrace_clear_single_step(struct thread *td)
661{
662 struct proc *p;
663
664 /* TODO: This needs to be updated for Thumb-2 */
665 if ((td->td_frame->tf_spsr & PSR_T) != 0)
666 return (EINVAL);
667
668 if (td->td_md.md_ptrace_instr) {
669 p = td->td_proc;
670 PROC_UNLOCK(p);
671 ptrace_write_int(td, td->td_md.md_ptrace_addr,
672 td->td_md.md_ptrace_instr);
673 PROC_LOCK(p);
674 td->td_md.md_ptrace_instr = 0;
675 }
676 return (0);
677}
678
679int
680ptrace_set_pc(struct thread *td, unsigned long addr)
681{
682 td->td_frame->tf_pc = addr;
683 return (0);
684}
685
686void
687cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
688{
689}
690
691void
692spinlock_enter(void)
693{
694 struct thread *td;
695 register_t cspr;
696
697 td = curthread;
698 if (td->td_md.md_spinlock_count == 0) {
699 cspr = disable_interrupts(PSR_I | PSR_F);
700 td->td_md.md_spinlock_count = 1;
701 td->td_md.md_saved_cspr = cspr;
702 } else
703 td->td_md.md_spinlock_count++;
704 critical_enter();
705}
706
707void
708spinlock_exit(void)
709{
710 struct thread *td;
711 register_t cspr;
712
713 td = curthread;
714 critical_exit();
715 cspr = td->td_md.md_saved_cspr;
716 td->td_md.md_spinlock_count--;
717 if (td->td_md.md_spinlock_count == 0)
718 restore_interrupts(cspr);
719}
720
721/*
722 * Clear registers on exec
723 */
724void
725exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
726{
727 struct trapframe *tf = td->td_frame;
728
729 memset(tf, 0, sizeof(*tf));
730 tf->tf_usr_sp = stack;
731 tf->tf_usr_lr = imgp->entry_addr;
732 tf->tf_svc_lr = 0x77777777;
733 tf->tf_pc = imgp->entry_addr;
734 tf->tf_spsr = PSR_USR32_MODE;
735}
736
737/*
738 * Get machine context.
739 */
740int
741get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret)
742{
743 struct trapframe *tf = td->td_frame;
744 __greg_t *gr = mcp->__gregs;
745
746 if (clear_ret & GET_MC_CLEAR_RET)
747 gr[_REG_R0] = 0;
748 else
749 gr[_REG_R0] = tf->tf_r0;
750 gr[_REG_R1] = tf->tf_r1;
751 gr[_REG_R2] = tf->tf_r2;
752 gr[_REG_R3] = tf->tf_r3;
753 gr[_REG_R4] = tf->tf_r4;
754 gr[_REG_R5] = tf->tf_r5;
755 gr[_REG_R6] = tf->tf_r6;
756 gr[_REG_R7] = tf->tf_r7;
757 gr[_REG_R8] = tf->tf_r8;
758 gr[_REG_R9] = tf->tf_r9;
759 gr[_REG_R10] = tf->tf_r10;
760 gr[_REG_R11] = tf->tf_r11;
761 gr[_REG_R12] = tf->tf_r12;
762 gr[_REG_SP] = tf->tf_usr_sp;
763 gr[_REG_LR] = tf->tf_usr_lr;
764 gr[_REG_PC] = tf->tf_pc;
765 gr[_REG_CPSR] = tf->tf_spsr;
766
767 return (0);
768}
769
770/*
771 * Set machine context.
772 *
773 * However, we don't set any but the user modifiable flags, and we won't
774 * touch the cs selector.
775 */
776int
777set_mcontext(struct thread *td, mcontext_t *mcp)
778{
779 struct trapframe *tf = td->td_frame;
780 const __greg_t *gr = mcp->__gregs;
781
782 tf->tf_r0 = gr[_REG_R0];
783 tf->tf_r1 = gr[_REG_R1];
784 tf->tf_r2 = gr[_REG_R2];
785 tf->tf_r3 = gr[_REG_R3];
786 tf->tf_r4 = gr[_REG_R4];
787 tf->tf_r5 = gr[_REG_R5];
788 tf->tf_r6 = gr[_REG_R6];
789 tf->tf_r7 = gr[_REG_R7];
790 tf->tf_r8 = gr[_REG_R8];
791 tf->tf_r9 = gr[_REG_R9];
792 tf->tf_r10 = gr[_REG_R10];
793 tf->tf_r11 = gr[_REG_R11];
794 tf->tf_r12 = gr[_REG_R12];
795 tf->tf_usr_sp = gr[_REG_SP];
796 tf->tf_usr_lr = gr[_REG_LR];
797 tf->tf_pc = gr[_REG_PC];
798 tf->tf_spsr = gr[_REG_CPSR];
799
800 return (0);
801}
802
803/*
804 * MPSAFE
805 */
806int
807sys_sigreturn(td, uap)
808 struct thread *td;
809 struct sigreturn_args /* {
810 const struct __ucontext *sigcntxp;
811 } */ *uap;
812{
813 ucontext_t uc;
814 int spsr;
| 637 /* TODO: This needs to be updated for Thumb-2 */
638 if ((td->td_frame->tf_spsr & PSR_T) != 0)
639 return (EINVAL);
640
641 KASSERT(td->td_md.md_ptrace_instr == 0,
642 ("Didn't clear single step"));
643 p = td->td_proc;
644 PROC_UNLOCK(p);
645 error = ptrace_read_int(td, td->td_frame->tf_pc + 4,
646 &td->td_md.md_ptrace_instr);
647 if (error)
648 goto out;
649 error = ptrace_write_int(td, td->td_frame->tf_pc + 4,
650 PTRACE_BREAKPOINT);
651 if (error)
652 td->td_md.md_ptrace_instr = 0;
653 td->td_md.md_ptrace_addr = td->td_frame->tf_pc + 4;
654out:
655 PROC_LOCK(p);
656 return (error);
657}
658
659int
660ptrace_clear_single_step(struct thread *td)
661{
662 struct proc *p;
663
664 /* TODO: This needs to be updated for Thumb-2 */
665 if ((td->td_frame->tf_spsr & PSR_T) != 0)
666 return (EINVAL);
667
668 if (td->td_md.md_ptrace_instr) {
669 p = td->td_proc;
670 PROC_UNLOCK(p);
671 ptrace_write_int(td, td->td_md.md_ptrace_addr,
672 td->td_md.md_ptrace_instr);
673 PROC_LOCK(p);
674 td->td_md.md_ptrace_instr = 0;
675 }
676 return (0);
677}
678
679int
680ptrace_set_pc(struct thread *td, unsigned long addr)
681{
682 td->td_frame->tf_pc = addr;
683 return (0);
684}
685
686void
687cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
688{
689}
690
691void
692spinlock_enter(void)
693{
694 struct thread *td;
695 register_t cspr;
696
697 td = curthread;
698 if (td->td_md.md_spinlock_count == 0) {
699 cspr = disable_interrupts(PSR_I | PSR_F);
700 td->td_md.md_spinlock_count = 1;
701 td->td_md.md_saved_cspr = cspr;
702 } else
703 td->td_md.md_spinlock_count++;
704 critical_enter();
705}
706
707void
708spinlock_exit(void)
709{
710 struct thread *td;
711 register_t cspr;
712
713 td = curthread;
714 critical_exit();
715 cspr = td->td_md.md_saved_cspr;
716 td->td_md.md_spinlock_count--;
717 if (td->td_md.md_spinlock_count == 0)
718 restore_interrupts(cspr);
719}
720
721/*
722 * Clear registers on exec
723 */
724void
725exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
726{
727 struct trapframe *tf = td->td_frame;
728
729 memset(tf, 0, sizeof(*tf));
730 tf->tf_usr_sp = stack;
731 tf->tf_usr_lr = imgp->entry_addr;
732 tf->tf_svc_lr = 0x77777777;
733 tf->tf_pc = imgp->entry_addr;
734 tf->tf_spsr = PSR_USR32_MODE;
735}
736
737/*
738 * Get machine context.
739 */
740int
741get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret)
742{
743 struct trapframe *tf = td->td_frame;
744 __greg_t *gr = mcp->__gregs;
745
746 if (clear_ret & GET_MC_CLEAR_RET)
747 gr[_REG_R0] = 0;
748 else
749 gr[_REG_R0] = tf->tf_r0;
750 gr[_REG_R1] = tf->tf_r1;
751 gr[_REG_R2] = tf->tf_r2;
752 gr[_REG_R3] = tf->tf_r3;
753 gr[_REG_R4] = tf->tf_r4;
754 gr[_REG_R5] = tf->tf_r5;
755 gr[_REG_R6] = tf->tf_r6;
756 gr[_REG_R7] = tf->tf_r7;
757 gr[_REG_R8] = tf->tf_r8;
758 gr[_REG_R9] = tf->tf_r9;
759 gr[_REG_R10] = tf->tf_r10;
760 gr[_REG_R11] = tf->tf_r11;
761 gr[_REG_R12] = tf->tf_r12;
762 gr[_REG_SP] = tf->tf_usr_sp;
763 gr[_REG_LR] = tf->tf_usr_lr;
764 gr[_REG_PC] = tf->tf_pc;
765 gr[_REG_CPSR] = tf->tf_spsr;
766
767 return (0);
768}
769
770/*
771 * Set machine context.
772 *
773 * However, we don't set any but the user modifiable flags, and we won't
774 * touch the cs selector.
775 */
776int
777set_mcontext(struct thread *td, mcontext_t *mcp)
778{
779 struct trapframe *tf = td->td_frame;
780 const __greg_t *gr = mcp->__gregs;
781
782 tf->tf_r0 = gr[_REG_R0];
783 tf->tf_r1 = gr[_REG_R1];
784 tf->tf_r2 = gr[_REG_R2];
785 tf->tf_r3 = gr[_REG_R3];
786 tf->tf_r4 = gr[_REG_R4];
787 tf->tf_r5 = gr[_REG_R5];
788 tf->tf_r6 = gr[_REG_R6];
789 tf->tf_r7 = gr[_REG_R7];
790 tf->tf_r8 = gr[_REG_R8];
791 tf->tf_r9 = gr[_REG_R9];
792 tf->tf_r10 = gr[_REG_R10];
793 tf->tf_r11 = gr[_REG_R11];
794 tf->tf_r12 = gr[_REG_R12];
795 tf->tf_usr_sp = gr[_REG_SP];
796 tf->tf_usr_lr = gr[_REG_LR];
797 tf->tf_pc = gr[_REG_PC];
798 tf->tf_spsr = gr[_REG_CPSR];
799
800 return (0);
801}
802
803/*
804 * MPSAFE
805 */
806int
807sys_sigreturn(td, uap)
808 struct thread *td;
809 struct sigreturn_args /* {
810 const struct __ucontext *sigcntxp;
811 } */ *uap;
812{
813 ucontext_t uc;
814 int spsr;
|
815
| 815
|
816 if (uap == NULL)
817 return (EFAULT);
818 if (copyin(uap->sigcntxp, &uc, sizeof(uc)))
819 return (EFAULT);
820 /*
821 * Make sure the processor mode has not been tampered with and
822 * interrupts have not been disabled.
823 */
824 spsr = uc.uc_mcontext.__gregs[_REG_CPSR];
825 if ((spsr & PSR_MODE) != PSR_USR32_MODE ||
826 (spsr & (PSR_I | PSR_F)) != 0)
827 return (EINVAL);
828 /* Restore register context. */
829 set_mcontext(td, &uc.uc_mcontext);
830
831 /* Restore signal mask. */
832 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
833
834 return (EJUSTRETURN);
835}
836
837
838/*
839 * Construct a PCB from a trapframe. This is called from kdb_trap() where
840 * we want to start a backtrace from the function that caused us to enter
841 * the debugger. We have the context in the trapframe, but base the trace
842 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
843 * enough for a backtrace.
844 */
845void
846makectx(struct trapframe *tf, struct pcb *pcb)
847{
848 pcb->pcb_regs.sf_r4 = tf->tf_r4;
849 pcb->pcb_regs.sf_r5 = tf->tf_r5;
850 pcb->pcb_regs.sf_r6 = tf->tf_r6;
851 pcb->pcb_regs.sf_r7 = tf->tf_r7;
852 pcb->pcb_regs.sf_r8 = tf->tf_r8;
853 pcb->pcb_regs.sf_r9 = tf->tf_r9;
854 pcb->pcb_regs.sf_r10 = tf->tf_r10;
855 pcb->pcb_regs.sf_r11 = tf->tf_r11;
856 pcb->pcb_regs.sf_r12 = tf->tf_r12;
857 pcb->pcb_regs.sf_pc = tf->tf_pc;
858 pcb->pcb_regs.sf_lr = tf->tf_usr_lr;
859 pcb->pcb_regs.sf_sp = tf->tf_usr_sp;
860}
861
862/*
863 * Fake up a boot descriptor table
864 */
865vm_offset_t
866fake_preload_metadata(struct arm_boot_params *abp __unused)
867{
868#ifdef DDB
869 vm_offset_t zstart = 0, zend = 0;
870#endif
871 vm_offset_t lastaddr;
872 int i = 0;
873 static uint32_t fake_preload[35];
874
875 fake_preload[i++] = MODINFO_NAME;
876 fake_preload[i++] = strlen("kernel") + 1;
877 strcpy((char*)&fake_preload[i++], "kernel");
878 i += 1;
879 fake_preload[i++] = MODINFO_TYPE;
880 fake_preload[i++] = strlen("elf kernel") + 1;
881 strcpy((char*)&fake_preload[i++], "elf kernel");
882 i += 2;
883 fake_preload[i++] = MODINFO_ADDR;
884 fake_preload[i++] = sizeof(vm_offset_t);
885 fake_preload[i++] = KERNVIRTADDR;
886 fake_preload[i++] = MODINFO_SIZE;
887 fake_preload[i++] = sizeof(uint32_t);
888 fake_preload[i++] = (uint32_t)&end - KERNVIRTADDR;
889#ifdef DDB
890 if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
891 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
892 fake_preload[i++] = sizeof(vm_offset_t);
893 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
894 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
895 fake_preload[i++] = sizeof(vm_offset_t);
896 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
897 lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
898 zend = lastaddr;
899 zstart = *(uint32_t *)(KERNVIRTADDR + 4);
900 db_fetch_ksymtab(zstart, zend);
901 } else
902#endif
903 lastaddr = (vm_offset_t)&end;
904 fake_preload[i++] = 0;
905 fake_preload[i] = 0;
906 preload_metadata = (void *)fake_preload;
907
908 return (lastaddr);
909}
910
911void
912pcpu0_init(void)
913{
914#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B)
915 set_curthread(&thread0);
916#endif
917 pcpu_init(pcpup, 0, sizeof(struct pcpu));
918 PCPU_SET(curthread, &thread0);
919#ifdef VFP
920 PCPU_SET(cpu, 0);
921#endif
922}
923
924#if defined(LINUX_BOOT_ABI)
925vm_offset_t
926linux_parse_boot_param(struct arm_boot_params *abp)
927{
928 struct arm_lbabi_tag *walker;
929 uint32_t revision;
930 uint64_t serial;
931
932 /*
933 * Linux boot ABI: r0 = 0, r1 is the board type (!= 0) and r2
934 * is atags or dtb pointer. If all of these aren't satisfied,
935 * then punt.
936 */
937 if (!(abp->abp_r0 == 0 && abp->abp_r1 != 0 && abp->abp_r2 != 0))
938 return 0;
939
940 board_id = abp->abp_r1;
941 walker = (struct arm_lbabi_tag *)
942 (abp->abp_r2 + KERNVIRTADDR - abp->abp_physaddr);
943
944 /* xxx - Need to also look for binary device tree */
945 if (ATAG_TAG(walker) != ATAG_CORE)
946 return 0;
947
948 atag_list = walker;
949 while (ATAG_TAG(walker) != ATAG_NONE) {
950 switch (ATAG_TAG(walker)) {
951 case ATAG_CORE:
952 break;
953 case ATAG_MEM:
954 arm_physmem_hardware_region(walker->u.tag_mem.start,
955 walker->u.tag_mem.size);
956 break;
957 case ATAG_INITRD2:
958 break;
959 case ATAG_SERIAL:
960 serial = walker->u.tag_sn.low |
961 ((uint64_t)walker->u.tag_sn.high << 32);
962 board_set_serial(serial);
963 break;
964 case ATAG_REVISION:
965 revision = walker->u.tag_rev.rev;
966 board_set_revision(revision);
967 break;
968 case ATAG_CMDLINE:
969 /* XXX open question: Parse this for boothowto? */
970 bcopy(walker->u.tag_cmd.command, linux_command_line,
971 ATAG_SIZE(walker));
972 break;
973 default:
974 break;
975 }
976 walker = ATAG_NEXT(walker);
977 }
978
979 /* Save a copy for later */
980 bcopy(atag_list, atags,
981 (char *)walker - (char *)atag_list + ATAG_SIZE(walker));
982
983 return fake_preload_metadata(abp);
984}
985#endif
986
987#if defined(FREEBSD_BOOT_LOADER)
988vm_offset_t
989freebsd_parse_boot_param(struct arm_boot_params *abp)
990{
991 vm_offset_t lastaddr = 0;
992 void *mdp;
993 void *kmdp;
994#ifdef DDB
995 vm_offset_t ksym_start;
996 vm_offset_t ksym_end;
997#endif
998
999 /*
1000 * Mask metadata pointer: it is supposed to be on page boundary. If
1001 * the first argument (mdp) doesn't point to a valid address the
1002 * bootloader must have passed us something else than the metadata
1003 * ptr, so we give up. Also give up if we cannot find metadta section
1004 * the loader creates that we get all this data out of.
1005 */
1006
1007 if ((mdp = (void *)(abp->abp_r0 & ~PAGE_MASK)) == NULL)
1008 return 0;
1009 preload_metadata = mdp;
1010 kmdp = preload_search_by_type("elf kernel");
1011 if (kmdp == NULL)
1012 return 0;
1013
1014 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1015 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
1016 lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
1017#ifdef DDB
1018 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1019 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1020 db_fetch_ksymtab(ksym_start, ksym_end);
1021#endif
1022 return lastaddr;
1023}
1024#endif
1025
1026vm_offset_t
1027default_parse_boot_param(struct arm_boot_params *abp)
1028{
1029 vm_offset_t lastaddr;
1030
1031#if defined(LINUX_BOOT_ABI)
1032 if ((lastaddr = linux_parse_boot_param(abp)) != 0)
1033 return lastaddr;
1034#endif
1035#if defined(FREEBSD_BOOT_LOADER)
1036 if ((lastaddr = freebsd_parse_boot_param(abp)) != 0)
1037 return lastaddr;
1038#endif
1039 /* Fall back to hardcoded metadata. */
1040 lastaddr = fake_preload_metadata(abp);
1041
1042 return lastaddr;
1043}
1044
1045/*
1046 * Stub version of the boot parameter parsing routine. We are
1047 * called early in initarm, before even VM has been initialized.
1048 * This routine needs to preserve any data that the boot loader
1049 * has passed in before the kernel starts to grow past the end
1050 * of the BSS, traditionally the place boot-loaders put this data.
1051 *
1052 * Since this is called so early, things that depend on the vm system
1053 * being setup (including access to some SoC's serial ports), about
1054 * all that can be done in this routine is to copy the arguments.
1055 *
1056 * This is the default boot parameter parsing routine. Individual
1057 * kernels/boards can override this weak function with one of their
1058 * own. We just fake metadata...
1059 */
1060__weak_reference(default_parse_boot_param, parse_boot_param);
1061
1062/*
1063 * Initialize proc0
1064 */
1065void
1066init_proc0(vm_offset_t kstack)
1067{
1068 proc_linkup0(&proc0, &thread0);
1069 thread0.td_kstack = kstack;
1070 thread0.td_pcb = (struct pcb *)
1071 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
1072 thread0.td_pcb->pcb_flags = 0;
1073 thread0.td_pcb->pcb_vfpcpu = -1;
1074 thread0.td_pcb->pcb_vfpstate.fpscr = VFPSCR_DN | VFPSCR_FZ;
1075 thread0.td_frame = &proc0_tf;
1076 pcpup->pc_curpcb = thread0.td_pcb;
1077}
1078
1079#ifdef ARM_NEW_PMAP
1080void
1081set_stackptrs(int cpu)
1082{
1083
1084 set_stackptr(PSR_IRQ32_MODE,
1085 irqstack + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1086 set_stackptr(PSR_ABT32_MODE,
1087 abtstack + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1088 set_stackptr(PSR_UND32_MODE,
1089 undstack + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1090}
1091#else
1092void
1093set_stackptrs(int cpu)
1094{
1095
1096 set_stackptr(PSR_IRQ32_MODE,
1097 irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1098 set_stackptr(PSR_ABT32_MODE,
1099 abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1100 set_stackptr(PSR_UND32_MODE,
1101 undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1102}
1103#endif
1104
1105#ifdef FDT
1106static char *
1107kenv_next(char *cp)
1108{
1109
1110 if (cp != NULL) {
1111 while (*cp != 0)
1112 cp++;
1113 cp++;
1114 if (*cp == 0)
1115 cp = NULL;
1116 }
1117 return (cp);
1118}
1119
1120static void
1121print_kenv(void)
1122{
1123 char *cp;
1124
1125 debugf("loader passed (static) kenv:\n");
1126 if (kern_envp == NULL) {
1127 debugf(" no env, null ptr\n");
1128 return;
1129 }
1130 debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp);
1131
1132 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
1133 debugf(" %x %s\n", (uint32_t)cp, cp);
1134}
1135
1136#ifndef ARM_NEW_PMAP
1137void *
1138initarm(struct arm_boot_params *abp)
1139{
1140 struct mem_region mem_regions[FDT_MEM_REGIONS];
1141 struct pv_addr kernel_l1pt;
1142 struct pv_addr dpcpu;
1143 vm_offset_t dtbp, freemempos, l2_start, lastaddr;
1144 uint32_t memsize, l2size;
1145 char *env;
1146 void *kmdp;
1147 u_int l1pagetable;
1148 int i, j, err_devmap, mem_regions_sz;
1149
1150 lastaddr = parse_boot_param(abp);
1151 arm_physmem_kernaddr = abp->abp_physaddr;
1152
1153 memsize = 0;
1154
1155 cpuinfo_init();
1156 set_cpufuncs();
1157
1158 /*
1159 * Find the dtb passed in by the boot loader.
1160 */
1161 kmdp = preload_search_by_type("elf kernel");
1162 if (kmdp != NULL)
1163 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
1164 else
1165 dtbp = (vm_offset_t)NULL;
1166
1167#if defined(FDT_DTB_STATIC)
1168 /*
1169 * In case the device tree blob was not retrieved (from metadata) try
1170 * to use the statically embedded one.
1171 */
1172 if (dtbp == (vm_offset_t)NULL)
1173 dtbp = (vm_offset_t)&fdt_static_dtb;
1174#endif
1175
1176 if (OF_install(OFW_FDT, 0) == FALSE)
1177 panic("Cannot install FDT");
1178
1179 if (OF_init((void *)dtbp) != 0)
1180 panic("OF_init failed with the found device tree");
1181
1182 /* Grab physical memory regions information from device tree. */
1183 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0)
1184 panic("Cannot get physical memory regions");
1185 arm_physmem_hardware_regions(mem_regions, mem_regions_sz);
1186
1187 /* Grab reserved memory regions information from device tree. */
1188 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0)
| 816 if (uap == NULL)
817 return (EFAULT);
818 if (copyin(uap->sigcntxp, &uc, sizeof(uc)))
819 return (EFAULT);
820 /*
821 * Make sure the processor mode has not been tampered with and
822 * interrupts have not been disabled.
823 */
824 spsr = uc.uc_mcontext.__gregs[_REG_CPSR];
825 if ((spsr & PSR_MODE) != PSR_USR32_MODE ||
826 (spsr & (PSR_I | PSR_F)) != 0)
827 return (EINVAL);
828 /* Restore register context. */
829 set_mcontext(td, &uc.uc_mcontext);
830
831 /* Restore signal mask. */
832 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
833
834 return (EJUSTRETURN);
835}
836
837
838/*
839 * Construct a PCB from a trapframe. This is called from kdb_trap() where
840 * we want to start a backtrace from the function that caused us to enter
841 * the debugger. We have the context in the trapframe, but base the trace
842 * on the PCB. The PCB doesn't have to be perfect, as long as it contains
843 * enough for a backtrace.
844 */
845void
846makectx(struct trapframe *tf, struct pcb *pcb)
847{
848 pcb->pcb_regs.sf_r4 = tf->tf_r4;
849 pcb->pcb_regs.sf_r5 = tf->tf_r5;
850 pcb->pcb_regs.sf_r6 = tf->tf_r6;
851 pcb->pcb_regs.sf_r7 = tf->tf_r7;
852 pcb->pcb_regs.sf_r8 = tf->tf_r8;
853 pcb->pcb_regs.sf_r9 = tf->tf_r9;
854 pcb->pcb_regs.sf_r10 = tf->tf_r10;
855 pcb->pcb_regs.sf_r11 = tf->tf_r11;
856 pcb->pcb_regs.sf_r12 = tf->tf_r12;
857 pcb->pcb_regs.sf_pc = tf->tf_pc;
858 pcb->pcb_regs.sf_lr = tf->tf_usr_lr;
859 pcb->pcb_regs.sf_sp = tf->tf_usr_sp;
860}
861
862/*
863 * Fake up a boot descriptor table
864 */
865vm_offset_t
866fake_preload_metadata(struct arm_boot_params *abp __unused)
867{
868#ifdef DDB
869 vm_offset_t zstart = 0, zend = 0;
870#endif
871 vm_offset_t lastaddr;
872 int i = 0;
873 static uint32_t fake_preload[35];
874
875 fake_preload[i++] = MODINFO_NAME;
876 fake_preload[i++] = strlen("kernel") + 1;
877 strcpy((char*)&fake_preload[i++], "kernel");
878 i += 1;
879 fake_preload[i++] = MODINFO_TYPE;
880 fake_preload[i++] = strlen("elf kernel") + 1;
881 strcpy((char*)&fake_preload[i++], "elf kernel");
882 i += 2;
883 fake_preload[i++] = MODINFO_ADDR;
884 fake_preload[i++] = sizeof(vm_offset_t);
885 fake_preload[i++] = KERNVIRTADDR;
886 fake_preload[i++] = MODINFO_SIZE;
887 fake_preload[i++] = sizeof(uint32_t);
888 fake_preload[i++] = (uint32_t)&end - KERNVIRTADDR;
889#ifdef DDB
890 if (*(uint32_t *)KERNVIRTADDR == MAGIC_TRAMP_NUMBER) {
891 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_SSYM;
892 fake_preload[i++] = sizeof(vm_offset_t);
893 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 4);
894 fake_preload[i++] = MODINFO_METADATA|MODINFOMD_ESYM;
895 fake_preload[i++] = sizeof(vm_offset_t);
896 fake_preload[i++] = *(uint32_t *)(KERNVIRTADDR + 8);
897 lastaddr = *(uint32_t *)(KERNVIRTADDR + 8);
898 zend = lastaddr;
899 zstart = *(uint32_t *)(KERNVIRTADDR + 4);
900 db_fetch_ksymtab(zstart, zend);
901 } else
902#endif
903 lastaddr = (vm_offset_t)&end;
904 fake_preload[i++] = 0;
905 fake_preload[i] = 0;
906 preload_metadata = (void *)fake_preload;
907
908 return (lastaddr);
909}
910
911void
912pcpu0_init(void)
913{
914#if ARM_ARCH_6 || ARM_ARCH_7A || defined(CPU_MV_PJ4B)
915 set_curthread(&thread0);
916#endif
917 pcpu_init(pcpup, 0, sizeof(struct pcpu));
918 PCPU_SET(curthread, &thread0);
919#ifdef VFP
920 PCPU_SET(cpu, 0);
921#endif
922}
923
924#if defined(LINUX_BOOT_ABI)
925vm_offset_t
926linux_parse_boot_param(struct arm_boot_params *abp)
927{
928 struct arm_lbabi_tag *walker;
929 uint32_t revision;
930 uint64_t serial;
931
932 /*
933 * Linux boot ABI: r0 = 0, r1 is the board type (!= 0) and r2
934 * is atags or dtb pointer. If all of these aren't satisfied,
935 * then punt.
936 */
937 if (!(abp->abp_r0 == 0 && abp->abp_r1 != 0 && abp->abp_r2 != 0))
938 return 0;
939
940 board_id = abp->abp_r1;
941 walker = (struct arm_lbabi_tag *)
942 (abp->abp_r2 + KERNVIRTADDR - abp->abp_physaddr);
943
944 /* xxx - Need to also look for binary device tree */
945 if (ATAG_TAG(walker) != ATAG_CORE)
946 return 0;
947
948 atag_list = walker;
949 while (ATAG_TAG(walker) != ATAG_NONE) {
950 switch (ATAG_TAG(walker)) {
951 case ATAG_CORE:
952 break;
953 case ATAG_MEM:
954 arm_physmem_hardware_region(walker->u.tag_mem.start,
955 walker->u.tag_mem.size);
956 break;
957 case ATAG_INITRD2:
958 break;
959 case ATAG_SERIAL:
960 serial = walker->u.tag_sn.low |
961 ((uint64_t)walker->u.tag_sn.high << 32);
962 board_set_serial(serial);
963 break;
964 case ATAG_REVISION:
965 revision = walker->u.tag_rev.rev;
966 board_set_revision(revision);
967 break;
968 case ATAG_CMDLINE:
969 /* XXX open question: Parse this for boothowto? */
970 bcopy(walker->u.tag_cmd.command, linux_command_line,
971 ATAG_SIZE(walker));
972 break;
973 default:
974 break;
975 }
976 walker = ATAG_NEXT(walker);
977 }
978
979 /* Save a copy for later */
980 bcopy(atag_list, atags,
981 (char *)walker - (char *)atag_list + ATAG_SIZE(walker));
982
983 return fake_preload_metadata(abp);
984}
985#endif
986
987#if defined(FREEBSD_BOOT_LOADER)
988vm_offset_t
989freebsd_parse_boot_param(struct arm_boot_params *abp)
990{
991 vm_offset_t lastaddr = 0;
992 void *mdp;
993 void *kmdp;
994#ifdef DDB
995 vm_offset_t ksym_start;
996 vm_offset_t ksym_end;
997#endif
998
999 /*
1000 * Mask metadata pointer: it is supposed to be on page boundary. If
1001 * the first argument (mdp) doesn't point to a valid address the
1002 * bootloader must have passed us something else than the metadata
1003 * ptr, so we give up. Also give up if we cannot find metadta section
1004 * the loader creates that we get all this data out of.
1005 */
1006
1007 if ((mdp = (void *)(abp->abp_r0 & ~PAGE_MASK)) == NULL)
1008 return 0;
1009 preload_metadata = mdp;
1010 kmdp = preload_search_by_type("elf kernel");
1011 if (kmdp == NULL)
1012 return 0;
1013
1014 boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
1015 kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
1016 lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
1017#ifdef DDB
1018 ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
1019 ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
1020 db_fetch_ksymtab(ksym_start, ksym_end);
1021#endif
1022 return lastaddr;
1023}
1024#endif
1025
1026vm_offset_t
1027default_parse_boot_param(struct arm_boot_params *abp)
1028{
1029 vm_offset_t lastaddr;
1030
1031#if defined(LINUX_BOOT_ABI)
1032 if ((lastaddr = linux_parse_boot_param(abp)) != 0)
1033 return lastaddr;
1034#endif
1035#if defined(FREEBSD_BOOT_LOADER)
1036 if ((lastaddr = freebsd_parse_boot_param(abp)) != 0)
1037 return lastaddr;
1038#endif
1039 /* Fall back to hardcoded metadata. */
1040 lastaddr = fake_preload_metadata(abp);
1041
1042 return lastaddr;
1043}
1044
1045/*
1046 * Stub version of the boot parameter parsing routine. We are
1047 * called early in initarm, before even VM has been initialized.
1048 * This routine needs to preserve any data that the boot loader
1049 * has passed in before the kernel starts to grow past the end
1050 * of the BSS, traditionally the place boot-loaders put this data.
1051 *
1052 * Since this is called so early, things that depend on the vm system
1053 * being setup (including access to some SoC's serial ports), about
1054 * all that can be done in this routine is to copy the arguments.
1055 *
1056 * This is the default boot parameter parsing routine. Individual
1057 * kernels/boards can override this weak function with one of their
1058 * own. We just fake metadata...
1059 */
1060__weak_reference(default_parse_boot_param, parse_boot_param);
1061
1062/*
1063 * Initialize proc0
1064 */
1065void
1066init_proc0(vm_offset_t kstack)
1067{
1068 proc_linkup0(&proc0, &thread0);
1069 thread0.td_kstack = kstack;
1070 thread0.td_pcb = (struct pcb *)
1071 (thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
1072 thread0.td_pcb->pcb_flags = 0;
1073 thread0.td_pcb->pcb_vfpcpu = -1;
1074 thread0.td_pcb->pcb_vfpstate.fpscr = VFPSCR_DN | VFPSCR_FZ;
1075 thread0.td_frame = &proc0_tf;
1076 pcpup->pc_curpcb = thread0.td_pcb;
1077}
1078
1079#ifdef ARM_NEW_PMAP
1080void
1081set_stackptrs(int cpu)
1082{
1083
1084 set_stackptr(PSR_IRQ32_MODE,
1085 irqstack + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1086 set_stackptr(PSR_ABT32_MODE,
1087 abtstack + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1088 set_stackptr(PSR_UND32_MODE,
1089 undstack + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1090}
1091#else
1092void
1093set_stackptrs(int cpu)
1094{
1095
1096 set_stackptr(PSR_IRQ32_MODE,
1097 irqstack.pv_va + ((IRQ_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1098 set_stackptr(PSR_ABT32_MODE,
1099 abtstack.pv_va + ((ABT_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1100 set_stackptr(PSR_UND32_MODE,
1101 undstack.pv_va + ((UND_STACK_SIZE * PAGE_SIZE) * (cpu + 1)));
1102}
1103#endif
1104
1105#ifdef FDT
1106static char *
1107kenv_next(char *cp)
1108{
1109
1110 if (cp != NULL) {
1111 while (*cp != 0)
1112 cp++;
1113 cp++;
1114 if (*cp == 0)
1115 cp = NULL;
1116 }
1117 return (cp);
1118}
1119
1120static void
1121print_kenv(void)
1122{
1123 char *cp;
1124
1125 debugf("loader passed (static) kenv:\n");
1126 if (kern_envp == NULL) {
1127 debugf(" no env, null ptr\n");
1128 return;
1129 }
1130 debugf(" kern_envp = 0x%08x\n", (uint32_t)kern_envp);
1131
1132 for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
1133 debugf(" %x %s\n", (uint32_t)cp, cp);
1134}
1135
1136#ifndef ARM_NEW_PMAP
1137void *
1138initarm(struct arm_boot_params *abp)
1139{
1140 struct mem_region mem_regions[FDT_MEM_REGIONS];
1141 struct pv_addr kernel_l1pt;
1142 struct pv_addr dpcpu;
1143 vm_offset_t dtbp, freemempos, l2_start, lastaddr;
1144 uint32_t memsize, l2size;
1145 char *env;
1146 void *kmdp;
1147 u_int l1pagetable;
1148 int i, j, err_devmap, mem_regions_sz;
1149
1150 lastaddr = parse_boot_param(abp);
1151 arm_physmem_kernaddr = abp->abp_physaddr;
1152
1153 memsize = 0;
1154
1155 cpuinfo_init();
1156 set_cpufuncs();
1157
1158 /*
1159 * Find the dtb passed in by the boot loader.
1160 */
1161 kmdp = preload_search_by_type("elf kernel");
1162 if (kmdp != NULL)
1163 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
1164 else
1165 dtbp = (vm_offset_t)NULL;
1166
1167#if defined(FDT_DTB_STATIC)
1168 /*
1169 * In case the device tree blob was not retrieved (from metadata) try
1170 * to use the statically embedded one.
1171 */
1172 if (dtbp == (vm_offset_t)NULL)
1173 dtbp = (vm_offset_t)&fdt_static_dtb;
1174#endif
1175
1176 if (OF_install(OFW_FDT, 0) == FALSE)
1177 panic("Cannot install FDT");
1178
1179 if (OF_init((void *)dtbp) != 0)
1180 panic("OF_init failed with the found device tree");
1181
1182 /* Grab physical memory regions information from device tree. */
1183 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0)
1184 panic("Cannot get physical memory regions");
1185 arm_physmem_hardware_regions(mem_regions, mem_regions_sz);
1186
1187 /* Grab reserved memory regions information from device tree. */
1188 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0)
|
1189 arm_physmem_exclude_regions(mem_regions, mem_regions_sz,
| 1189 arm_physmem_exclude_regions(mem_regions, mem_regions_sz,
|
1190 EXFLAG_NODUMP | EXFLAG_NOALLOC);
1191
1192 /* Platform-specific initialisation */
1193 platform_probe_and_attach();
1194
1195 pcpu0_init();
1196
1197 /* Do basic tuning, hz etc */
1198 init_param1();
1199
1200 /* Calculate number of L2 tables needed for mapping vm_page_array */
1201 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page);
1202 l2size = (l2size >> L1_S_SHIFT) + 1;
1203
1204 /*
1205 * Add one table for end of kernel map, one for stacks, msgbuf and
1206 * L1 and L2 tables map and one for vectors map.
1207 */
1208 l2size += 3;
1209
1210 /* Make it divisible by 4 */
1211 l2size = (l2size + 3) & ~3;
1212
1213 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
1214
1215 /* Define a macro to simplify memory allocation */
1216#define valloc_pages(var, np) \
1217 alloc_pages((var).pv_va, (np)); \
1218 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
1219
1220#define alloc_pages(var, np) \
1221 (var) = freemempos; \
1222 freemempos += (np * PAGE_SIZE); \
1223 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1224
1225 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
1226 freemempos += PAGE_SIZE;
1227 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
1228
1229 for (i = 0, j = 0; i < l2size; ++i) {
1230 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
1231 valloc_pages(kernel_pt_table[i],
1232 L2_TABLE_SIZE / PAGE_SIZE);
1233 j = i;
1234 } else {
1235 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va +
1236 L2_TABLE_SIZE_REAL * (i - j);
1237 kernel_pt_table[i].pv_pa =
1238 kernel_pt_table[i].pv_va - KERNVIRTADDR +
1239 abp->abp_physaddr;
1240
1241 }
1242 }
1243 /*
1244 * Allocate a page for the system page mapped to 0x00000000
1245 * or 0xffff0000. This page will just contain the system vectors
1246 * and can be shared by all processes.
1247 */
1248 valloc_pages(systempage, 1);
1249
1250 /* Allocate dynamic per-cpu area. */
1251 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1252 dpcpu_init((void *)dpcpu.pv_va, 0);
1253
1254 /* Allocate stacks for all modes */
1255 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
1256 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
1257 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
1258 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
1259 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1260
1261 /*
1262 * Now we start construction of the L1 page table
1263 * We start by mapping the L2 page tables into the L1.
1264 * This means that we can replace L1 mappings later on if necessary
1265 */
1266 l1pagetable = kernel_l1pt.pv_va;
1267
1268 /*
1269 * Try to map as much as possible of kernel text and data using
1270 * 1MB section mapping and for the rest of initial kernel address
1271 * space use L2 coarse tables.
1272 *
1273 * Link L2 tables for mapping remainder of kernel (modulo 1MB)
1274 * and kernel structures
1275 */
1276 l2_start = lastaddr & ~(L1_S_OFFSET);
1277 for (i = 0 ; i < l2size - 1; i++)
1278 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE,
1279 &kernel_pt_table[i]);
1280
1281 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE;
1282
1283 /* Map kernel code and data */
1284 pmap_map_chunk(l1pagetable, KERNVIRTADDR, abp->abp_physaddr,
1285 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK,
1286 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
1287
1288 /* Map L1 directory and allocated L2 page tables */
1289 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
1290 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
1291
1292 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va,
1293 kernel_pt_table[0].pv_pa,
1294 L2_TABLE_SIZE_REAL * l2size,
1295 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
1296
1297 /* Map allocated DPCPU, stacks and msgbuf */
1298 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa,
1299 freemempos - dpcpu.pv_va,
1300 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
1301
1302 /* Link and map the vector page */
1303 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
1304 &kernel_pt_table[l2size - 1]);
1305 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
1306 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE);
1307
1308 /* Establish static device mappings. */
1309 err_devmap = platform_devmap_init();
1310 arm_devmap_bootstrap(l1pagetable, NULL);
1311 vm_max_kernel_address = platform_lastaddr();
1312
1313 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
1314 pmap_pa = kernel_l1pt.pv_pa;
1315 setttb(kernel_l1pt.pv_pa);
1316 cpu_tlb_flushID();
1317 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
1318
1319 /*
1320 * Now that proper page tables are installed, call cpu_setup() to enable
1321 * instruction and data caches and other chip-specific features.
1322 */
1323 cpu_setup();
1324
1325 /*
1326 * Only after the SOC registers block is mapped we can perform device
1327 * tree fixups, as they may attempt to read parameters from hardware.
1328 */
1329 OF_interpret("perform-fixup", 0);
1330
1331 platform_gpio_init();
1332
1333 cninit();
1334
1335 debugf("initarm: console initialized\n");
1336 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp);
1337 debugf(" boothowto = 0x%08x\n", boothowto);
1338 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
1339 print_kenv();
1340
1341 env = kern_getenv("kernelname");
1342 if (env != NULL) {
1343 strlcpy(kernelname, env, sizeof(kernelname));
1344 freeenv(env);
1345 }
1346
1347 if (err_devmap != 0)
1348 printf("WARNING: could not fully configure devmap, error=%d\n",
1349 err_devmap);
1350
1351 platform_late_init();
1352
1353 /*
1354 * Pages were allocated during the secondary bootstrap for the
1355 * stacks for different CPU modes.
1356 * We must now set the r13 registers in the different CPU modes to
1357 * point to these stacks.
1358 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
1359 * of the stack memory.
1360 */
1361 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
1362
1363 set_stackptrs(0);
1364
1365 /*
1366 * We must now clean the cache again....
1367 * Cleaning may be done by reading new data to displace any
1368 * dirty data in the cache. This will have happened in setttb()
1369 * but since we are boot strapping the addresses used for the read
1370 * may have just been remapped and thus the cache could be out
1371 * of sync. A re-clean after the switch will cure this.
1372 * After booting there are no gross relocations of the kernel thus
1373 * this problem will not occur after initarm().
1374 */
1375 cpu_idcache_wbinv_all();
1376
1377 undefined_init();
1378
1379 init_proc0(kernelstack.pv_va);
1380
1381 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
1382 pmap_bootstrap(freemempos, &kernel_l1pt);
1383 msgbufp = (void *)msgbufpv.pv_va;
1384 msgbufinit(msgbufp, msgbufsize);
1385 mutex_init();
1386
1387 /*
1388 * Exclude the kernel (and all the things we allocated which immediately
1389 * follow the kernel) from the VM allocation pool but not from crash
1390 * dumps. virtual_avail is a global variable which tracks the kva we've
1391 * "allocated" while setting up pmaps.
1392 *
1393 * Prepare the list of physical memory available to the vm subsystem.
1394 */
| 1190 EXFLAG_NODUMP | EXFLAG_NOALLOC);
1191
1192 /* Platform-specific initialisation */
1193 platform_probe_and_attach();
1194
1195 pcpu0_init();
1196
1197 /* Do basic tuning, hz etc */
1198 init_param1();
1199
1200 /* Calculate number of L2 tables needed for mapping vm_page_array */
1201 l2size = (memsize / PAGE_SIZE) * sizeof(struct vm_page);
1202 l2size = (l2size >> L1_S_SHIFT) + 1;
1203
1204 /*
1205 * Add one table for end of kernel map, one for stacks, msgbuf and
1206 * L1 and L2 tables map and one for vectors map.
1207 */
1208 l2size += 3;
1209
1210 /* Make it divisible by 4 */
1211 l2size = (l2size + 3) & ~3;
1212
1213 freemempos = (lastaddr + PAGE_MASK) & ~PAGE_MASK;
1214
1215 /* Define a macro to simplify memory allocation */
1216#define valloc_pages(var, np) \
1217 alloc_pages((var).pv_va, (np)); \
1218 (var).pv_pa = (var).pv_va + (abp->abp_physaddr - KERNVIRTADDR);
1219
1220#define alloc_pages(var, np) \
1221 (var) = freemempos; \
1222 freemempos += (np * PAGE_SIZE); \
1223 memset((char *)(var), 0, ((np) * PAGE_SIZE));
1224
1225 while (((freemempos - L1_TABLE_SIZE) & (L1_TABLE_SIZE - 1)) != 0)
1226 freemempos += PAGE_SIZE;
1227 valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
1228
1229 for (i = 0, j = 0; i < l2size; ++i) {
1230 if (!(i % (PAGE_SIZE / L2_TABLE_SIZE_REAL))) {
1231 valloc_pages(kernel_pt_table[i],
1232 L2_TABLE_SIZE / PAGE_SIZE);
1233 j = i;
1234 } else {
1235 kernel_pt_table[i].pv_va = kernel_pt_table[j].pv_va +
1236 L2_TABLE_SIZE_REAL * (i - j);
1237 kernel_pt_table[i].pv_pa =
1238 kernel_pt_table[i].pv_va - KERNVIRTADDR +
1239 abp->abp_physaddr;
1240
1241 }
1242 }
1243 /*
1244 * Allocate a page for the system page mapped to 0x00000000
1245 * or 0xffff0000. This page will just contain the system vectors
1246 * and can be shared by all processes.
1247 */
1248 valloc_pages(systempage, 1);
1249
1250 /* Allocate dynamic per-cpu area. */
1251 valloc_pages(dpcpu, DPCPU_SIZE / PAGE_SIZE);
1252 dpcpu_init((void *)dpcpu.pv_va, 0);
1253
1254 /* Allocate stacks for all modes */
1255 valloc_pages(irqstack, IRQ_STACK_SIZE * MAXCPU);
1256 valloc_pages(abtstack, ABT_STACK_SIZE * MAXCPU);
1257 valloc_pages(undstack, UND_STACK_SIZE * MAXCPU);
1258 valloc_pages(kernelstack, KSTACK_PAGES * MAXCPU);
1259 valloc_pages(msgbufpv, round_page(msgbufsize) / PAGE_SIZE);
1260
1261 /*
1262 * Now we start construction of the L1 page table
1263 * We start by mapping the L2 page tables into the L1.
1264 * This means that we can replace L1 mappings later on if necessary
1265 */
1266 l1pagetable = kernel_l1pt.pv_va;
1267
1268 /*
1269 * Try to map as much as possible of kernel text and data using
1270 * 1MB section mapping and for the rest of initial kernel address
1271 * space use L2 coarse tables.
1272 *
1273 * Link L2 tables for mapping remainder of kernel (modulo 1MB)
1274 * and kernel structures
1275 */
1276 l2_start = lastaddr & ~(L1_S_OFFSET);
1277 for (i = 0 ; i < l2size - 1; i++)
1278 pmap_link_l2pt(l1pagetable, l2_start + i * L1_S_SIZE,
1279 &kernel_pt_table[i]);
1280
1281 pmap_curmaxkvaddr = l2_start + (l2size - 1) * L1_S_SIZE;
1282
1283 /* Map kernel code and data */
1284 pmap_map_chunk(l1pagetable, KERNVIRTADDR, abp->abp_physaddr,
1285 (((uint32_t)(lastaddr) - KERNVIRTADDR) + PAGE_MASK) & ~PAGE_MASK,
1286 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
1287
1288 /* Map L1 directory and allocated L2 page tables */
1289 pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
1290 L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
1291
1292 pmap_map_chunk(l1pagetable, kernel_pt_table[0].pv_va,
1293 kernel_pt_table[0].pv_pa,
1294 L2_TABLE_SIZE_REAL * l2size,
1295 VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
1296
1297 /* Map allocated DPCPU, stacks and msgbuf */
1298 pmap_map_chunk(l1pagetable, dpcpu.pv_va, dpcpu.pv_pa,
1299 freemempos - dpcpu.pv_va,
1300 VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
1301
1302 /* Link and map the vector page */
1303 pmap_link_l2pt(l1pagetable, ARM_VECTORS_HIGH,
1304 &kernel_pt_table[l2size - 1]);
1305 pmap_map_entry(l1pagetable, ARM_VECTORS_HIGH, systempage.pv_pa,
1306 VM_PROT_READ|VM_PROT_WRITE|VM_PROT_EXECUTE, PTE_CACHE);
1307
1308 /* Establish static device mappings. */
1309 err_devmap = platform_devmap_init();
1310 arm_devmap_bootstrap(l1pagetable, NULL);
1311 vm_max_kernel_address = platform_lastaddr();
1312
1313 cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2)) | DOMAIN_CLIENT);
1314 pmap_pa = kernel_l1pt.pv_pa;
1315 setttb(kernel_l1pt.pv_pa);
1316 cpu_tlb_flushID();
1317 cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL * 2));
1318
1319 /*
1320 * Now that proper page tables are installed, call cpu_setup() to enable
1321 * instruction and data caches and other chip-specific features.
1322 */
1323 cpu_setup();
1324
1325 /*
1326 * Only after the SOC registers block is mapped we can perform device
1327 * tree fixups, as they may attempt to read parameters from hardware.
1328 */
1329 OF_interpret("perform-fixup", 0);
1330
1331 platform_gpio_init();
1332
1333 cninit();
1334
1335 debugf("initarm: console initialized\n");
1336 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp);
1337 debugf(" boothowto = 0x%08x\n", boothowto);
1338 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
1339 print_kenv();
1340
1341 env = kern_getenv("kernelname");
1342 if (env != NULL) {
1343 strlcpy(kernelname, env, sizeof(kernelname));
1344 freeenv(env);
1345 }
1346
1347 if (err_devmap != 0)
1348 printf("WARNING: could not fully configure devmap, error=%d\n",
1349 err_devmap);
1350
1351 platform_late_init();
1352
1353 /*
1354 * Pages were allocated during the secondary bootstrap for the
1355 * stacks for different CPU modes.
1356 * We must now set the r13 registers in the different CPU modes to
1357 * point to these stacks.
1358 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
1359 * of the stack memory.
1360 */
1361 cpu_control(CPU_CONTROL_MMU_ENABLE, CPU_CONTROL_MMU_ENABLE);
1362
1363 set_stackptrs(0);
1364
1365 /*
1366 * We must now clean the cache again....
1367 * Cleaning may be done by reading new data to displace any
1368 * dirty data in the cache. This will have happened in setttb()
1369 * but since we are boot strapping the addresses used for the read
1370 * may have just been remapped and thus the cache could be out
1371 * of sync. A re-clean after the switch will cure this.
1372 * After booting there are no gross relocations of the kernel thus
1373 * this problem will not occur after initarm().
1374 */
1375 cpu_idcache_wbinv_all();
1376
1377 undefined_init();
1378
1379 init_proc0(kernelstack.pv_va);
1380
1381 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
1382 pmap_bootstrap(freemempos, &kernel_l1pt);
1383 msgbufp = (void *)msgbufpv.pv_va;
1384 msgbufinit(msgbufp, msgbufsize);
1385 mutex_init();
1386
1387 /*
1388 * Exclude the kernel (and all the things we allocated which immediately
1389 * follow the kernel) from the VM allocation pool but not from crash
1390 * dumps. virtual_avail is a global variable which tracks the kva we've
1391 * "allocated" while setting up pmaps.
1392 *
1393 * Prepare the list of physical memory available to the vm subsystem.
1394 */
|
1395 arm_physmem_exclude_region(abp->abp_physaddr,
| 1395 arm_physmem_exclude_region(abp->abp_physaddr,
|
1396 (virtual_avail - KERNVIRTADDR), EXFLAG_NOALLOC);
1397 arm_physmem_init_kernel_globals();
1398
1399 init_param2(physmem);
1400 kdb_init();
1401
1402 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
1403 sizeof(struct pcb)));
1404}
1405#else /* !ARM_NEW_PMAP */
1406void *
1407initarm(struct arm_boot_params *abp)
1408{
1409 struct mem_region mem_regions[FDT_MEM_REGIONS];
1410 vm_paddr_t lastaddr;
1411 vm_offset_t dtbp, kernelstack, dpcpu;
1412 uint32_t memsize;
1413 char *env;
1414 void *kmdp;
1415 int err_devmap, mem_regions_sz;
1416
1417 /* get last allocated physical address */
1418 arm_physmem_kernaddr = abp->abp_physaddr;
1419 lastaddr = parse_boot_param(abp) - KERNVIRTADDR + arm_physmem_kernaddr;
1420
1421 memsize = 0;
1422 set_cpufuncs();
1423 cpuinfo_init();
1424
1425 /*
1426 * Find the dtb passed in by the boot loader.
1427 */
1428 kmdp = preload_search_by_type("elf kernel");
1429 if (kmdp != NULL)
1430 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
1431 else
1432 dtbp = (vm_offset_t)NULL;
1433#if defined(FDT_DTB_STATIC)
1434 /*
1435 * In case the device tree blob was not retrieved (from metadata) try
1436 * to use the statically embedded one.
1437 */
1438 if (dtbp == (vm_offset_t)NULL)
1439 dtbp = (vm_offset_t)&fdt_static_dtb;
1440#endif
1441
1442 if (OF_install(OFW_FDT, 0) == FALSE)
1443 panic("Cannot install FDT");
1444
1445 if (OF_init((void *)dtbp) != 0)
1446 panic("OF_init failed with the found device tree");
1447
1448 /* Grab physical memory regions information from device tree. */
1449 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0)
1450 panic("Cannot get physical memory regions");
1451 arm_physmem_hardware_regions(mem_regions, mem_regions_sz);
1452
1453 /* Grab reserved memory regions information from device tree. */
1454 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0)
1455 arm_physmem_exclude_regions(mem_regions, mem_regions_sz,
1456 EXFLAG_NODUMP | EXFLAG_NOALLOC);
1457
1458 /*
1459 * Set TEX remapping registers.
1460 * Setup kernel page tables and switch to kernel L1 page table.
1461 */
1462 pmap_set_tex();
1463 pmap_bootstrap_prepare(lastaddr);
1464
1465 /*
1466 * Now that proper page tables are installed, call cpu_setup() to enable
1467 * instruction and data caches and other chip-specific features.
1468 */
1469 cpu_setup();
1470
1471 /* Platform-specific initialisation */
1472 platform_probe_and_attach();
1473 pcpu0_init();
1474
1475 /* Do basic tuning, hz etc */
1476 init_param1();
1477
1478 /*
1479 * Allocate a page for the system page mapped to 0xffff0000
1480 * This page will just contain the system vectors and can be
1481 * shared by all processes.
1482 */
1483 systempage = pmap_preboot_get_pages(1);
1484
1485 /* Map the vector page. */
1486 pmap_preboot_map_pages(systempage, ARM_VECTORS_HIGH, 1);
1487 if (virtual_end >= ARM_VECTORS_HIGH)
1488 virtual_end = ARM_VECTORS_HIGH - 1;
1489
1490 /* Allocate dynamic per-cpu area. */
1491 dpcpu = pmap_preboot_get_vpages(DPCPU_SIZE / PAGE_SIZE);
1492 dpcpu_init((void *)dpcpu, 0);
1493
1494 /* Allocate stacks for all modes */
1495 irqstack = pmap_preboot_get_vpages(IRQ_STACK_SIZE * MAXCPU);
1496 abtstack = pmap_preboot_get_vpages(ABT_STACK_SIZE * MAXCPU);
1497 undstack = pmap_preboot_get_vpages(UND_STACK_SIZE * MAXCPU );
1498 kernelstack = pmap_preboot_get_vpages(KSTACK_PAGES * MAXCPU);
1499
1500 /* Allocate message buffer. */
1501 msgbufp = (void *)pmap_preboot_get_vpages(
1502 round_page(msgbufsize) / PAGE_SIZE);
1503
1504 /*
1505 * Pages were allocated during the secondary bootstrap for the
1506 * stacks for different CPU modes.
1507 * We must now set the r13 registers in the different CPU modes to
1508 * point to these stacks.
1509 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
1510 * of the stack memory.
1511 */
1512 set_stackptrs(0);
1513 mutex_init();
1514
1515 /* Establish static device mappings. */
1516 err_devmap = platform_devmap_init();
1517 arm_devmap_bootstrap(0, NULL);
1518 vm_max_kernel_address = platform_lastaddr();
1519
1520 /*
1521 * Only after the SOC registers block is mapped we can perform device
1522 * tree fixups, as they may attempt to read parameters from hardware.
1523 */
1524 OF_interpret("perform-fixup", 0);
1525 platform_gpio_init();
1526 cninit();
1527
1528 debugf("initarm: console initialized\n");
1529 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp);
1530 debugf(" boothowto = 0x%08x\n", boothowto);
1531 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
1532 debugf(" lastaddr1: 0x%08x\n", lastaddr);
1533 print_kenv();
1534
1535 env = kern_getenv("kernelname");
1536 if (env != NULL)
1537 strlcpy(kernelname, env, sizeof(kernelname));
1538
1539 if (err_devmap != 0)
1540 printf("WARNING: could not fully configure devmap, error=%d\n",
1541 err_devmap);
1542
1543 platform_late_init();
1544
1545 /*
1546 * We must now clean the cache again....
1547 * Cleaning may be done by reading new data to displace any
1548 * dirty data in the cache. This will have happened in setttb()
1549 * but since we are boot strapping the addresses used for the read
1550 * may have just been remapped and thus the cache could be out
1551 * of sync. A re-clean after the switch will cure this.
1552 * After booting there are no gross relocations of the kernel thus
1553 * this problem will not occur after initarm().
1554 */
1555 /* Set stack for exception handlers */
1556 undefined_init();
1557 init_proc0(kernelstack);
1558 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
1559 enable_interrupts(PSR_A);
1560 pmap_bootstrap(0);
1561
1562 /* Exclude the kernel (and all the things we allocated which immediately
1563 * follow the kernel) from the VM allocation pool but not from crash
1564 * dumps. virtual_avail is a global variable which tracks the kva we've
1565 * "allocated" while setting up pmaps.
1566 *
1567 * Prepare the list of physical memory available to the vm subsystem.
1568 */
1569 arm_physmem_exclude_region(abp->abp_physaddr,
1570 pmap_preboot_get_pages(0) - abp->abp_physaddr, EXFLAG_NOALLOC);
1571 arm_physmem_init_kernel_globals();
1572
1573 init_param2(physmem);
1574 /* Init message buffer. */
1575 msgbufinit(msgbufp, msgbufsize);
1576 kdb_init();
1577 return ((void *)STACKALIGN(thread0.td_pcb));
1578
1579}
1580
1581#endif /* !ARM_NEW_PMAP */
1582#endif /* FDT */
| 1396 (virtual_avail - KERNVIRTADDR), EXFLAG_NOALLOC);
1397 arm_physmem_init_kernel_globals();
1398
1399 init_param2(physmem);
1400 kdb_init();
1401
1402 return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP -
1403 sizeof(struct pcb)));
1404}
1405#else /* !ARM_NEW_PMAP */
1406void *
1407initarm(struct arm_boot_params *abp)
1408{
1409 struct mem_region mem_regions[FDT_MEM_REGIONS];
1410 vm_paddr_t lastaddr;
1411 vm_offset_t dtbp, kernelstack, dpcpu;
1412 uint32_t memsize;
1413 char *env;
1414 void *kmdp;
1415 int err_devmap, mem_regions_sz;
1416
1417 /* get last allocated physical address */
1418 arm_physmem_kernaddr = abp->abp_physaddr;
1419 lastaddr = parse_boot_param(abp) - KERNVIRTADDR + arm_physmem_kernaddr;
1420
1421 memsize = 0;
1422 set_cpufuncs();
1423 cpuinfo_init();
1424
1425 /*
1426 * Find the dtb passed in by the boot loader.
1427 */
1428 kmdp = preload_search_by_type("elf kernel");
1429 if (kmdp != NULL)
1430 dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
1431 else
1432 dtbp = (vm_offset_t)NULL;
1433#if defined(FDT_DTB_STATIC)
1434 /*
1435 * In case the device tree blob was not retrieved (from metadata) try
1436 * to use the statically embedded one.
1437 */
1438 if (dtbp == (vm_offset_t)NULL)
1439 dtbp = (vm_offset_t)&fdt_static_dtb;
1440#endif
1441
1442 if (OF_install(OFW_FDT, 0) == FALSE)
1443 panic("Cannot install FDT");
1444
1445 if (OF_init((void *)dtbp) != 0)
1446 panic("OF_init failed with the found device tree");
1447
1448 /* Grab physical memory regions information from device tree. */
1449 if (fdt_get_mem_regions(mem_regions, &mem_regions_sz, &memsize) != 0)
1450 panic("Cannot get physical memory regions");
1451 arm_physmem_hardware_regions(mem_regions, mem_regions_sz);
1452
1453 /* Grab reserved memory regions information from device tree. */
1454 if (fdt_get_reserved_regions(mem_regions, &mem_regions_sz) == 0)
1455 arm_physmem_exclude_regions(mem_regions, mem_regions_sz,
1456 EXFLAG_NODUMP | EXFLAG_NOALLOC);
1457
1458 /*
1459 * Set TEX remapping registers.
1460 * Setup kernel page tables and switch to kernel L1 page table.
1461 */
1462 pmap_set_tex();
1463 pmap_bootstrap_prepare(lastaddr);
1464
1465 /*
1466 * Now that proper page tables are installed, call cpu_setup() to enable
1467 * instruction and data caches and other chip-specific features.
1468 */
1469 cpu_setup();
1470
1471 /* Platform-specific initialisation */
1472 platform_probe_and_attach();
1473 pcpu0_init();
1474
1475 /* Do basic tuning, hz etc */
1476 init_param1();
1477
1478 /*
1479 * Allocate a page for the system page mapped to 0xffff0000
1480 * This page will just contain the system vectors and can be
1481 * shared by all processes.
1482 */
1483 systempage = pmap_preboot_get_pages(1);
1484
1485 /* Map the vector page. */
1486 pmap_preboot_map_pages(systempage, ARM_VECTORS_HIGH, 1);
1487 if (virtual_end >= ARM_VECTORS_HIGH)
1488 virtual_end = ARM_VECTORS_HIGH - 1;
1489
1490 /* Allocate dynamic per-cpu area. */
1491 dpcpu = pmap_preboot_get_vpages(DPCPU_SIZE / PAGE_SIZE);
1492 dpcpu_init((void *)dpcpu, 0);
1493
1494 /* Allocate stacks for all modes */
1495 irqstack = pmap_preboot_get_vpages(IRQ_STACK_SIZE * MAXCPU);
1496 abtstack = pmap_preboot_get_vpages(ABT_STACK_SIZE * MAXCPU);
1497 undstack = pmap_preboot_get_vpages(UND_STACK_SIZE * MAXCPU );
1498 kernelstack = pmap_preboot_get_vpages(KSTACK_PAGES * MAXCPU);
1499
1500 /* Allocate message buffer. */
1501 msgbufp = (void *)pmap_preboot_get_vpages(
1502 round_page(msgbufsize) / PAGE_SIZE);
1503
1504 /*
1505 * Pages were allocated during the secondary bootstrap for the
1506 * stacks for different CPU modes.
1507 * We must now set the r13 registers in the different CPU modes to
1508 * point to these stacks.
1509 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
1510 * of the stack memory.
1511 */
1512 set_stackptrs(0);
1513 mutex_init();
1514
1515 /* Establish static device mappings. */
1516 err_devmap = platform_devmap_init();
1517 arm_devmap_bootstrap(0, NULL);
1518 vm_max_kernel_address = platform_lastaddr();
1519
1520 /*
1521 * Only after the SOC registers block is mapped we can perform device
1522 * tree fixups, as they may attempt to read parameters from hardware.
1523 */
1524 OF_interpret("perform-fixup", 0);
1525 platform_gpio_init();
1526 cninit();
1527
1528 debugf("initarm: console initialized\n");
1529 debugf(" arg1 kmdp = 0x%08x\n", (uint32_t)kmdp);
1530 debugf(" boothowto = 0x%08x\n", boothowto);
1531 debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
1532 debugf(" lastaddr1: 0x%08x\n", lastaddr);
1533 print_kenv();
1534
1535 env = kern_getenv("kernelname");
1536 if (env != NULL)
1537 strlcpy(kernelname, env, sizeof(kernelname));
1538
1539 if (err_devmap != 0)
1540 printf("WARNING: could not fully configure devmap, error=%d\n",
1541 err_devmap);
1542
1543 platform_late_init();
1544
1545 /*
1546 * We must now clean the cache again....
1547 * Cleaning may be done by reading new data to displace any
1548 * dirty data in the cache. This will have happened in setttb()
1549 * but since we are boot strapping the addresses used for the read
1550 * may have just been remapped and thus the cache could be out
1551 * of sync. A re-clean after the switch will cure this.
1552 * After booting there are no gross relocations of the kernel thus
1553 * this problem will not occur after initarm().
1554 */
1555 /* Set stack for exception handlers */
1556 undefined_init();
1557 init_proc0(kernelstack);
1558 arm_vector_init(ARM_VECTORS_HIGH, ARM_VEC_ALL);
1559 enable_interrupts(PSR_A);
1560 pmap_bootstrap(0);
1561
1562 /* Exclude the kernel (and all the things we allocated which immediately
1563 * follow the kernel) from the VM allocation pool but not from crash
1564 * dumps. virtual_avail is a global variable which tracks the kva we've
1565 * "allocated" while setting up pmaps.
1566 *
1567 * Prepare the list of physical memory available to the vm subsystem.
1568 */
1569 arm_physmem_exclude_region(abp->abp_physaddr,
1570 pmap_preboot_get_pages(0) - abp->abp_physaddr, EXFLAG_NOALLOC);
1571 arm_physmem_init_kernel_globals();
1572
1573 init_param2(physmem);
1574 /* Init message buffer. */
1575 msgbufinit(msgbufp, msgbufsize);
1576 kdb_init();
1577 return ((void *)STACKALIGN(thread0.td_pcb));
1578
1579}
1580
1581#endif /* !ARM_NEW_PMAP */
1582#endif /* FDT */
|