| busdma_machdep-v6.c (274536) | busdma_machdep-v6.c (274538) |
|---|---|
| 1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * --- 17 unchanged lines hidden (view full) --- 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * --- 17 unchanged lines hidden (view full) --- 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 274536 2014-11-15 02:58:17Z ian $"); | 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 274538 2014-11-15 03:39:58Z ian $"); |
| 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> --- 1337 unchanged lines hidden (view full) --- 1380 physcopyin((void *)bpage->vaddr, 1381 bpage->dataaddr, 1382 bpage->datacount); 1383 bpage = STAILQ_NEXT(bpage, links); 1384 } 1385 dmat->bounce_zone->total_bounced++; 1386 } 1387 } | 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> --- 1337 unchanged lines hidden (view full) --- 1380 physcopyin((void *)bpage->vaddr, 1381 bpage->dataaddr, 1382 bpage->datacount); 1383 bpage = STAILQ_NEXT(bpage, links); 1384 } 1385 dmat->bounce_zone->total_bounced++; 1386 } 1387 } |
| 1388 if (map->flags & DMAMAP_COHERENT) | 1388 1389 /* 1390 * For COHERENT memory no cache maintenance is necessary, but ensure all 1391 * writes have reached memory for the PREWRITE case. 1392 */ 1393 if (map->flags & DMAMAP_COHERENT) { 1394 if (op & BUS_DMASYNC_PREWRITE) { 1395 dsb(); 1396 cpu_l2cache_drain_writebuf(); 1397 } |
| 1389 return; | 1398 return; |
| 1399 } |
|
| 1390 1391 if (map->sync_count != 0) { 1392 if (!pmap_dmap_iscurrent(map->pmap)) 1393 panic("_bus_dmamap_sync: wrong user map for sync."); 1394 /* ARM caches are not self-snooping for dma */ 1395 1396 sl = &map->slist[0]; 1397 end = &map->slist[map->sync_count]; --- 291 unchanged lines hidden --- | 1400 1401 if (map->sync_count != 0) { 1402 if (!pmap_dmap_iscurrent(map->pmap)) 1403 panic("_bus_dmamap_sync: wrong user map for sync."); 1404 /* ARM caches are not self-snooping for dma */ 1405 1406 sl = &map->slist[0]; 1407 end = &map->slist[map->sync_count]; --- 291 unchanged lines hidden --- |