| busdma_machdep-v6.c (247776) | busdma_machdep-v6.c (248655) |
|---|---|
| 1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * --- 17 unchanged lines hidden (view full) --- 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> | 1/*- 2 * Copyright (c) 2012 Ian Lepore 3 * Copyright (c) 2010 Mark Tinguely 4 * Copyright (c) 2004 Olivier Houchard 5 * Copyright (c) 2002 Peter Grehan 6 * Copyright (c) 1997, 1998 Justin T. Gibbs. 7 * All rights reserved. 8 * --- 17 unchanged lines hidden (view full) --- 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * From i386/busdma_machdep.c 191438 2009-04-23 20:24:19Z jhb 31 */ 32 33#include <sys/cdefs.h> |
| 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 247776 2013-03-04 10:41:54Z cognet $"); | 34__FBSDID("$FreeBSD: head/sys/arm/arm/busdma_machdep-v6.c 248655 2013-03-23 17:17:06Z ian $"); |
| 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> --- 1102 unchanged lines hidden (view full) --- 1145 struct bounce_page *bpage; 1146 struct sync_list *sl, *end; 1147 bus_size_t len, unalign; 1148 vm_offset_t buf, ebuf; 1149#ifdef FIX_DMAP_BUS_DMASYNC_POSTREAD 1150 vm_offset_t bbuf; 1151 char _tmp_cl[arm_dcache_align], _tmp_clend[arm_dcache_align]; 1152#endif | 35 36#define _ARM32_BUS_DMA_PRIVATE 37#include <sys/param.h> 38#include <sys/kdb.h> 39#include <ddb/ddb.h> 40#include <ddb/db_output.h> 41#include <sys/systm.h> 42#include <sys/malloc.h> --- 1102 unchanged lines hidden (view full) --- 1145 struct bounce_page *bpage; 1146 struct sync_list *sl, *end; 1147 bus_size_t len, unalign; 1148 vm_offset_t buf, ebuf; 1149#ifdef FIX_DMAP_BUS_DMASYNC_POSTREAD 1150 vm_offset_t bbuf; 1151 char _tmp_cl[arm_dcache_align], _tmp_clend[arm_dcache_align]; 1152#endif |
| 1153 /* if buffer was from user space, it it possible that this 1154 * is not the same vm map. The fix is to map each page in 1155 * the buffer into the current address space (KVM) and then 1156 * do the bounce copy or sync list cache operation. 1157 * 1158 * The sync list entries are already broken into 1159 * their respective physical pages. 1160 */ 1161 if (!pmap_dmap_iscurrent(map->pmap)) 1162 printf("_bus_dmamap_sync: wrong user map: %p %x\n", map->pmap, op); 1163 | 1153 /* 1154 * If the buffer was from user space, it is possible that this is not 1155 * the same vm map, especially on a POST operation. It's not clear that 1156 * dma on userland buffers can work at all right now, certainly not if a 1157 * partial cacheline flush has to be handled. To be safe, until we're 1158 * able to test direct userland dma, panic on a map mismatch. 1159 */ |
| 1164 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { | 1160 if ((bpage = STAILQ_FIRST(&map->bpages)) != NULL) { |
| 1165 | 1161 if (!pmap_dmap_iscurrent(map->pmap)) 1162 panic("_bus_dmamap_sync: wrong user map for bounce sync."); |
| 1166 /* Handle data bouncing. */ 1167 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1168 "performing bounce", __func__, dmat, dmat->flags, op); 1169 1170 if (op & BUS_DMASYNC_PREWRITE) { 1171 while (bpage != NULL) { 1172 if (bpage->datavaddr != 0) 1173 bcopy((void *)bpage->datavaddr, --- 9 unchanged lines hidden (view full) --- 1183 (vm_offset_t)bpage->busaddr, 1184 bpage->datacount); 1185 bpage = STAILQ_NEXT(bpage, links); 1186 } 1187 dmat->bounce_zone->total_bounced++; 1188 } 1189 1190 if (op & BUS_DMASYNC_POSTREAD) { | 1163 /* Handle data bouncing. */ 1164 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1165 "performing bounce", __func__, dmat, dmat->flags, op); 1166 1167 if (op & BUS_DMASYNC_PREWRITE) { 1168 while (bpage != NULL) { 1169 if (bpage->datavaddr != 0) 1170 bcopy((void *)bpage->datavaddr, --- 9 unchanged lines hidden (view full) --- 1180 (vm_offset_t)bpage->busaddr, 1181 bpage->datacount); 1182 bpage = STAILQ_NEXT(bpage, links); 1183 } 1184 dmat->bounce_zone->total_bounced++; 1185 } 1186 1187 if (op & BUS_DMASYNC_POSTREAD) { |
| 1191 if (!pmap_dmap_iscurrent(map->pmap)) 1192 panic("_bus_dmamap_sync: wrong user map. apply fix"); 1193 | |
| 1194 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1195 bpage->datacount); 1196 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1197 (vm_offset_t)bpage->busaddr, 1198 bpage->datacount); 1199 while (bpage != NULL) { 1200 vm_offset_t startv; 1201 vm_paddr_t startp; --- 23 unchanged lines hidden (view full) --- 1225 } 1226 dmat->bounce_zone->total_bounced++; 1227 } 1228 } 1229 if (map->flags & DMAMAP_COHERENT) 1230 return; 1231 1232 if (map->sync_count != 0) { | 1188 cpu_dcache_inv_range((vm_offset_t)bpage->vaddr, 1189 bpage->datacount); 1190 l2cache_inv_range((vm_offset_t)bpage->vaddr, 1191 (vm_offset_t)bpage->busaddr, 1192 bpage->datacount); 1193 while (bpage != NULL) { 1194 vm_offset_t startv; 1195 vm_paddr_t startp; --- 23 unchanged lines hidden (view full) --- 1219 } 1220 dmat->bounce_zone->total_bounced++; 1221 } 1222 } 1223 if (map->flags & DMAMAP_COHERENT) 1224 return; 1225 1226 if (map->sync_count != 0) { |
| 1227 if (!pmap_dmap_iscurrent(map->pmap)) 1228 panic("_bus_dmamap_sync: wrong user map for sync."); |
|
| 1233 /* ARM caches are not self-snooping for dma */ 1234 1235 sl = &map->slist[0]; 1236 end = &map->slist[map->sync_count]; 1237 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1238 "performing sync", __func__, dmat, dmat->flags, op); 1239 1240 switch (op) { --- 57 unchanged lines hidden (view full) --- 1298 l2cache_wbinv_range(sl->vaddr, 1299 sl->busaddr, sl->datacount); 1300 sl++; 1301 } 1302 break; 1303 1304#ifdef FIX_DMAP_BUS_DMASYNC_POSTREAD 1305 case BUS_DMASYNC_POSTREAD: | 1229 /* ARM caches are not self-snooping for dma */ 1230 1231 sl = &map->slist[0]; 1232 end = &map->slist[map->sync_count]; 1233 CTR4(KTR_BUSDMA, "%s: tag %p tag flags 0x%x op 0x%x " 1234 "performing sync", __func__, dmat, dmat->flags, op); 1235 1236 switch (op) { --- 57 unchanged lines hidden (view full) --- 1294 l2cache_wbinv_range(sl->vaddr, 1295 sl->busaddr, sl->datacount); 1296 sl++; 1297 } 1298 break; 1299 1300#ifdef FIX_DMAP_BUS_DMASYNC_POSTREAD 1301 case BUS_DMASYNC_POSTREAD: |
| 1306 if (!pmap_dmap_iscurrent(map->pmap)) 1307 panic("_bus_dmamap_sync: wrong user map. apply fix"); | |
| 1308 while (sl != end) { 1309 /* write back the unaligned portions */ 1310 vm_paddr_t physaddr; 1311 register_t s = 0; 1312 1313 buf = sl->vaddr; 1314 len = sl->datacount; 1315 physaddr = sl->busaddr; --- 302 unchanged lines hidden --- | 1302 while (sl != end) { 1303 /* write back the unaligned portions */ 1304 vm_paddr_t physaddr; 1305 register_t s = 0; 1306 1307 buf = sl->vaddr; 1308 len = sl->datacount; 1309 physaddr = sl->busaddr; --- 302 unchanged lines hidden --- |