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aw_gate.c (308324) aw_gate.c (309762)
1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 9 unchanged lines hidden (view full) ---

18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: stable/11/sys/arm/allwinner/clk/aw_gate.c 308324 2016-11-05 04:17:32Z mmel $
26 * $FreeBSD: stable/11/sys/arm/allwinner/clk/aw_gate.c 309762 2016-12-09 20:35:01Z manu $
27 */
28
29/*
30 * Allwinner clock gates
31 */
32
33#include <sys/cdefs.h>
27 */
28
29/*
30 * Allwinner clock gates
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/clk/aw_gate.c 308324 2016-11-05 04:17:32Z mmel $");
34__FBSDID("$FreeBSD: stable/11/sys/arm/allwinner/clk/aw_gate.c 309762 2016-12-09 20:35:01Z manu $");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <machine/bus.h>
43
44#include <dev/ofw/ofw_bus.h>
45#include <dev/ofw/ofw_bus_subr.h>
46#include <dev/ofw/ofw_subr.h>
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <machine/bus.h>
43
44#include <dev/ofw/ofw_bus.h>
45#include <dev/ofw/ofw_bus_subr.h>
46#include <dev/ofw/ofw_subr.h>
47#include <dev/fdt/fdt_common.h>
47
48#include <dev/extres/clk/clk_gate.h>
49
50#define GATE_OFFSET(index) ((index / 32) * 4)
51#define GATE_SHIFT(index) (index % 32)
52
53static struct ofw_compat_data compat_data[] = {
54 { "allwinner,sun4i-a10-dram-gates-clk",

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84 (uintptr_t)"Allwinner APB2 Clock Gates" },
85
86 { "allwinner,sun8i-a83t-bus-gates-clk",
87 (uintptr_t)"Allwinner Bus Clock Gates" },
88 { "allwinner,sun8i-a83t-apb0-gates-clk",
89 (uintptr_t)"Allwinner APB0 Clock Gates" },
90
91 { "allwinner,sun8i-h3-bus-gates-clk",
48
49#include <dev/extres/clk/clk_gate.h>
50
51#define GATE_OFFSET(index) ((index / 32) * 4)
52#define GATE_SHIFT(index) (index % 32)
53
54static struct ofw_compat_data compat_data[] = {
55 { "allwinner,sun4i-a10-dram-gates-clk",

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85 (uintptr_t)"Allwinner APB2 Clock Gates" },
86
87 { "allwinner,sun8i-a83t-bus-gates-clk",
88 (uintptr_t)"Allwinner Bus Clock Gates" },
89 { "allwinner,sun8i-a83t-apb0-gates-clk",
90 (uintptr_t)"Allwinner APB0 Clock Gates" },
91
92 { "allwinner,sun8i-h3-bus-gates-clk",
92 (uintptr_t)"Allwinner Bus Clock Gates"},
93 (uintptr_t)"Allwinner Bus Clock Gates" },
94 { "allwinner,sun8i-h3-apb0-gates-clk",
95 (uintptr_t)"Allwinner APB0 Clock Gates" },
93
94 { "allwinner,sun9i-a80-apbs-gates-clk",
95 (uintptr_t)"Allwinner APBS Clock Gates" },
96
96
97 { "allwinner,sun9i-a80-apbs-gates-clk",
98 (uintptr_t)"Allwinner APBS Clock Gates" },
99
100 { "allwinner,sunxi-multi-bus-gates-clk",
101 (uintptr_t)"Allwinner Multi Bus Clock Gates" },
102
97 { NULL, 0 }
98};
99
100static int
101aw_gate_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
102 const char *pclkname, const char *clkname, int index)
103{
104 const char *parent_names[1] = { pclkname };

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114 def.mask = 1;
115 def.on_value = 1;
116 def.off_value = 0;
117
118 return (clknode_gate_register(clkdom, &def));
119}
120
121static int
103 { NULL, 0 }
104};
105
106static int
107aw_gate_create(device_t dev, bus_addr_t paddr, struct clkdom *clkdom,
108 const char *pclkname, const char *clkname, int index)
109{
110 const char *parent_names[1] = { pclkname };

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120 def.mask = 1;
121 def.on_value = 1;
122 def.off_value = 0;
123
124 return (clknode_gate_register(clkdom, &def));
125}
126
127static int
128aw_gate_add(device_t dev, struct clkdom *clkdom, phandle_t node,
129 bus_addr_t paddr)
130{
131 const char **names;
132 uint32_t *indices;
133 clk_t clk_parent;
134 int index, nout, error;
135
136 indices = NULL;
137
138 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
139 if (nout == 0) {
140 device_printf(dev, "no clock outputs found\n");
141 return (ENOENT);
142 }
143 if (indices == NULL) {
144 device_printf(dev, "no clock-indices property\n");
145 return (ENXIO);
146 }
147
148 error = clk_get_by_ofw_index(dev, node, 0, &clk_parent);
149 if (error != 0) {
150 device_printf(dev, "cannot parse clock parent\n");
151 return (ENXIO);
152 }
153
154 for (index = 0; index < nout; index++) {
155 error = aw_gate_create(dev, paddr, clkdom,
156 clk_get_name(clk_parent), names[index], indices[index]);
157 if (error)
158 return (error);
159 }
160
161 return (0);
162}
163
164static int
122aw_gate_probe(device_t dev)
123{
124 const char *d;
125
126 if (!ofw_bus_status_okay(dev))
127 return (ENXIO);
128
129 d = (const char *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
130 if (d == NULL)
131 return (ENXIO);
132
133 device_set_desc(dev, d);
134 return (BUS_PROBE_DEFAULT);
135}
136
137static int
138aw_gate_attach(device_t dev)
139{
140 struct clkdom *clkdom;
165aw_gate_probe(device_t dev)
166{
167 const char *d;
168
169 if (!ofw_bus_status_okay(dev))
170 return (ENXIO);
171
172 d = (const char *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
173 if (d == NULL)
174 return (ENXIO);
175
176 device_set_desc(dev, d);
177 return (BUS_PROBE_DEFAULT);
178}
179
180static int
181aw_gate_attach(device_t dev)
182{
183 struct clkdom *clkdom;
141 const char **names;
142 int index, nout, error;
143 uint32_t *indices;
144 clk_t clk_parent;
145 bus_addr_t paddr;
146 bus_size_t psize;
184 bus_addr_t paddr;
185 bus_size_t psize;
147 phandle_t node;
186 phandle_t node, child;
148
149 node = ofw_bus_get_node(dev);
187
188 node = ofw_bus_get_node(dev);
150 indices = NULL;
151
152 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
153 device_printf(dev, "cannot parse 'reg' property\n");
154 return (ENXIO);
155 }
156
157 clkdom = clkdom_create(dev);
158
189
190 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
191 device_printf(dev, "cannot parse 'reg' property\n");
192 return (ENXIO);
193 }
194
195 clkdom = clkdom_create(dev);
196
159 nout = clk_parse_ofw_out_names(dev, node, &names, &indices);
160 if (nout == 0) {
161 device_printf(dev, "no clock outputs found\n");
162 error = ENOENT;
163 goto fail;
164 }
165 if (indices == NULL) {
166 device_printf(dev, "no clock-indices property\n");
167 error = ENXIO;
168 goto fail;
169 }
197 if (ofw_bus_is_compatible(dev, "allwinner,sunxi-multi-bus-gates-clk")) {
198 for (child = OF_child(node); child > 0; child = OF_peer(child))
199 aw_gate_add(dev, clkdom, child, paddr);
200 } else
201 aw_gate_add(dev, clkdom, node, paddr);
170
202
171 error = clk_get_by_ofw_index(dev, 0, 0, &clk_parent);
172 if (error != 0) {
173 device_printf(dev, "cannot parse clock parent\n");
174 return (ENXIO);
175 }
176
177 for (index = 0; index < nout; index++) {
178 error = aw_gate_create(dev, paddr, clkdom,
179 clk_get_name(clk_parent), names[index], indices[index]);
180 if (error)
181 goto fail;
182 }
183
184 if (clkdom_finit(clkdom) != 0) {
185 device_printf(dev, "cannot finalize clkdom initialization\n");
203 if (clkdom_finit(clkdom) != 0) {
204 device_printf(dev, "cannot finalize clkdom initialization\n");
186 error = ENXIO;
187 goto fail;
205 return (ENXIO);
188 }
189
190 if (bootverbose)
191 clkdom_dump(clkdom);
192
193 return (0);
206 }
207
208 if (bootverbose)
209 clkdom_dump(clkdom);
210
211 return (0);
194
195fail:
196 return (error);
197}
198
199static device_method_t aw_gate_methods[] = {
200 /* Device interface */
201 DEVMETHOD(device_probe, aw_gate_probe),
202 DEVMETHOD(device_attach, aw_gate_attach),
203
204 DEVMETHOD_END

--- 12 unchanged lines hidden --- 		212}
213
214static device_method_t aw_gate_methods[] = {
215 /* Device interface */
216 DEVMETHOD(device_probe, aw_gate_probe),
217 DEVMETHOD(device_attach, aw_gate_attach),
218
219 DEVMETHOD_END

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