| pmap.h (255732) | pmap.h (256072) |
|---|---|
| 1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1991 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department and William Jolitz of UUNET Technologies Inc. --- 25 unchanged lines hidden (view full) --- 34 * Derived from hp300 version by Mike Hibler, this version by William 35 * Jolitz uses a recursive map [a pde points to the page directory] to 36 * map the page tables using the pagetables themselves. This is done to 37 * reduce the impact on kernel virtual memory for lots of sparse address 38 * space, and to reduce the cost of memory to each process. 39 * 40 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 41 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 | 1/*- 2 * Copyright (c) 2003 Peter Wemm. 3 * Copyright (c) 1991 Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department and William Jolitz of UUNET Technologies Inc. --- 25 unchanged lines hidden (view full) --- 34 * Derived from hp300 version by Mike Hibler, this version by William 35 * Jolitz uses a recursive map [a pde points to the page directory] to 36 * map the page tables using the pagetables themselves. This is done to 37 * reduce the impact on kernel virtual memory for lots of sparse address 38 * space, and to reduce the cost of memory to each process. 39 * 40 * from: hp300: @(#)pmap.h 7.2 (Berkeley) 12/16/90 41 * from: @(#)pmap.h 7.4 (Berkeley) 5/12/91 |
| 42 * $FreeBSD: head/sys/amd64/include/pmap.h 255732 2013-09-20 17:06:49Z neel $ | 42 * $FreeBSD: head/sys/amd64/include/pmap.h 256072 2013-10-05 21:22:35Z neel $ |
| 43 */ 44 45#ifndef _MACHINE_PMAP_H_ 46#define _MACHINE_PMAP_H_ 47 48/* 49 * Page-directory and page-table entries follow this format, with a few 50 * of the fields not present here and there, depending on a lot of things. 51 */ 52 /* ---- Intel Nomenclature ---- */ | 43 */ 44 45#ifndef _MACHINE_PMAP_H_ 46#define _MACHINE_PMAP_H_ 47 48/* 49 * Page-directory and page-table entries follow this format, with a few 50 * of the fields not present here and there, depending on a lot of things. 51 */ 52 /* ---- Intel Nomenclature ---- */ |
| 53#define PG_V 0x001 /* P Valid */ 54#define PG_RW 0x002 /* R/W Read/Write */ 55#define PG_U 0x004 /* U/S User/Supervisor */ 56#define PG_NC_PWT 0x008 /* PWT Write through */ 57#define PG_NC_PCD 0x010 /* PCD Cache disable */ 58#define PG_A 0x020 /* A Accessed */ 59#define PG_M 0x040 /* D Dirty */ 60#define PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ 61#define PG_PTE_PAT 0x080 /* PAT PAT index */ 62#define PG_G 0x100 /* G Global */ 63#define PG_AVAIL1 0x200 /* / Available for system */ 64#define PG_AVAIL2 0x400 /* < programmers use */ 65#define PG_AVAIL3 0x800 /* \ */ 66#define PG_PDE_PAT 0x1000 /* PAT PAT index */ 67#define PG_NX (1ul<<63) /* No-execute */ | 53#define X86_PG_V 0x001 /* P Valid */ 54#define X86_PG_RW 0x002 /* R/W Read/Write */ 55#define X86_PG_U 0x004 /* U/S User/Supervisor */ 56#define X86_PG_NC_PWT 0x008 /* PWT Write through */ 57#define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ 58#define X86_PG_A 0x020 /* A Accessed */ 59#define X86_PG_M 0x040 /* D Dirty */ 60#define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ 61#define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ 62#define X86_PG_G 0x100 /* G Global */ 63#define X86_PG_AVAIL1 0x200 /* / Available for system */ 64#define X86_PG_AVAIL2 0x400 /* < programmers use */ 65#define X86_PG_AVAIL3 0x800 /* \ */ 66#define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ 67#define X86_PG_NX (1ul<<63) /* No-execute */ 68#define X86_PG_AVAIL(x) (1ul << (x)) |
| 68 | 69 |
| 70/* Page level cache control fields used to determine the PAT type */ 71#define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) 72#define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) |
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| 69 | 73 |
| 74/* 75 * Intel extended page table (EPT) bit definitions. 76 */ 77#define EPT_PG_READ 0x001 /* R Read */ 78#define EPT_PG_WRITE 0x002 /* W Write */ 79#define EPT_PG_EXECUTE 0x004 /* X Execute */ 80#define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ 81#define EPT_PG_PS 0x080 /* PS Page size */ 82#define EPT_PG_A 0x100 /* A Accessed */ 83#define EPT_PG_M 0x200 /* D Dirty */ 84#define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ 85 86/* 87 * Define the PG_xx macros in terms of the bits on x86 PTEs. 88 */ 89#define PG_V X86_PG_V 90#define PG_RW X86_PG_RW 91#define PG_U X86_PG_U 92#define PG_NC_PWT X86_PG_NC_PWT 93#define PG_NC_PCD X86_PG_NC_PCD 94#define PG_A X86_PG_A 95#define PG_M X86_PG_M 96#define PG_PS X86_PG_PS 97#define PG_PTE_PAT X86_PG_PTE_PAT 98#define PG_G X86_PG_G 99#define PG_AVAIL1 X86_PG_AVAIL1 100#define PG_AVAIL2 X86_PG_AVAIL2 101#define PG_AVAIL3 X86_PG_AVAIL3 102#define PG_PDE_PAT X86_PG_PDE_PAT 103#define PG_NX X86_PG_NX 104#define PG_PDE_CACHE X86_PG_PDE_CACHE 105#define PG_PTE_CACHE X86_PG_PTE_CACHE 106 |
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| 70/* Our various interpretations of the above */ | 107/* Our various interpretations of the above */ |
| 71#define PG_W PG_AVAIL1 /* "Wired" pseudoflag */ 72#define PG_MANAGED PG_AVAIL2 | 108#define PG_W X86_PG_AVAIL3 /* "Wired" pseudoflag */ 109#define PG_MANAGED X86_PG_AVAIL2 110#define EPT_PG_EMUL_V X86_PG_AVAIL(52) 111#define EPT_PG_EMUL_RW X86_PG_AVAIL(53) |
| 73#define PG_FRAME (0x000ffffffffff000ul) 74#define PG_PS_FRAME (0x000fffffffe00000ul) | 112#define PG_FRAME (0x000ffffffffff000ul) 113#define PG_PS_FRAME (0x000fffffffe00000ul) |
| 75#define PG_PROT (PG_RW|PG_U) /* all protection bits . */ 76#define PG_N (PG_NC_PWT|PG_NC_PCD) /* Non-cacheable */ | |
| 77 | 114 |
| 78/* Page level cache control fields used to determine the PAT type */ 79#define PG_PDE_CACHE (PG_PDE_PAT | PG_NC_PWT | PG_NC_PCD) 80#define PG_PTE_CACHE (PG_PTE_PAT | PG_NC_PWT | PG_NC_PCD) 81 | |
| 82/* 83 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 84 * (PTE) page mappings have identical settings for the following fields: 85 */ | 115/* 116 * Promotion to a 2MB (PDE) page mapping requires that the corresponding 4KB 117 * (PTE) page mappings have identical settings for the following fields: 118 */ |
| 86#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_PAT | \ 87 PG_M | PG_A | PG_NC_PCD | PG_NC_PWT | PG_U | PG_RW | PG_V) | 119#define PG_PTE_PROMOTE (PG_NX | PG_MANAGED | PG_W | PG_G | PG_PTE_CACHE | \ 120 PG_M | PG_A | PG_U | PG_RW | PG_V) |
| 88 89/* 90 * Page Protection Exception bits 91 */ 92 93#define PGEX_P 0x01 /* Protection violation vs. not present */ 94#define PGEX_W 0x02 /* during a Write cycle */ 95#define PGEX_U 0x04 /* access from User mode (UPL) */ 96#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ 97#define PGEX_I 0x10 /* during an instruction fetch */ 98 | 121 122/* 123 * Page Protection Exception bits 124 */ 125 126#define PGEX_P 0x01 /* Protection violation vs. not present */ 127#define PGEX_W 0x02 /* during a Write cycle */ 128#define PGEX_U 0x04 /* access from User mode (UPL) */ 129#define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ 130#define PGEX_I 0x10 /* during an instruction fetch */ 131 |
| 132/* 133 * undef the PG_xx macros that define bits in the regular x86 PTEs that 134 * have a different position in nested PTEs. This is done when compiling 135 * code that needs to be aware of the differences between regular x86 and 136 * nested PTEs. 137 * 138 * The appropriate bitmask will be calculated at runtime based on the pmap 139 * type. 140 */ 141#ifdef AMD64_NPT_AWARE 142#undef PG_AVAIL1 /* X86_PG_AVAIL1 aliases with EPT_PG_M */ 143#undef PG_G 144#undef PG_A 145#undef PG_M 146#undef PG_PDE_PAT 147#undef PG_PDE_CACHE 148#undef PG_PTE_PAT 149#undef PG_PTE_CACHE 150#undef PG_RW 151#undef PG_V 152#endif 153 |
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| 99/* 100 * Pte related macros. This is complicated by having to deal with 101 * the sign extension of the 48th bit. 102 */ 103#define KVADDR(l4, l3, l2, l1) ( \ 104 ((unsigned long)-1 << 47) | \ 105 ((unsigned long)(l4) << PML4SHIFT) | \ 106 ((unsigned long)(l3) << PDPSHIFT) | \ --- 144 unchanged lines hidden (view full) --- 251 int pm_pcid; /* context id */ 252 enum pmap_type pm_type; /* regular or nested tables */ 253 struct pmap_statistics pm_stats; /* pmap statistics */ 254 struct vm_radix pm_root; /* spare page table pages */ 255 long pm_eptgen; /* EPT pmap generation id */ 256 int pm_flags; 257}; 258 | 154/* 155 * Pte related macros. This is complicated by having to deal with 156 * the sign extension of the 48th bit. 157 */ 158#define KVADDR(l4, l3, l2, l1) ( \ 159 ((unsigned long)-1 << 47) | \ 160 ((unsigned long)(l4) << PML4SHIFT) | \ 161 ((unsigned long)(l3) << PDPSHIFT) | \ --- 144 unchanged lines hidden (view full) --- 306 int pm_pcid; /* context id */ 307 enum pmap_type pm_type; /* regular or nested tables */ 308 struct pmap_statistics pm_stats; /* pmap statistics */ 309 struct vm_radix pm_root; /* spare page table pages */ 310 long pm_eptgen; /* EPT pmap generation id */ 311 int pm_flags; 312}; 313 |
| 314/* flags */ 315#define PMAP_PDE_SUPERPAGE (1 << 0) /* supports 2MB superpages */ 316#define PMAP_EMULATE_AD_BITS (1 << 1) /* needs A/D bits emulation */ 317#define PMAP_SUPPORTS_EXEC_ONLY (1 << 2) /* execute only mappings ok */ 318 |
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| 259typedef struct pmap *pmap_t; 260 261#ifdef _KERNEL 262extern struct pmap kernel_pmap_store; 263#define kernel_pmap (&kernel_pmap_store) 264 265#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 266#define PMAP_LOCK_ASSERT(pmap, type) \ 267 mtx_assert(&(pmap)->pm_mtx, (type)) 268#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 269#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 270 NULL, MTX_DEF | MTX_DUPOK) 271#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) 272#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 273#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 274#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) | 319typedef struct pmap *pmap_t; 320 321#ifdef _KERNEL 322extern struct pmap kernel_pmap_store; 323#define kernel_pmap (&kernel_pmap_store) 324 325#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx) 326#define PMAP_LOCK_ASSERT(pmap, type) \ 327 mtx_assert(&(pmap)->pm_mtx, (type)) 328#define PMAP_LOCK_DESTROY(pmap) mtx_destroy(&(pmap)->pm_mtx) 329#define PMAP_LOCK_INIT(pmap) mtx_init(&(pmap)->pm_mtx, "pmap", \ 330 NULL, MTX_DEF | MTX_DUPOK) 331#define PMAP_LOCKED(pmap) mtx_owned(&(pmap)->pm_mtx) 332#define PMAP_MTX(pmap) (&(pmap)->pm_mtx) 333#define PMAP_TRYLOCK(pmap) mtx_trylock(&(pmap)->pm_mtx) 334#define PMAP_UNLOCK(pmap) mtx_unlock(&(pmap)->pm_mtx) |
| 335 336int pmap_pinit_type(pmap_t pmap, enum pmap_type pm_type, int flags); 337int pmap_emulate_accessed_dirty(pmap_t pmap, vm_offset_t va, int ftype); |
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| 275#endif 276 277/* 278 * For each vm_page_t, there is a list of all currently valid virtual 279 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 280 */ 281typedef struct pv_entry { 282 vm_offset_t pv_va; /* virtual address for mapping */ --- 42 unchanged lines hidden (view full) --- 325void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 326void pmap_unmapdev(vm_offset_t, vm_size_t); 327void pmap_invalidate_page(pmap_t, vm_offset_t); 328void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); 329void pmap_invalidate_all(pmap_t); 330void pmap_invalidate_cache(void); 331void pmap_invalidate_cache_pages(vm_page_t *pages, int count); 332void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); | 338#endif 339 340/* 341 * For each vm_page_t, there is a list of all currently valid virtual 342 * mappings of that page. An entry is a pv_entry_t, the list is pv_list. 343 */ 344typedef struct pv_entry { 345 vm_offset_t pv_va; /* virtual address for mapping */ --- 42 unchanged lines hidden (view full) --- 388void pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma); 389void pmap_unmapdev(vm_offset_t, vm_size_t); 390void pmap_invalidate_page(pmap_t, vm_offset_t); 391void pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t); 392void pmap_invalidate_all(pmap_t); 393void pmap_invalidate_cache(void); 394void pmap_invalidate_cache_pages(vm_page_t *pages, int count); 395void pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva); |
| 333 | 396void pmap_get_mapping(pmap_t pmap, vm_offset_t va, uint64_t *ptr, int *num); |
| 334#endif /* _KERNEL */ 335 336#endif /* !LOCORE */ 337 338#endif /* !_MACHINE_PMAP_H_ */ | 397#endif /* _KERNEL */ 398 399#endif /* !LOCORE */ 400 401#endif /* !_MACHINE_PMAP_H_ */ |