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libpmc.c (331722) libpmc.c (339767)
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

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20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: stable/11/lib/libpmc/libpmc.c 331722 2018-03-29 02:50:57Z eadler $");
28__FBSDID("$FreeBSD: stable/11/lib/libpmc/libpmc.c 339767 2018-10-26 05:12:56Z mmacy $");
29
30#include <sys/types.h>
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/pmc.h>
34#include <sys/syscall.h>
35
36#include <ctype.h>

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56static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
57 struct pmc_op_pmcallocate *_pmc_config);
58static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
59 struct pmc_op_pmcallocate *_pmc_config);
60static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
61 struct pmc_op_pmcallocate *_pmc_config);
62static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
63 struct pmc_op_pmcallocate *_pmc_config);
29
30#include <sys/types.h>
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/pmc.h>
34#include <sys/syscall.h>
35
36#include <ctype.h>

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56static int iap_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
57 struct pmc_op_pmcallocate *_pmc_config);
58static int ucf_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
59 struct pmc_op_pmcallocate *_pmc_config);
60static int ucp_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
61 struct pmc_op_pmcallocate *_pmc_config);
62static int k8_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
63 struct pmc_op_pmcallocate *_pmc_config);
64static int f17h_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
65 struct pmc_op_pmcallocate *_pmc_config);
64static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
65 struct pmc_op_pmcallocate *_pmc_config);
66#endif
67#if defined(__i386__)
68static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
69 struct pmc_op_pmcallocate *_pmc_config);
70static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
71 struct pmc_op_pmcallocate *_pmc_config);

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152 static const struct pmc_event_descr N##_event_table[] = \
153 { \
154 __PMC_EV_##C() \
155 }
156
157PMC_CLASSDEP_TABLE(iaf, IAF);
158PMC_CLASSDEP_TABLE(k7, K7);
159PMC_CLASSDEP_TABLE(k8, K8);
66static int p4_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
67 struct pmc_op_pmcallocate *_pmc_config);
68#endif
69#if defined(__i386__)
70static int p5_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
71 struct pmc_op_pmcallocate *_pmc_config);
72static int p6_allocate_pmc(enum pmc_event _pe, char *_ctrspec,
73 struct pmc_op_pmcallocate *_pmc_config);

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154 static const struct pmc_event_descr N##_event_table[] = \
155 { \
156 __PMC_EV_##C() \
157 }
158
159PMC_CLASSDEP_TABLE(iaf, IAF);
160PMC_CLASSDEP_TABLE(k7, K7);
161PMC_CLASSDEP_TABLE(k8, K8);
162PMC_CLASSDEP_TABLE(f17h, F17H);
160PMC_CLASSDEP_TABLE(p4, P4);
161PMC_CLASSDEP_TABLE(p5, P5);
162PMC_CLASSDEP_TABLE(p6, P6);
163PMC_CLASSDEP_TABLE(xscale, XSCALE);
164PMC_CLASSDEP_TABLE(armv7, ARMV7);
165PMC_CLASSDEP_TABLE(armv8, ARMV8);
166PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
167PMC_CLASSDEP_TABLE(mips74k, MIPS74K);

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337PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
338PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
339PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
340PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
341PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
342PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
343PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
344PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
163PMC_CLASSDEP_TABLE(p4, P4);
164PMC_CLASSDEP_TABLE(p5, P5);
165PMC_CLASSDEP_TABLE(p6, P6);
166PMC_CLASSDEP_TABLE(xscale, XSCALE);
167PMC_CLASSDEP_TABLE(armv7, ARMV7);
168PMC_CLASSDEP_TABLE(armv8, ARMV8);
169PMC_CLASSDEP_TABLE(mips24k, MIPS24K);
170PMC_CLASSDEP_TABLE(mips74k, MIPS74K);

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340PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
341PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
342PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
343PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
344PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
345PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
346PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
347PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);
348PMC_MDEP_TABLE(f17h, F17H, PMC_CLASS_SOFT, PMC_CLASS_TSC);
345PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
346PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
347PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
348PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
349PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
350PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
351PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
352PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);

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403PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
404PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
405#endif
406#if defined(__i386__)
407PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
408#endif
409#if defined(__i386__) || defined(__amd64__)
410PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
349PMC_MDEP_TABLE(p4, P4, PMC_CLASS_SOFT, PMC_CLASS_TSC);
350PMC_MDEP_TABLE(p5, P5, PMC_CLASS_SOFT, PMC_CLASS_TSC);
351PMC_MDEP_TABLE(p6, P6, PMC_CLASS_SOFT, PMC_CLASS_TSC);
352PMC_MDEP_TABLE(xscale, XSCALE, PMC_CLASS_SOFT, PMC_CLASS_XSCALE);
353PMC_MDEP_TABLE(cortex_a8, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
354PMC_MDEP_TABLE(cortex_a9, ARMV7, PMC_CLASS_SOFT, PMC_CLASS_ARMV7);
355PMC_MDEP_TABLE(cortex_a53, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);
356PMC_MDEP_TABLE(cortex_a57, ARMV8, PMC_CLASS_SOFT, PMC_CLASS_ARMV8);

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407PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
408PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
409#endif
410#if defined(__i386__)
411PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
412#endif
413#if defined(__i386__) || defined(__amd64__)
414PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);
415PMC_CLASS_TABLE_DESC(f17h, F17H, f17h, f17h);
411PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
412#endif
413#if defined(__i386__)
414PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
415PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
416#endif
417#if defined(__i386__) || defined(__amd64__)
418PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);

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1153 return (-1);
1154
1155 if (n < 0) /* Parsing failed. */
1156 return (-1);
1157 }
1158
1159 return (0);
1160}
416PMC_CLASS_TABLE_DESC(p4, P4, p4, p4);
417#endif
418#if defined(__i386__)
419PMC_CLASS_TABLE_DESC(p5, P5, p5, p5);
420PMC_CLASS_TABLE_DESC(p6, P6, p6, p6);
421#endif
422#if defined(__i386__) || defined(__amd64__)
423PMC_CLASS_TABLE_DESC(tsc, TSC, tsc, tsc);

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1158 return (-1);
1159
1160 if (n < 0) /* Parsing failed. */
1161 return (-1);
1162 }
1163
1164 return (0);
1165}
1166/* AMD Fam17H PMCs */
1167static struct pmc_event_alias f17h_aliases[] = {
1168 EV_ALIAS("branches", "ex_ret_brn_tkn"),
1169 EV_ALIAS("branch-mispredicts",
1170 "ex_ret_brn_tkn_misp"),
1171 EV_ALIAS("cycles", "tsc"),
1172 EV_ALIAS("dc-access", "ls_dc_access"),
1173 EV_ALIAS("ic-misses", "ic_fw32_miss"),
1174 EV_ALIAS("instructions", "ex_ret_inst"),
1175 EV_ALIAS("unhalted-cycles", "ls_not_halted_cycle"),
1176 EV_ALIAS(NULL, NULL)
1177};
1178#define __F17HMASK(N, V) PMCMASK(N, (1 << (V)))
1179static const struct pmc_masks f17h_mask_FPU_PIPEASSIGMENT[] = {
1180 __F17HMASK(FPU_PIPEASSIGMENT_uOP_P0, 0),
1181 __F17HMASK(FPU_PIPEASSIGMENT_uOP_P1, 1),
1182 __F17HMASK(FPU_PIPEASSIGMENT_uOP_P2, 2),
1183 __F17HMASK(FPU_PIPEASSIGMENT_uOP_P3, 3),
1184 __F17HMASK(FPU_PIPEASSIGMENT_MultiuOP_P0, 4),
1185 __F17HMASK(FPU_PIPEASSIGMENT_MultiuOP_P1, 5),
1186 __F17HMASK(FPU_PIPEASSIGMENT_MultiuOP_P2, 6),
1187 __F17HMASK(FPU_PIPEASSIGMENT_MultiuOP_P3, 7),
1188 NULLMASK
1189};
1190static const struct pmc_masks f17h_mask_FP_SCHED_EMPTY[] = {
1191 __F17HMASK(FP_SCHED_EMPTY, 0x0),
1192 NULLMASK
1193};
1194static const struct pmc_masks f17h_mask_FP_RET_X87_FPOPS[] = {
1195 __F17HMASK(FP_RET_X87_ADDSUBOPS, 0),
1196 __F17HMASK(FP_RET_X87_MULOPS, 1),
1197 __F17HMASK(FP_RET_X87_DIVSQRTOPS, 2),
1198 NULLMASK
1199};
1200static const struct pmc_masks f17h_mask_FP_RET_SSEAVX_OPS[] = {
1201 __F17HMASK(FP_RET_SSEAVX_SPADDSUBOPS, 0),
1202 __F17HMASK(FP_RET_SSEAVX_SPMULOPS, 1),
1203 __F17HMASK(FP_RET_SSEAVX_SPDIVOPS, 2),
1204 __F17HMASK(FP_RET_SSEAVX_SPMULADDOPS, 3),
1205 __F17HMASK(FP_RET_SSEAVX_DPADDSUBOPS, 4),
1206 __F17HMASK(FP_RET_SSEAVX_DPMULOPS, 5),
1207 __F17HMASK(FP_RET_SSEAVX_DPDIVOPS, 6),
1208 __F17HMASK(FP_RET_SSEAVX_DPMULADDOPS, 7),
1209 NULLMASK
1210};
1211static const struct pmc_masks f17h_mask_FP_NUM_MOVELIM_SCAL_OPT[] = {
1212 __F17HMASK(FP_NUM_SSEMOV_OPS, 0),
1213 __F17HMASK(FP_NUM_SSEMOV_ELIM, 1),
1214 __F17HMASK(FP_NUM_OPS_OPTPOT, 2),
1215 __F17HMASK(FP_NUM_OPS_OPT, 3),
1216 NULLMASK
1217};
1218static const struct pmc_masks f17h_mask_FP_RET_SEROPS[] = {
1219 __F17HMASK(FP_RET_SSE_BOTEXEC, 0),
1220 __F17HMASK(FP_RET_SSE_CTRL, 1),
1221 __F17HMASK(FP_RET_BOTEXEC, 2),
1222 __F17HMASK(FP_RET_X87_CTRL, 3),
1223 NULLMASK
1224};
1225static const struct pmc_masks f17h_mask_LS_BAD_STATUS2[] = {
1226 __F17HMASK(LS_BAD_STATUS2_STLI_NOSTATE, 0),
1227 __F17HMASK(LS_BAD_STATUS2_STLI_OTHER, 1),
1228 __F17HMASK(LS_BAD_STATUS2_STLF_NODATA, 2),
1229 NULLMASK
1230};
1231static const struct pmc_masks f17h_mask_LS_LOCKS[] = {
1232 __F17HMASK(LS_LOCKS_BUSLOCKS, 0),
1233 __F17HMASK(LS_LOCKS_NONSPECLOCK, 1),
1234 __F17HMASK(LS_SPECLOCK, 2),
1235 __F17HMASK(LS_SPECLCOK_MAPCOMMIT, 3),
1236 NULLMASK
1237};
1238static const struct pmc_masks f17h_mask_LS_RET_CLFLUSH_INST[] = {
1239 __F17HMASK(LS_RET_CLFLUSH_INST, 0x0),
1240 NULLMASK
1241};
1242static const struct pmc_masks f17h_mask_LS_RET_CPUID_INST[] = {
1243 __F17HMASK(LS_RET_CPUID_INST, 0x0),
1244 NULLMASK
1245};
1246static const struct pmc_masks f17h_mask_LS_DISPATCH[] = {
1247 __F17HMASK(LS_DISPATCH_LD, 0),
1248 __F17HMASK(LS_DISPATCH_STR, 1),
1249 __F17HMASK(LS_DISPATCH_LDSTR, 2),
1250 NULLMASK
1251};
1252static const struct pmc_masks f17h_mask_LS_SMI_RX[] = {
1253 __F17HMASK(LS_SMI_RX, 0x0),
1254 NULLMASK
1255};
1256static const struct pmc_masks f17h_mask_LS_STLF[] = {
1257 __F17HMASK(LS_STLF, 0x0),
1258 NULLMASK
1259};
1260static const struct pmc_masks f17h_mask_LS_STLF_COMMITCANCEL[] = {
1261 __F17HMASK(LS_STLF_COMMITCANCEL, 0x0),
1262 NULLMASK
1263};
1264static const struct pmc_masks f17h_mask_LS_DC_ACCESS[] = {
1265 __F17HMASK(LS_DC_ACCESS, 0x0),
1266 NULLMASK
1267};
1268static const struct pmc_masks f17h_mask_LS_MAB_ALLOCPIPE[] = {
1269 __F17HMASK(LS_MAB_ALLOCPIPE_DATAPIPE, 0),
1270 __F17HMASK(LS_MAB_ALLOCPIPE_STPIPE, 1),
1271 __F17HMASK(LS_MAB_ALLOCPIPE_TLBPIPELATE, 2),
1272 __F17HMASK(LS_MAB_ALLOCPIPE_HWPF, 3),
1273 __F17HMASK(LS_MAB_ALLOCPIPE_TLPPIPEEARLY, 4),
1274 NULLMASK
1275};
1276static const struct pmc_masks f17h_mask_LS_REFFILS_FROM_SYS[] = {
1277 __F17HMASK(LS_MABRESP_LCL_L2, 0),
1278 __F17HMASK(LS_MABRESP_LCL_CACHE, 1),
1279 __F17HMASK(LS_MABRESP_LCL_DRAM, 3),
1280 __F17HMASK(LS_MABRESP_LCL_RMT_CACHE, 4),
1281 __F17HMASK(LS_MABRESP_LCL_RMT_DRAM, 6),
1282 NULLMASK
1283};
1284static const struct pmc_masks f17h_mask_LS_L1_DTLBMISS[] = {
1285 __F17HMASK(LS_TLBRELOAD_4KL2HIT, 0),
1286 __F17HMASK(LS_TLBRELOAD_32KL2HIT, 1),
1287 __F17HMASK(LS_TLBRELOAD_2ML2HIT, 2),
1288 __F17HMASK(LS_TLBRELOAD_1GL2HIT, 3),
1289 __F17HMASK(LS_TLBRELOAD_4KL2MISS, 4),
1290 __F17HMASK(LS_TLBRELOAD_32KML2MISS, 5),
1291 __F17HMASK(LS_TLBRELOAD_2ML2MISS, 6),
1292 __F17HMASK(LS_TLBRELOAD_1GL2MISS, 7),
1293 NULLMASK
1294};
1295static const struct pmc_masks f17h_mask_LS_TABLEWALKER[] = {
1296 __F17HMASK(LS_PERFMON_TW_ALLOCDSIDE0, 0),
1297 __F17HMASK(LS_PERFMON_TW_ALLOCDSIDE1, 1),
1298 __F17HMASK(LS_PERFMON_TW_ALLOCISIDE0, 2),
1299 __F17HMASK(LS_PERFMON_TW_ALLOCISIDE1, 3),
1300 NULLMASK
1301};
1302static const struct pmc_masks f17h_mask_LS_MISAL_ACCESS[] = {
1303 __F17HMASK(LS_MISAL_ACCESS, 0x0),
1304 NULLMASK
1305};
1306static const struct pmc_masks f17h_mask_LS_PREF_INST_DISPATCH[] = {
1307 __F17HMASK(LS_LOAD_PREF_W, 0),
1308 __F17HMASK(LS_STORE_PREF_W, 1),
1309 __F17HMASK(LS_PREF_PREFETCH_NTA, 2),
1310 NULLMASK
1311};
1312static const struct pmc_masks f17h_mask_LS_HWPF_ALLOCATED[] = {
1313 __F17HMASK(LS_ALLOC_STREAM_PF, 0),
1314 __F17HMASK(LS_ALLOC_STRIDE_PF, 1),
1315 NULLMASK
1316};
1317static const struct pmc_masks f17h_mask_LS_HWPF_HIT[] = {
1318 __F17HMASK(LS_HIT_STREAM_PF, 0),
1319 __F17HMASK(LS_HIT_STRIDE_PF, 1),
1320 NULLMASK
1321};
1322static const struct pmc_masks f17h_mask_LS_TW_INPROG_DSIDE[] = {
1323 __F17HMASK(LS_TW_INPROG_DSIDE0, 0),
1324 __F17HMASK(LS_TW_INPROG_ISIDE0, 1),
1325 __F17HMASK(LS_TW_INPROG_DSIDE1, 2),
1326 __F17HMASK(LS_TW_INPROG_ISIDE1, 3),
1327 NULLMASK
1328};
1329static const struct pmc_masks f17h_mask_LS_INEF_SW_PREF[] = {
1330 __F17HMASK(LS_INEF_SW_PREF_DATAPIPE_SW_PF_DCHIT, 0),
1331 __F17HMASK(LS_INEF_SW_PREF_MAB_MCH_CNT, 1),
1332 NULLMASK
1333};
1334static const struct pmc_masks f17h_mask_LS_MAB_MCH_CNT[] = {
1335 __F17HMASK(LS_MAB_MCH_CNT, 0x0),
1336 NULLMASK
1337};
1338static const struct pmc_masks f17h_mask_LS_HW_PF_MABALLOC[] = {
1339 __F17HMASK(LS_MABALLOC_HW_PFSTREAM, 0),
1340 __F17HMASK(LS_MABALLOC_HW_PFSTRIDE, 1),
1341 __F17HMASK(LS_MABALLOC_PFREGION, 2),
1342 NULLMASK
1343};
1344static const struct pmc_masks f17h_mask_LS_HW_PF_MATCH[] = {
1345 __F17HMASK(LS_MATCH_HW_PFSTREAM, 0),
1346 __F17HMASK(LS_MATCH_HW_PFSTRIDE, 1),
1347 __F17HMASK(LS_MATCH_HW_PFREGION, 2),
1348 NULLMASK
1349};
1350static const struct pmc_masks f17h_mask_LS_SW_PF_DCFILLS[] = {
1351 __F17HMASK(LS_SW_PF_MABRESP_LCL_L2, 0),
1352 __F17HMASK(LS_SW_PF_MABRESP_LCL_L2_CACHE, 1),
1353 __F17HMASK(LS_SW_PF_MABRESP_LCL_DRM, 3),
1354 __F17HMASK(LS_SW_PF_MABRESP_RMT_CACHE, 4),
1355 __F17HMASK(LS_SW_PF_MABRESP_RMT_DRAM, 6),
1356 NULLMASK
1357};
1358static const struct pmc_masks f17h_mask_LS_HW_PF_DCFILLS[] = {
1359 __F17HMASK(LS_HW_PF_MABRESP_LCL_L2, 0),
1360 __F17HMASK(LS_HW_PF_MABRESP_LCL_CACHE, 1),
1361 __F17HMASK(LS_HW_PF_MABRESP_LCL_DRAM, 3),
1362 __F17HMASK(LS_HW_PF_MABRESP_RMT_CACHE, 4),
1363 __F17HMASK(LS_HW_PF_MABRESP_RMT_DRAM, 6),
1364 NULLMASK
1365};
1366static const struct pmc_masks f17h_mask_LS_TW_DCFILLS[] = {
1367 __F17HMASK(LS_TW_MABRESP_LCL_L2, 0),
1368 __F17HMASK(LS_TW_MABRESP_LCL_CACHE, 1),
1369 __F17HMASK(LS_TW_MABRESP_LCL_DRAM, 3),
1370 __F17HMASK(LS_TW_MABRESP_RMT_CACHE, 4),
1371 __F17HMASK(LS_TW_MABRESP_RMT_DRAM, 6),
1372 NULLMASK
1373};
1161
1374
1375static const struct pmc_masks f17h_mask_LS_ALLOC_MAB_COUNT[] = {
1376 __F17HMASK(LS_ALLOC_MAB_COUNT, 0x0),
1377 NULLMASK
1378};
1379static const struct pmc_masks f17h_mask_LS_TW_INITLEVEL[] = {
1380 __F17HMASK(LS_TW_INITLGH_NATIVE_PDPT, 0),
1381 __F17HMASK(LS_TW_INITLGH_NATIVE_PDT, 1),
1382 __F17HMASK(LS_TW_INITLGH_NATIVE_PFT, 2),
1383 __F17HMASK(LS_TW_INITLGH_NATIVE_PG, 3),
1384 __F17HMASK(LS_TW_INITL_NESTED_PDPT, 4),
1385 __F17HMASK(LS_TW_INITL_NESTED_PDT, 5),
1386 __F17HMASK(LS_TW_INITL_NESTED_PFT, 6),
1387 __F17HMASK(LS_TW_INITL_NESTED_PG, 7),
1388 NULLMASK
1389};
1390static const struct pmc_masks f17h_mask_LS_NOT_HALTED_CYCLE[] = {
1391 __F17HMASK(LS_NOT_HALTED_CYCLE, 0x00),
1392 NULLMASK
1393};
1394static const struct pmc_masks f17h_mask_LS_TW_RETURN_TYPES[] = {
1395 __F17HMASK(LS_TWC_RET_TYPE_SPEC_VALID, 0),
1396 __F17HMASK(LS_TWC_RET_TYPE_SPEC_FAULT_NAB, 2),
1397 __F17HMASK(LS_TWC_RET_TYPE_SPEC_FAULT_AB, 3),
1398 __F17HMASK(LS_TWC_RET_TYPE_NONSPEC_VALID, 6),
1399 __F17HMASK(LS_TWC_RET_TYPE_NONSPEC_FAULT, 7),
1400 NULLMASK
1401};
1402static const struct pmc_masks f17h_mask_IC_FW32[] = {
1403 __F17HMASK(IC_FW32, 0x0),
1404 NULLMASK
1405};
1406static const struct pmc_masks f17h_mask_IC_FW32_MISS[] = {
1407 __F17HMASK(IC_FW32_MISS, 0x0),
1408 NULLMASK
1409};
1410static const struct pmc_masks f17h_mask_IC_CACHEFILL_L2[] = {
1411 __F17HMASK(IC_CACHEFILL_L2, 0x0),
1412 NULLMASK
1413};
1414static const struct pmc_masks f17h_mask_IC_CACHEFILL_SYS[] = {
1415 __F17HMASK(IC_CACHEFILL_SYS, 0x0),
1416 NULLMASK
1417};
1418static const struct pmc_masks f17h_mask_BP_L1TLBMISS_L2HIT[] = {
1419 __F17HMASK(BP_L1TLBMISS_L2HIT, 0x0),
1420 NULLMASK
1421};
1422static const struct pmc_masks f17h_mask_BP_L1TLBMISS_L2MISS[] = {
1423 __F17HMASK(BP_L1TLBMISS_L2MISS, 0x0),
1424 NULLMASK
1425};
1426static const struct pmc_masks f17h_mask_IC_FETCHSTALL[] = {
1427 __F17HMASK(IC_FETCHSTALL_BACKPRESSURE, 0),
1428 __F17HMASK(IC_FETCHSTALL_DQEMPTY, 1),
1429 __F17HMASK(IC_FETCHSTALL_ANY, 2),
1430 NULLMASK
1431};
1432static const struct pmc_masks f17h_mask_BP_L1_BTBCORRECT[] = {
1433 __F17HMASK(BP_L1_BTBCORRECT, 0x0),
1434 NULLMASK
1435};
1436static const struct pmc_masks f17h_mask_BP_L2_BTBCORRECT[] = {
1437 __F17HMASK(BP_L2_BTBCORRECT, 0x0),
1438 NULLMASK
1439};
1440static const struct pmc_masks f17h_mask_IC_CACHEINVAL[] = {
1441 __F17HMASK(IC_CACHEINVAL_FILLINV, 0),
1442 __F17HMASK(IC_CACHEINVAL_L2_INV_PROVBE, 1),
1443 NULLMASK
1444};
1445static const struct pmc_masks f17h_mask_BP_TLB_REL[] = {
1446 __F17HMASK(BP_TLB_REL, 0x0),
1447 NULLMASK
1448};
1449static const struct pmc_masks f17h_mask_ICOC_MODE_SWITCH[] = {
1450 __F17HMASK(IC2OC_MODE_SWITCH, 0),
1451 __F17HMASK(OC2IC_MODE_SWITCH, 1),
1452 NULLMASK
1453};
1454static const struct pmc_masks f17h_mask_DE_DISPATCH_TOKEN_STALLS[] = {
1455 __F17HMASK(DE_ALSQ1_TOKEN_STALL, 0),
1456 __F17HMASK(DE_ALSQ2_TOKEN_STALL, 1),
1457 __F17HMASK(DE_ALSQ3_TOKEN_STALL, 2),
1458 __F17HMASK(DE_ALSQ3_0_TOKEN_STALL, 3),
1459 __F17HMASK(DE_ALU_TOKEN_STALL, 4),
1460 __F17HMASK(DE_AGSQ_TOKEN_STALL, 5),
1461 __F17HMASK(DE_RETIRE_TOKEN_STALLS, 6),
1462 NULLMASK
1463};
1464static const struct pmc_masks f17h_mask_EX_RET_INST[] = {
1465 __F17HMASK(EX_RET_INST, 0x0),
1466 NULLMASK
1467};
1468static const struct pmc_masks f17h_mask_EX_RET_COPS[] = {
1469 __F17HMASK(EX_RET_COPS, 0x0),
1470 NULLMASK
1471};
1472static const struct pmc_masks f17h_mask_EX_RET_BRN[] = {
1473 __F17HMASK(EX_RET_BRN, 0x0),
1474 NULLMASK
1475};
1476static const struct pmc_masks f17h_mask_EX_RET_BRN_MISP[] = {
1477 __F17HMASK(EX_RET_BRN_MISP, 0x0),
1478 NULLMASK
1479};
1480static const struct pmc_masks f17h_mask_EX_RET_BRN_TKN[] = {
1481 __F17HMASK(EX_RET_BRN_TKN, 0x0),
1482 NULLMASK
1483};
1484static const struct pmc_masks f17h_mask_EX_RET_BRN_TKN_MISP[] = {
1485 __F17HMASK(EX_RET_BRN_TKN_MISP, 0x0),
1486 NULLMASK
1487};
1488static const struct pmc_masks f17h_mask_EX_RET_BRN_FAR[] = {
1489 __F17HMASK(EX_RET_BRN_FAR, 0x0),
1490 NULLMASK
1491};
1492static const struct pmc_masks f17h_mask_EX_RET_BRN_RESYNC[] = {
1493 __F17HMASK(EX_RET_BRN_RESYNC, 0x0),
1494 NULLMASK
1495};
1496static const struct pmc_masks f17h_mask_EX_RET_BRN_NEAR_RET[] = {
1497 __F17HMASK(EX_RET_BRN_NEAR_RET, 0x0),
1498 NULLMASK
1499};
1500static const struct pmc_masks f17h_mask_EX_RET_BRN_NEAR_RET_MISPRED[] = {
1501 __F17HMASK(EX_RET_BRN_NEAR_RET_MISPRED, 0x0),
1502 NULLMASK
1503};
1504static const struct pmc_masks f17h_mask_EX_RET_BRN_IND_MISP[] = {
1505 __F17HMASK(EX_RET_BRN_IND_MISP, 0x0),
1506 NULLMASK
1507};
1508static const struct pmc_masks f17h_mask_EX_RET_MMX_FP_INSTR[] = {
1509 __F17HMASK(EX_RET_MMX_X87_INST, 0),
1510 __F17HMASK(EX_RET_MMX_INSTR, 1),
1511 __F17HMASK(EX_RET_MMX_SSE_INSTR, 2),
1512 NULLMASK
1513};
1514static const struct pmc_masks f17h_mask_EX_RET_COND_BRN[] = {
1515 __F17HMASK(EX_RET_COND_BRN, 0x0),
1516 NULLMASK
1517};
1518static const struct pmc_masks f17h_mask_EX_DIV_BUSY[] = {
1519 __F17HMASK(EX_DIV_BUSY, 0x0),
1520 NULLMASK
1521};
1522static const struct pmc_masks f17h_mask_EX_DIV_COUNT[] = {
1523 __F17HMASK(EX_DIV_COUNT, 0x0),
1524 NULLMASK
1525};
1526static const struct pmc_masks f17h_mask_L2_REQUEST_G1[] = {
1527 __F17HMASK(L2_REQUEST_G1_OTHERREQ, 0),
1528 __F17HMASK(L2_REQUEST_G1_HWPF, 1),
1529 __F17HMASK(L2_REQUEST_G1_PREFETCHL2, 2),
1530 __F17HMASK(L2_REQUEST_G1_CHANGETOX, 3),
1531 __F17HMASK(L2_REQUEST_G1_CACHEABLEICRD, 4),
1532 __F17HMASK(L2_REQUEST_G1_LSRDBLKC, 5),
1533 __F17HMASK(L2_REQUEST_G1_RDBLKX, 6),
1534 __F17HMASK(L2_REQUEST_G1_RDBLKL, 7),
1535 NULLMASK
1536};
1537static const struct pmc_masks f17h_mask_L2_REQUEST_G2[] = {
1538 __F17HMASK(L2_REQUEST_G2_BUSLOCKRESP, 0),
1539 __F17HMASK(L2_REQUEST_G2_BUSLOCKORIG, 1),
1540 __F17HMASK(L2_REQUEST_G2_SMCINV, 2),
1541 __F17HMASK(L2_REQUEST_G2_ICRDSIZENC, 3),
1542 __F17HMASK(L2_REQUEST_G2_ICRDSIZE, 4),
1543 __F17HMASK(L2_REQUEST_G2_LSRDSIZENC, 5),
1544 __F17HMASK(L2_REQUEST_G2_LSRDSIZE, 6),
1545 __F17HMASK(L2_REQUEST_G2_GROUP1, 7),
1546 NULLMASK
1547};
1548static const struct pmc_masks f17h_mask_L2_LATENCY[] = {
1549 __F17HMASK(L2_LATENCY_CYC_WAITINGONFILLS, 0x0),
1550 NULLMASK
1551};
1552static const struct pmc_masks f17h_mask_L2_WBCREQ[] = {
1553 __F17HMASK(L2_WBCREQ_CLZERO, 0),
1554 __F17HMASK(L2_WBCREQ_LOCALICCLR, 1),
1555 __F17HMASK(L2_WBCREQ_ZEROBYTESTORE, 2),
1556 __F17HMASK(L2_WBCREQ_ILINEFLUSH, 3),
1557 __F17HMASK(L2_WBCREQ_CACHELINEFLUSH, 4),
1558 __F17HMASK(L2_WBCREQ_WBCCLOSE, 5),
1559 __F17HMASK(L2_WBCREQ_WCBWRITE, 6),
1560 NULLMASK
1561};
1562static const struct pmc_masks f17h_mask_L2_CACHEREQSTAT[] = {
1563 __F17HMASK(L2_CACHEREQSTAT_ICFILLMISS, 0),
1564 __F17HMASK(L2_CACHEREQSTAT_ICFILLHITS, 1),
1565 __F17HMASK(L2_CACHEREQSTAT_ICFILLHITX, 2),
1566 __F17HMASK(L2_CACHEREQSTAT_LSRDBLKC, 3),
1567 __F17HMASK(L2_CACHEREQSTAT_LSRDBLKX, 4),
1568 __F17HMASK(L2_CACHEREQSTAT_LSRDBLKLHITS, 5),
1569 __F17HMASK(L2_CACHEREQSTAT_LSRDBLKLHITX, 6),
1570 __F17HMASK(L2_CACHEREQSTAT_LSRDBLKCS, 7),
1571 NULLMASK
1572};
1573static const struct pmc_masks f17h_mask_L2_SMCEVENTS[] = {
1574 __F17HMASK(L2_SMCEVENTS_ICFILLSTQCAMMATOT, 0),
1575 __F17HMASK(L2_SMCEVENTS_ICFILLSTQCAMMATTT, 1),
1576 __F17HMASK(L2_SMCEVENTS_LSRDBLKLSXCHGTOX, 2),
1577 __F17HMASK(L2_SMCEVENTS_RDBLKXCHGTOX, 3),
1578 __F17HMASK(L2_SMCEVENTS_LSRDBLKLSCHITL2ICVAL, 4),
1579 __F17HMASK(L2_SMCEVENTS_ICFETCHHITL2, 5),
1580 __F17HMASK(L2_SMCEVENTS_ICFETCHHITL2DCVAL, 6),
1581 NULLMASK
1582};
1583static const struct pmc_masks f17h_mask_L2_FILLPENDING[] = {
1584 __F17HMASK(L2_FILLPENDING_L2FILLBUSY, 0),
1585 NULLMASK
1586};
1587static const struct pmc_masks f17h_mask_EX_TAGGED_IBSOPS[] = {
1588 __F17HMASK(EX_TAGGED_IBSOPS, 0x0),
1589 __F17HMASK(EX_TAGGED_IBSOPS_RET, 0x1),
1590 __F17HMASK(EX_TAGGED_IBSOPS_CNT_RLOVER, 0x2),
1591 NULLMASK
1592};
1593static const struct pmc_masks f17h_mask_EX_RET_FUSED_BRNCH_INST[] = {
1594 __F17HMASK(EX_RET_FUSED_BRNCH_INST, 0x0),
1595 NULLMASK
1596};
1597
1598#define F17H_KW_COUNT "count"
1599#define F17H_KW_EDGE "edge"
1600#define F17H_KW_INV "inv"
1601#define F17H_KW_MASK "mask"
1602#define F17H_KW_OS "os"
1603#define F17H_KW_USR "usr"
1604
1605static int
1606f17h_allocate_pmc(enum pmc_event pe, char *ctrspec,
1607 struct pmc_op_pmcallocate *pmc_config)
1608{
1609 char *e, *p, *q;
1610 int n;
1611 uint32_t count;
1612 const struct pmc_masks *pmask;
1613 uint64_t evmask = 0;
1614 (void)ctrspec;
1615
1616 pmc_config->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE);
1617 pmc_config->pm_md.pm_amd.pm_amd_config = 0;
1618
1619
1620#define __F17HSETMASK(M) pmask = f17h_mask_##M
1621 switch (pe) {
1622 case PMC_EV_F17H_FPU_PIPEASSIGMENT:
1623 __F17HSETMASK(FPU_PIPEASSIGMENT);
1624 break;
1625 case PMC_EV_F17H_FP_SCHED_EMPTY:
1626 __F17HSETMASK(FP_SCHED_EMPTY);
1627 break;
1628 case PMC_EV_F17H_FP_RET_X87_FPOPS:
1629 __F17HSETMASK(FP_RET_X87_FPOPS);
1630 break;
1631 case PMC_EV_F17H_FP_RET_SSEAVX_OPS:
1632 __F17HSETMASK(FP_RET_SSEAVX_OPS);
1633 break;
1634 case PMC_EV_F17H_FP_NUM_MOVELIM_SCAL_OPT:
1635 __F17HSETMASK(FP_NUM_MOVELIM_SCAL_OPT);
1636 break;
1637 case PMC_EV_F17H_FP_RET_SEROPS:
1638 __F17HSETMASK(FP_RET_SEROPS);
1639 break;
1640 case PMC_EV_F17H_LS_BAD_STATUS2:
1641 __F17HSETMASK(LS_BAD_STATUS2);
1642 break;
1643 case PMC_EV_F17H_LS_LOCKS:
1644 __F17HSETMASK(LS_LOCKS);
1645 break;
1646 case PMC_EV_F17H_LS_RET_CLFLUSH_INST:
1647 __F17HSETMASK(LS_RET_CLFLUSH_INST);
1648 break;
1649 case PMC_EV_F17H_LS_RET_CPUID_INST:
1650 __F17HSETMASK(LS_RET_CPUID_INST);
1651 break;
1652 case PMC_EV_F17H_LS_DISPATCH:
1653 __F17HSETMASK(LS_DISPATCH);
1654 break;
1655 case PMC_EV_F17H_LS_SMI_RX:
1656 __F17HSETMASK(LS_SMI_RX);
1657 break;
1658 case PMC_EV_F17H_LS_STLF:
1659 __F17HSETMASK(LS_STLF);
1660 break;
1661 case PMC_EV_F17H_LS_STLF_COMMITCANCEL:
1662 __F17HSETMASK(LS_STLF_COMMITCANCEL);
1663 break;
1664 case PMC_EV_F17H_LS_DC_ACCESS:
1665 __F17HSETMASK(LS_DC_ACCESS);
1666 break;
1667 case PMC_EV_F17H_LS_MAB_ALLOCPIPE:
1668 __F17HSETMASK(LS_MAB_ALLOCPIPE);
1669 break;
1670 case PMC_EV_F17H_LS_REFFILS_FROM_SYS:
1671 __F17HSETMASK(LS_REFFILS_FROM_SYS);
1672 break;
1673 case PMC_EV_F17H_LS_L1_DTLBMISS:
1674 __F17HSETMASK(LS_L1_DTLBMISS);
1675 break;
1676 case PMC_EV_F17H_LS_TABLEWALKER:
1677 __F17HSETMASK(LS_TABLEWALKER);
1678 break;
1679 case PMC_EV_F17H_LS_MISAL_ACCESS:
1680 __F17HSETMASK(LS_MISAL_ACCESS);
1681 break;
1682 case PMC_EV_F17H_LS_PREF_INST_DISPATCH:
1683 __F17HSETMASK(LS_PREF_INST_DISPATCH);
1684 break;
1685 case PMC_EV_F17H_LS_HWPF_ALLOCATED:
1686 __F17HSETMASK(LS_HWPF_ALLOCATED);
1687 break;
1688 case PMC_EV_F17H_LS_HWPF_HIT:
1689 __F17HSETMASK(LS_HWPF_HIT);
1690 break;
1691 case PMC_EV_F17H_LS_TW_INPROG_DSIDE:
1692 __F17HSETMASK(LS_TW_INPROG_DSIDE);
1693 break;
1694 case PMC_EV_F17H_LS_INEF_SW_PREF:
1695 __F17HSETMASK(LS_INEF_SW_PREF);
1696 break;
1697 case PMC_EV_F17H_LS_MAB_MCH_CNT:
1698 __F17HSETMASK(LS_MAB_MCH_CNT);
1699 break;
1700 case PMC_EV_F17H_LS_HW_PF_MABALLOC:
1701 __F17HSETMASK(LS_HW_PF_MABALLOC);
1702 break;
1703 case PMC_EV_F17H_LS_HW_PF_MATCH:
1704 __F17HSETMASK(LS_HW_PF_MATCH);
1705 break;
1706 case PMC_EV_F17H_LS_SW_PF_DCFILLS:
1707 __F17HSETMASK(LS_SW_PF_DCFILLS);
1708 break;
1709 case PMC_EV_F17H_LS_HW_PF_DCFILLS:
1710 __F17HSETMASK(LS_HW_PF_DCFILLS);
1711 break;
1712 case PMC_EV_F17H_LS_TW_DCFILLS:
1713 __F17HSETMASK(LS_TW_DCFILLS);
1714 break;
1715 case PMC_EV_F17H_LS_ALLOC_MAB_COUNT:
1716 __F17HSETMASK(LS_ALLOC_MAB_COUNT);
1717 break;
1718 case PMC_EV_F17H_LS_TW_INITLEVEL:
1719 __F17HSETMASK(LS_TW_INITLEVEL);
1720 break;
1721 case PMC_EV_F17H_LS_NOT_HALTED_CYCLE:
1722 __F17HSETMASK(LS_NOT_HALTED_CYCLE);
1723 break;
1724 case PMC_EV_F17H_LS_TW_RETURN_TYPES:
1725 __F17HSETMASK(LS_TW_RETURN_TYPES);
1726 break;
1727 case PMC_EV_F17H_IC_FW32:
1728 __F17HSETMASK(IC_FW32);
1729 break;
1730 case PMC_EV_F17H_IC_FW32_MISS:
1731 __F17HSETMASK(IC_FW32_MISS);
1732 break;
1733 case PMC_EV_F17H_IC_CACHEFILL_L2:
1734 __F17HSETMASK(IC_CACHEFILL_L2);
1735 break;
1736 case PMC_EV_F17H_IC_CACHEFILL_SYS:
1737 __F17HSETMASK(IC_CACHEFILL_SYS);
1738 break;
1739 case PMC_EV_F17H_BP_L1TLBMISS_L2HIT:
1740 __F17HSETMASK(BP_L1TLBMISS_L2HIT);
1741 break;
1742 case PMC_EV_F17H_BP_L1TLBMISS_L2MISS:
1743 __F17HSETMASK(BP_L1TLBMISS_L2MISS);
1744 break;
1745 case PMC_EV_F17H_IC_FETCHSTALL:
1746 __F17HSETMASK(IC_FETCHSTALL);
1747 break;
1748 case PMC_EV_F17H_BP_L1_BTBCORRECT:
1749 __F17HSETMASK(BP_L1_BTBCORRECT);
1750 break;
1751 case PMC_EV_F17H_BP_L2_BTBCORRECT:
1752 __F17HSETMASK(BP_L2_BTBCORRECT);
1753 break;
1754 case PMC_EV_F17H_IC_CACHEINVAL:
1755 __F17HSETMASK(IC_CACHEINVAL);
1756 break;
1757 case PMC_EV_F17H_BP_TLB_REL:
1758 __F17HSETMASK(BP_TLB_REL);
1759 break;
1760 case PMC_EV_F17H_ICOC_MODE_SWITCH:
1761 __F17HSETMASK(ICOC_MODE_SWITCH);
1762 break;
1763 case PMC_EV_F17H_DE_DISPATCH_TOKEN_STALLS:
1764 __F17HSETMASK(DE_DISPATCH_TOKEN_STALLS);
1765 break;
1766 case PMC_EV_F17H_EX_RET_INST:
1767 __F17HSETMASK(EX_RET_INST);
1768 break;
1769 case PMC_EV_F17H_EX_RET_COPS:
1770 __F17HSETMASK(EX_RET_COPS);
1771 break;
1772 case PMC_EV_F17H_EX_RET_BRN:
1773 __F17HSETMASK(EX_RET_BRN);
1774 break;
1775 case PMC_EV_F17H_EX_RET_BRN_MISP:
1776 __F17HSETMASK(EX_RET_BRN_MISP);
1777 break;
1778 case PMC_EV_F17H_EX_RET_BRN_TKN:
1779 __F17HSETMASK(EX_RET_BRN_TKN);
1780 break;
1781 case PMC_EV_F17H_EX_RET_BRN_TKN_MISP:
1782 __F17HSETMASK(EX_RET_BRN_TKN_MISP);
1783 break;
1784 case PMC_EV_F17H_EX_RET_BRN_FAR:
1785 __F17HSETMASK(EX_RET_BRN_FAR);
1786 break;
1787 case PMC_EV_F17H_EX_RET_BRN_RESYNC:
1788 __F17HSETMASK(EX_RET_BRN_RESYNC);
1789 break;
1790 case PMC_EV_F17H_EX_RET_BRN_NEAR_RET:
1791 __F17HSETMASK(EX_RET_BRN_NEAR_RET);
1792 break;
1793 case PMC_EV_F17H_EX_RET_BRN_NEAR_RET_MISPRED:
1794 __F17HSETMASK(EX_RET_BRN_NEAR_RET_MISPRED);
1795 break;
1796 case PMC_EV_F17H_EX_RET_BRN_IND_MISP:
1797 __F17HSETMASK(EX_RET_BRN_IND_MISP);
1798 break;
1799 case PMC_EV_F17H_EX_RET_MMX_FP_INSTR:
1800 __F17HSETMASK(EX_RET_MMX_FP_INSTR);
1801 break;
1802 case PMC_EV_F17H_EX_RET_COND_BRN:
1803 __F17HSETMASK(EX_RET_COND_BRN);
1804 break;
1805 case PMC_EV_F17H_EX_DIV_BUSY:
1806 __F17HSETMASK(EX_DIV_BUSY);
1807 break;
1808 case PMC_EV_F17H_EX_DIV_COUNT:
1809 __F17HSETMASK(EX_DIV_COUNT);
1810 break;
1811 case PMC_EV_F17H_L2_REQUEST_G1:
1812 __F17HSETMASK(L2_REQUEST_G1);
1813 break;
1814 case PMC_EV_F17H_L2_REQUEST_G2:
1815 __F17HSETMASK(L2_REQUEST_G2);
1816 break;
1817 case PMC_EV_F17H_L2_LATENCY:
1818 __F17HSETMASK(L2_LATENCY);
1819 break;
1820 case PMC_EV_F17H_L2_WBCREQ:
1821 __F17HSETMASK(L2_WBCREQ);
1822 break;
1823 case PMC_EV_F17H_L2_CACHEREQSTAT:
1824 __F17HSETMASK(L2_CACHEREQSTAT);
1825 break;
1826 case PMC_EV_F17H_L2_SMCEVENTS:
1827 __F17HSETMASK(L2_SMCEVENTS);
1828 break;
1829 case PMC_EV_F17H_L2_FILLPENDING:
1830 __F17HSETMASK(L2_FILLPENDING);
1831 break;
1832 case PMC_EV_F17H_EX_TAGGED_IBSOPS:
1833 __F17HSETMASK(EX_TAGGED_IBSOPS);
1834 break;
1835 case PMC_EV_F17H_EX_RET_FUSED_BRNCH_INST:
1836 __F17HSETMASK(EX_RET_FUSED_BRNCH_INST);
1837 break;
1838 default:
1839 printf(" %s failed, event not supported\n", __FUNCTION__);
1840 return -1;
1841 }
1842 while ((p = strsep(&ctrspec, ",")) != NULL) {
1843 if (KWPREFIXMATCH(p, F17H_KW_COUNT "=")) {
1844 q = strchr(p, '=');
1845 if (*++q == '\0') /* skip '=' */
1846 return (-1);
1847
1848 count = strtol(q, &e, 0);
1849 if (e == q || *e != '\0')
1850 return (-1);
1851
1852 pmc_config->pm_caps |= PMC_CAP_THRESHOLD;
1853 pmc_config->pm_md.pm_amd.pm_amd_config |=
1854 AMD_PMC_TO_COUNTER(count);
1855
1856 } else if (KWMATCH(p, F17H_KW_EDGE)) {
1857 pmc_config->pm_caps |= PMC_CAP_EDGE;
1858 } else if (KWMATCH(p, F17H_KW_INV)) {
1859 pmc_config->pm_caps |= PMC_CAP_INVERT;
1860 } else if (KWPREFIXMATCH(p, F17H_KW_MASK "=")) {
1861 if ((n = pmc_parse_mask(pmask, p, &evmask)) < 0)
1862 return (-1);
1863 pmc_config->pm_caps |= PMC_CAP_QUALIFIER;
1864 } else if (KWMATCH(p, F17H_KW_OS)) {
1865 pmc_config->pm_caps |= PMC_CAP_SYSTEM;
1866 } else if (KWMATCH(p, F17H_KW_USR)) {
1867 pmc_config->pm_caps |= PMC_CAP_USER;
1868 } else
1869 return (-1);
1870}
1871 if (pmc_config->pm_caps & PMC_CAP_QUALIFIER) {
1872 pmc_config->pm_md.pm_amd.pm_amd_config =
1873 AMD_PMC_TO_UNITMASK(evmask);
1874 }
1875 return 0;
1876}
1162/*
1163 * AMD K8 PMCs.
1164 *
1165 * These are very similar to AMD K7 PMCs, but support more kinds of
1166 * events.
1167 */
1168
1169static struct pmc_event_alias k8_aliases[] = {

--- 1917 unchanged lines hidden (view full) ---

3087 case PMC_CLASS_K7:
3088 ev = k7_event_table;
3089 count = PMC_EVENT_TABLE_SIZE(k7);
3090 break;
3091 case PMC_CLASS_K8:
3092 ev = k8_event_table;
3093 count = PMC_EVENT_TABLE_SIZE(k8);
3094 break;
1877/*
1878 * AMD K8 PMCs.
1879 *
1880 * These are very similar to AMD K7 PMCs, but support more kinds of
1881 * events.
1882 */
1883
1884static struct pmc_event_alias k8_aliases[] = {

--- 1917 unchanged lines hidden (view full) ---

3802 case PMC_CLASS_K7:
3803 ev = k7_event_table;
3804 count = PMC_EVENT_TABLE_SIZE(k7);
3805 break;
3806 case PMC_CLASS_K8:
3807 ev = k8_event_table;
3808 count = PMC_EVENT_TABLE_SIZE(k8);
3809 break;
3810 case PMC_CLASS_F17H:
3811 ev = f17h_event_table;
3812 count = PMC_EVENT_TABLE_SIZE(f17h);
3813 break;
3095 case PMC_CLASS_P4:
3096 ev = p4_event_table;
3097 count = PMC_EVENT_TABLE_SIZE(p4);
3098 break;
3099 case PMC_CLASS_P5:
3100 ev = p5_event_table;
3101 count = PMC_EVENT_TABLE_SIZE(p5);
3102 break;

--- 252 unchanged lines hidden (view full) ---

3355 pmc_class_table[n] = &p6_class_table_descr;
3356 break;
3357#endif
3358#if defined(__amd64__) || defined(__i386__)
3359 case PMC_CPU_AMD_K8:
3360 PMC_MDEP_INIT(k8);
3361 pmc_class_table[n] = &k8_class_table_descr;
3362 break;
3814 case PMC_CLASS_P4:
3815 ev = p4_event_table;
3816 count = PMC_EVENT_TABLE_SIZE(p4);
3817 break;
3818 case PMC_CLASS_P5:
3819 ev = p5_event_table;
3820 count = PMC_EVENT_TABLE_SIZE(p5);
3821 break;

--- 252 unchanged lines hidden (view full) ---

4074 pmc_class_table[n] = &p6_class_table_descr;
4075 break;
4076#endif
4077#if defined(__amd64__) || defined(__i386__)
4078 case PMC_CPU_AMD_K8:
4079 PMC_MDEP_INIT(k8);
4080 pmc_class_table[n] = &k8_class_table_descr;
4081 break;
4082 case PMC_CPU_AMD_F17H:
4083 PMC_MDEP_INIT(f17h);
4084 pmc_class_table[n] = &f17h_class_table_descr;
4085 break;
3363 case PMC_CPU_INTEL_ATOM:
3364 PMC_MDEP_INIT_INTEL_V2(atom);
3365 break;
3366 case PMC_CPU_INTEL_ATOM_SILVERMONT:
3367 PMC_MDEP_INIT_INTEL_V2(atom_silvermont);
3368 break;
3369 case PMC_CPU_INTEL_CORE:
3370 PMC_MDEP_INIT(core);

--- 299 unchanged lines hidden (view full) ---

3670 break;
3671 }
3672 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
3673 ev = k7_event_table;
3674 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
3675 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
3676 ev = k8_event_table;
3677 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
4086 case PMC_CPU_INTEL_ATOM:
4087 PMC_MDEP_INIT_INTEL_V2(atom);
4088 break;
4089 case PMC_CPU_INTEL_ATOM_SILVERMONT:
4090 PMC_MDEP_INIT_INTEL_V2(atom_silvermont);
4091 break;
4092 case PMC_CPU_INTEL_CORE:
4093 PMC_MDEP_INIT(core);

--- 299 unchanged lines hidden (view full) ---

4393 break;
4394 }
4395 } else if (pe >= PMC_EV_K7_FIRST && pe <= PMC_EV_K7_LAST) {
4396 ev = k7_event_table;
4397 evfence = k7_event_table + PMC_EVENT_TABLE_SIZE(k7);
4398 } else if (pe >= PMC_EV_K8_FIRST && pe <= PMC_EV_K8_LAST) {
4399 ev = k8_event_table;
4400 evfence = k8_event_table + PMC_EVENT_TABLE_SIZE(k8);
4401 } else if ((int)pe >= PMC_EV_F17H_FIRST &&
4402 (int)pe <= PMC_EV_F17H_LAST) {
4403 ev = f17h_event_table;
4404 evfence = f17h_event_table + PMC_EVENT_TABLE_SIZE(f17h);
3678 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
3679 ev = p4_event_table;
3680 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
3681 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
3682 ev = p5_event_table;
3683 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
3684 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
3685 ev = p6_event_table;

--- 258 unchanged lines hidden --- 		4405 } else if (pe >= PMC_EV_P4_FIRST && pe <= PMC_EV_P4_LAST) {
4406 ev = p4_event_table;
4407 evfence = p4_event_table + PMC_EVENT_TABLE_SIZE(p4);
4408 } else if (pe >= PMC_EV_P5_FIRST && pe <= PMC_EV_P5_LAST) {
4409 ev = p5_event_table;
4410 evfence = p5_event_table + PMC_EVENT_TABLE_SIZE(p5);
4411 } else if (pe >= PMC_EV_P6_FIRST && pe <= PMC_EV_P6_LAST) {
4412 ev = p6_event_table;

--- 258 unchanged lines hidden ---