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libpmc.c (289317) libpmc.c (291494)
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2003-2008 Joseph Koshy
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 11 unchanged lines hidden (view full) ---

20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 289317 2015-10-14 16:56:25Z bz $");
28__FBSDID("$FreeBSD: head/lib/libpmc/libpmc.c 291494 2015-11-30 17:35:49Z rrs $");
29
30#include <sys/types.h>
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/pmc.h>
34#include <sys/syscall.h>
35
36#include <ctype.h>

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212 __PMC_EV_ALIAS_HASWELL()
213};
214
215static const struct pmc_event_descr haswell_xeon_event_table[] =
216{
217 __PMC_EV_ALIAS_HASWELL_XEON()
218};
219
29
30#include <sys/types.h>
31#include <sys/param.h>
32#include <sys/module.h>
33#include <sys/pmc.h>
34#include <sys/syscall.h>
35
36#include <ctype.h>

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212 __PMC_EV_ALIAS_HASWELL()
213};
214
215static const struct pmc_event_descr haswell_xeon_event_table[] =
216{
217 __PMC_EV_ALIAS_HASWELL_XEON()
218};
219
220static const struct pmc_event_descr broadwell_event_table[] =
221{
222 __PMC_EV_ALIAS_BROADWELL()
223};
220
224
225static const struct pmc_event_descr broadwell_xeon_event_table[] =
226{
227 __PMC_EV_ALIAS_BROADWELL_XEON()
228};
229
230static const struct pmc_event_descr skylake_event_table[] =
231{
232 __PMC_EV_ALIAS_SKYLAKE()
233};
234
221static const struct pmc_event_descr ivybridge_event_table[] =
222{
223 __PMC_EV_ALIAS_IVYBRIDGE()
224};
225
226static const struct pmc_event_descr ivybridge_xeon_event_table[] =
227{
228 __PMC_EV_ALIAS_IVYBRIDGE_XEON()

--- 24 unchanged lines hidden (view full) ---

253 __PMC_EV_ALIAS_COREI7UC()
254};
255
256static const struct pmc_event_descr haswelluc_event_table[] =
257{
258 __PMC_EV_ALIAS_HASWELLUC()
259};
260
235static const struct pmc_event_descr ivybridge_event_table[] =
236{
237 __PMC_EV_ALIAS_IVYBRIDGE()
238};
239
240static const struct pmc_event_descr ivybridge_xeon_event_table[] =
241{
242 __PMC_EV_ALIAS_IVYBRIDGE_XEON()

--- 24 unchanged lines hidden (view full) ---

267 __PMC_EV_ALIAS_COREI7UC()
268};
269
270static const struct pmc_event_descr haswelluc_event_table[] =
271{
272 __PMC_EV_ALIAS_HASWELLUC()
273};
274
275static const struct pmc_event_descr broadwelluc_event_table[] =
276{
277 __PMC_EV_ALIAS_BROADWELLUC()
278};
279
261static const struct pmc_event_descr sandybridgeuc_event_table[] =
262{
263 __PMC_EV_ALIAS_SANDYBRIDGEUC()
264};
265
266static const struct pmc_event_descr westmereuc_event_table[] =
267{
268 __PMC_EV_ALIAS_WESTMEREUC()

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301PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
302PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
303PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
304PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
305PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
306PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
307PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
308PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
280static const struct pmc_event_descr sandybridgeuc_event_table[] =
281{
282 __PMC_EV_ALIAS_SANDYBRIDGEUC()
283};
284
285static const struct pmc_event_descr westmereuc_event_table[] =
286{
287 __PMC_EV_ALIAS_WESTMEREUC()

--- 32 unchanged lines hidden (view full) ---

320PMC_MDEP_TABLE(atom, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
321PMC_MDEP_TABLE(atom_silvermont, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
322PMC_MDEP_TABLE(core, IAP, PMC_CLASS_SOFT, PMC_CLASS_TSC);
323PMC_MDEP_TABLE(core2, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
324PMC_MDEP_TABLE(corei7, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
325PMC_MDEP_TABLE(nehalem_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
326PMC_MDEP_TABLE(haswell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
327PMC_MDEP_TABLE(haswell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
328PMC_MDEP_TABLE(broadwell, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
329PMC_MDEP_TABLE(broadwell_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
330PMC_MDEP_TABLE(skylake, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
309PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
310PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
311PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
312PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
313PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
314PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
315PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
316PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);

--- 36 unchanged lines hidden (view full) ---

353PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
354PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
355PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
356PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
357PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
358PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
359PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
360PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
331PMC_MDEP_TABLE(ivybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
332PMC_MDEP_TABLE(ivybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
333PMC_MDEP_TABLE(sandybridge, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
334PMC_MDEP_TABLE(sandybridge_xeon, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
335PMC_MDEP_TABLE(westmere, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC, PMC_CLASS_UCF, PMC_CLASS_UCP);
336PMC_MDEP_TABLE(westmere_ex, IAP, PMC_CLASS_SOFT, PMC_CLASS_IAF, PMC_CLASS_TSC);
337PMC_MDEP_TABLE(k7, K7, PMC_CLASS_SOFT, PMC_CLASS_TSC);
338PMC_MDEP_TABLE(k8, K8, PMC_CLASS_SOFT, PMC_CLASS_TSC);

--- 36 unchanged lines hidden (view full) ---

375PMC_CLASS_TABLE_DESC(atom, IAP, atom, iap);
376PMC_CLASS_TABLE_DESC(atom_silvermont, IAP, atom_silvermont, iap);
377PMC_CLASS_TABLE_DESC(core, IAP, core, iap);
378PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
379PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
380PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
381PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
382PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
383PMC_CLASS_TABLE_DESC(broadwell, IAP, broadwell, iap);
384PMC_CLASS_TABLE_DESC(broadwell_xeon, IAP, broadwell_xeon, iap);
385PMC_CLASS_TABLE_DESC(skylake, IAP, skylake, iap);
361PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
362PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
363PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
364PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
365PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
366PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
367PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
368PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
369PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
386PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
387PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
388PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
389PMC_CLASS_TABLE_DESC(sandybridge_xeon, IAP, sandybridge_xeon, iap);
390PMC_CLASS_TABLE_DESC(westmere, IAP, westmere, iap);
391PMC_CLASS_TABLE_DESC(westmere_ex, IAP, westmere_ex, iap);
392PMC_CLASS_TABLE_DESC(ucf, UCF, ucf, ucf);
393PMC_CLASS_TABLE_DESC(corei7uc, UCP, corei7uc, ucp);
394PMC_CLASS_TABLE_DESC(haswelluc, UCP, haswelluc, ucp);
395PMC_CLASS_TABLE_DESC(broadwelluc, UCP, broadwelluc, ucp);
370PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
371PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
372#endif
373#if defined(__i386__)
374PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
375#endif
376#if defined(__i386__) || defined(__amd64__)
377PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);

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684#define corei7_aliases core2_aliases
685#define corei7_aliases_without_iaf core2_aliases_without_iaf
686#define nehalem_ex_aliases core2_aliases
687#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf
688#define haswell_aliases core2_aliases
689#define haswell_aliases_without_iaf core2_aliases_without_iaf
690#define haswell_xeon_aliases core2_aliases
691#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf
396PMC_CLASS_TABLE_DESC(sandybridgeuc, UCP, sandybridgeuc, ucp);
397PMC_CLASS_TABLE_DESC(westmereuc, UCP, westmereuc, ucp);
398#endif
399#if defined(__i386__)
400PMC_CLASS_TABLE_DESC(k7, K7, k7, k7);
401#endif
402#if defined(__i386__) || defined(__amd64__)
403PMC_CLASS_TABLE_DESC(k8, K8, k8, k8);

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710#define corei7_aliases core2_aliases
711#define corei7_aliases_without_iaf core2_aliases_without_iaf
712#define nehalem_ex_aliases core2_aliases
713#define nehalem_ex_aliases_without_iaf core2_aliases_without_iaf
714#define haswell_aliases core2_aliases
715#define haswell_aliases_without_iaf core2_aliases_without_iaf
716#define haswell_xeon_aliases core2_aliases
717#define haswell_xeon_aliases_without_iaf core2_aliases_without_iaf
718#define broadwell_aliases core2_aliases
719#define broadwell_aliases_without_iaf core2_aliases_without_iaf
720#define broadwell_xeon_aliases core2_aliases
721#define broadwell_xeon_aliases_without_iaf core2_aliases_without_iaf
722#define skylake_aliases core2_aliases
723#define skylake_aliases_without_iaf core2_aliases_without_iaf
692#define ivybridge_aliases core2_aliases
693#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
694#define ivybridge_xeon_aliases core2_aliases
695#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
696#define sandybridge_aliases core2_aliases
697#define sandybridge_aliases_without_iaf core2_aliases_without_iaf
698#define sandybridge_xeon_aliases core2_aliases
699#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf

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844 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
845 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
846 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
847 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
848 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
849 NULLMASK
850};
851
724#define ivybridge_aliases core2_aliases
725#define ivybridge_aliases_without_iaf core2_aliases_without_iaf
726#define ivybridge_xeon_aliases core2_aliases
727#define ivybridge_xeon_aliases_without_iaf core2_aliases_without_iaf
728#define sandybridge_aliases core2_aliases
729#define sandybridge_aliases_without_iaf core2_aliases_without_iaf
730#define sandybridge_xeon_aliases core2_aliases
731#define sandybridge_xeon_aliases_without_iaf core2_aliases_without_iaf

--- 144 unchanged lines hidden (view full) ---

876 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
877 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
878 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
879 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
880 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
881 NULLMASK
882};
883
884/* Broadwell is defined to use the same mask as Haswell */
852static struct pmc_masks iap_rsp_mask_haswell[] = {
853 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
854 PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
855 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
856 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
857 PMCMASK(REQ_PF_RFO, (1ULL << 5)),
858 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
859 PMCMASK(REQ_OTHER, (1ULL << 15)),
860 PMCMASK(RES_ANY, (1ULL << 16)),
861 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
862 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
863 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
864 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
865 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
866 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
885static struct pmc_masks iap_rsp_mask_haswell[] = {
886 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
887 PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
888 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
889 PMCMASK(REQ_PF_DATA_RD, (1ULL << 4)),
890 PMCMASK(REQ_PF_RFO, (1ULL << 5)),
891 PMCMASK(REQ_PF_IFETCH, (1ULL << 6)),
892 PMCMASK(REQ_OTHER, (1ULL << 15)),
893 PMCMASK(RES_ANY, (1ULL << 16)),
894 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
895 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
896 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
897 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
898 PMCMASK(RES_SUPPLIER_LLC_HITF, (1ULL << 21)),
899 PMCMASK(RES_SUPPLIER_LOCAL, (1ULL << 22)),
900 /*
901 * For processor type 06_45H 22 is L4_HIT_LOCAL_L4
902 * and 23, 24 and 25 are also defined.
903 */
867 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
868 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
869 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
870 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
871 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
872 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
873 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
874 NULLMASK
875};
876
904 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
905 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
906 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
907 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
908 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
909 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
910 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
911 NULLMASK
912};
913
914static struct pmc_masks iap_rsp_mask_skylake[] = {
915 PMCMASK(REQ_DMND_DATA_RD, (1ULL << 0)),
916 PMCMASK(REQ_DMND_RFO, (1ULL << 1)),
917 PMCMASK(REQ_DMND_IFETCH, (1ULL << 2)),
918 PMCMASK(REQ_PF_DATA_RD, (1ULL << 7)),
919 PMCMASK(REQ_PF_RFO, (1ULL << 8)),
920 PMCMASK(REQ_STRM_ST, (1ULL << 11)),
921 PMCMASK(REQ_OTHER, (1ULL << 15)),
922 PMCMASK(RES_ANY, (1ULL << 16)),
923 PMCMASK(RES_SUPPLIER_SUPP, (1ULL << 17)),
924 PMCMASK(RES_SUPPLIER_LLC_HITM, (1ULL << 18)),
925 PMCMASK(RES_SUPPLIER_LLC_HITE, (1ULL << 19)),
926 PMCMASK(RES_SUPPLIER_LLC_HITS, (1ULL << 20)),
927 PMCMASK(RES_SUPPLIER_L4_HIT, (1ULL << 22)),
928 PMCMASK(RES_SUPPLIER_DRAM, (1ULL << 26)),
929 PMCMASK(RES_SUPPLIER_SPL_HIT, (1ULL << 30)),
930 PMCMASK(RES_SNOOP_SNP_NONE, (1ULL << 31)),
931 PMCMASK(RES_SNOOP_SNP_NO_NEEDED,(1ULL << 32)),
932 PMCMASK(RES_SNOOP_SNP_MISS, (1ULL << 33)),
933 PMCMASK(RES_SNOOP_HIT_NO_FWD, (1ULL << 34)),
934 PMCMASK(RES_SNOOP_HIT_FWD, (1ULL << 35)),
935 PMCMASK(RES_SNOOP_HITM, (1ULL << 36)),
936 PMCMASK(RES_NON_DRAM, (1ULL << 37)),
937 NULLMASK
938};
939
940
877static int
878iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
879 struct pmc_op_pmcallocate *pmc_config)
880{
881 char *e, *p, *q;
882 uint64_t cachestate, evmask, rsp;
883 int count, n;
884

--- 75 unchanged lines hidden (view full) ---

960 } else
961 return (-1);
962 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL ||
963 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) {
964 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
965 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
966 } else
967 return (-1);
941static int
942iap_allocate_pmc(enum pmc_event pe, char *ctrspec,
943 struct pmc_op_pmcallocate *pmc_config)
944{
945 char *e, *p, *q;
946 uint64_t cachestate, evmask, rsp;
947 int count, n;
948

--- 75 unchanged lines hidden (view full) ---

1024 } else
1025 return (-1);
1026 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL ||
1027 cpu_info.pm_cputype == PMC_CPU_INTEL_HASWELL_XEON) {
1028 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
1029 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
1030 } else
1031 return (-1);
1032 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL ||
1033 cpu_info.pm_cputype == PMC_CPU_INTEL_BROADWELL_XEON) {
1034 /* Broadwell is defined to use same mask as haswell */
1035 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
1036 n = pmc_parse_mask(iap_rsp_mask_haswell, p, &rsp);
1037 } else
1038 return (-1);
1039
1040 } else if (cpu_info.pm_cputype == PMC_CPU_INTEL_SKYLAKE) {
1041 if (KWPREFIXMATCH(p, IAP_KW_RSP "=")) {
1042 n = pmc_parse_mask(iap_rsp_mask_skylake, p, &rsp);
1043 } else
1044 return (-1);
1045
968 } else
969 return (-1);
970
971 if (n < 0) /* Parsing failed. */
972 return (-1);
973 }
974
975 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;

--- 1936 unchanged lines hidden (view full) ---

2912 case PMC_CPU_INTEL_HASWELL:
2913 ev = haswell_event_table;
2914 count = PMC_EVENT_TABLE_SIZE(haswell);
2915 break;
2916 case PMC_CPU_INTEL_HASWELL_XEON:
2917 ev = haswell_xeon_event_table;
2918 count = PMC_EVENT_TABLE_SIZE(haswell_xeon);
2919 break;
1046 } else
1047 return (-1);
1048
1049 if (n < 0) /* Parsing failed. */
1050 return (-1);
1051 }
1052
1053 pmc_config->pm_md.pm_iap.pm_iap_config |= evmask;

--- 1936 unchanged lines hidden (view full) ---

2990 case PMC_CPU_INTEL_HASWELL:
2991 ev = haswell_event_table;
2992 count = PMC_EVENT_TABLE_SIZE(haswell);
2993 break;
2994 case PMC_CPU_INTEL_HASWELL_XEON:
2995 ev = haswell_xeon_event_table;
2996 count = PMC_EVENT_TABLE_SIZE(haswell_xeon);
2997 break;
2998 case PMC_CPU_INTEL_BROADWELL:
2999 ev = broadwell_event_table;
3000 count = PMC_EVENT_TABLE_SIZE(broadwell);
3001 break;
3002 case PMC_CPU_INTEL_BROADWELL_XEON:
3003 ev = broadwell_xeon_event_table;
3004 count = PMC_EVENT_TABLE_SIZE(broadwell_xeon);
3005 break;
3006 case PMC_CPU_INTEL_SKYLAKE:
3007 ev = skylake_event_table;
3008 count = PMC_EVENT_TABLE_SIZE(skylake);
3009 break;
2920 case PMC_CPU_INTEL_IVYBRIDGE:
2921 ev = ivybridge_event_table;
2922 count = PMC_EVENT_TABLE_SIZE(ivybridge);
2923 break;
2924 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
2925 ev = ivybridge_xeon_event_table;
2926 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
2927 break;

--- 29 unchanged lines hidden (view full) ---

2957 case PMC_CPU_INTEL_COREI7:
2958 ev = corei7uc_event_table;
2959 count = PMC_EVENT_TABLE_SIZE(corei7uc);
2960 break;
2961 case PMC_CPU_INTEL_HASWELL:
2962 ev = haswelluc_event_table;
2963 count = PMC_EVENT_TABLE_SIZE(haswelluc);
2964 break;
3010 case PMC_CPU_INTEL_IVYBRIDGE:
3011 ev = ivybridge_event_table;
3012 count = PMC_EVENT_TABLE_SIZE(ivybridge);
3013 break;
3014 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3015 ev = ivybridge_xeon_event_table;
3016 count = PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3017 break;

--- 29 unchanged lines hidden (view full) ---

3047 case PMC_CPU_INTEL_COREI7:
3048 ev = corei7uc_event_table;
3049 count = PMC_EVENT_TABLE_SIZE(corei7uc);
3050 break;
3051 case PMC_CPU_INTEL_HASWELL:
3052 ev = haswelluc_event_table;
3053 count = PMC_EVENT_TABLE_SIZE(haswelluc);
3054 break;
3055 case PMC_CPU_INTEL_BROADWELL:
3056 ev = broadwelluc_event_table;
3057 count = PMC_EVENT_TABLE_SIZE(broadwelluc);
3058 break;
2965 case PMC_CPU_INTEL_SANDYBRIDGE:
2966 ev = sandybridgeuc_event_table;
2967 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
2968 break;
2969 case PMC_CPU_INTEL_WESTMERE:
2970 ev = westmereuc_event_table;
2971 count = PMC_EVENT_TABLE_SIZE(westmereuc);
2972 break;

--- 303 unchanged lines hidden (view full) ---

3276 case PMC_CPU_INTEL_HASWELL:
3277 pmc_class_table[n++] = &ucf_class_table_descr;
3278 pmc_class_table[n++] = &haswelluc_class_table_descr;
3279 PMC_MDEP_INIT_INTEL_V2(haswell);
3280 break;
3281 case PMC_CPU_INTEL_HASWELL_XEON:
3282 PMC_MDEP_INIT_INTEL_V2(haswell_xeon);
3283 break;
3059 case PMC_CPU_INTEL_SANDYBRIDGE:
3060 ev = sandybridgeuc_event_table;
3061 count = PMC_EVENT_TABLE_SIZE(sandybridgeuc);
3062 break;
3063 case PMC_CPU_INTEL_WESTMERE:
3064 ev = westmereuc_event_table;
3065 count = PMC_EVENT_TABLE_SIZE(westmereuc);
3066 break;

--- 303 unchanged lines hidden (view full) ---

3370 case PMC_CPU_INTEL_HASWELL:
3371 pmc_class_table[n++] = &ucf_class_table_descr;
3372 pmc_class_table[n++] = &haswelluc_class_table_descr;
3373 PMC_MDEP_INIT_INTEL_V2(haswell);
3374 break;
3375 case PMC_CPU_INTEL_HASWELL_XEON:
3376 PMC_MDEP_INIT_INTEL_V2(haswell_xeon);
3377 break;
3378 case PMC_CPU_INTEL_BROADWELL:
3379 pmc_class_table[n++] = &ucf_class_table_descr;
3380 pmc_class_table[n++] = &broadwelluc_class_table_descr;
3381 PMC_MDEP_INIT_INTEL_V2(broadwell);
3382 break;
3383 case PMC_CPU_INTEL_BROADWELL_XEON:
3384 PMC_MDEP_INIT_INTEL_V2(broadwell_xeon);
3385 break;
3386 case PMC_CPU_INTEL_SKYLAKE:
3387 PMC_MDEP_INIT_INTEL_V2(skylake);
3388 break;
3284 case PMC_CPU_INTEL_IVYBRIDGE:
3285 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3286 break;
3287 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3288 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3289 break;
3290 case PMC_CPU_INTEL_SANDYBRIDGE:
3291 pmc_class_table[n++] = &ucf_class_table_descr;

--- 183 unchanged lines hidden (view full) ---

3475 case PMC_CPU_INTEL_HASWELL:
3476 ev = haswell_event_table;
3477 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
3478 break;
3479 case PMC_CPU_INTEL_HASWELL_XEON:
3480 ev = haswell_xeon_event_table;
3481 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon);
3482 break;
3389 case PMC_CPU_INTEL_IVYBRIDGE:
3390 PMC_MDEP_INIT_INTEL_V2(ivybridge);
3391 break;
3392 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3393 PMC_MDEP_INIT_INTEL_V2(ivybridge_xeon);
3394 break;
3395 case PMC_CPU_INTEL_SANDYBRIDGE:
3396 pmc_class_table[n++] = &ucf_class_table_descr;

--- 183 unchanged lines hidden (view full) ---

3580 case PMC_CPU_INTEL_HASWELL:
3581 ev = haswell_event_table;
3582 evfence = haswell_event_table + PMC_EVENT_TABLE_SIZE(haswell);
3583 break;
3584 case PMC_CPU_INTEL_HASWELL_XEON:
3585 ev = haswell_xeon_event_table;
3586 evfence = haswell_xeon_event_table + PMC_EVENT_TABLE_SIZE(haswell_xeon);
3587 break;
3483
3588 case PMC_CPU_INTEL_BROADWELL:
3589 ev = broadwell_event_table;
3590 evfence = broadwell_event_table + PMC_EVENT_TABLE_SIZE(broadwell);
3591 break;
3592 case PMC_CPU_INTEL_BROADWELL_XEON:
3593 ev = broadwell_xeon_event_table;
3594 evfence = broadwell_xeon_event_table + PMC_EVENT_TABLE_SIZE(broadwell_xeon);
3595 break;
3596 case PMC_CPU_INTEL_SKYLAKE:
3597 ev = skylake_event_table;
3598 evfence = skylake_event_table + PMC_EVENT_TABLE_SIZE(skylake);
3599 break;
3484 case PMC_CPU_INTEL_IVYBRIDGE:
3485 ev = ivybridge_event_table;
3486 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3487 break;
3488 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3489 ev = ivybridge_xeon_event_table;
3490 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3491 break;

--- 312 unchanged lines hidden --- 		3600 case PMC_CPU_INTEL_IVYBRIDGE:
3601 ev = ivybridge_event_table;
3602 evfence = ivybridge_event_table + PMC_EVENT_TABLE_SIZE(ivybridge);
3603 break;
3604 case PMC_CPU_INTEL_IVYBRIDGE_XEON:
3605 ev = ivybridge_xeon_event_table;
3606 evfence = ivybridge_xeon_event_table + PMC_EVENT_TABLE_SIZE(ivybridge_xeon);
3607 break;

--- 312 unchanged lines hidden ---