| X86ISelLowering.cpp (323245) | X86ISelLowering.cpp (326496) |
|---|---|
| 1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 7012 unchanged lines hidden (view full) --- 7021 SDLoc dl(Op); 7022 if (ISD::isBuildVectorAllZeros(Op.getNode())) 7023 return DAG.getTargetConstant(0, dl, VT); 7024 7025 if (ISD::isBuildVectorAllOnes(Op.getNode())) 7026 return DAG.getTargetConstant(1, dl, VT); 7027 7028 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { | 1//===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 7012 unchanged lines hidden (view full) --- 7021 SDLoc dl(Op); 7022 if (ISD::isBuildVectorAllZeros(Op.getNode())) 7023 return DAG.getTargetConstant(0, dl, VT); 7024 7025 if (ISD::isBuildVectorAllOnes(Op.getNode())) 7026 return DAG.getTargetConstant(1, dl, VT); 7027 7028 if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) { |
| 7029 if (VT == MVT::v64i1 && !Subtarget.is64Bit()) { 7030 // Split the pieces. 7031 SDValue Lower = 7032 DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(0, 32)); 7033 SDValue Upper = 7034 DAG.getBuildVector(MVT::v32i1, dl, Op.getNode()->ops().slice(32, 32)); 7035 // We have to manually lower both halves so getNode doesn't try to 7036 // reassemble the build_vector. 7037 Lower = LowerBUILD_VECTORvXi1(Lower, DAG); 7038 Upper = LowerBUILD_VECTORvXi1(Upper, DAG); 7039 return DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v64i1, Lower, Upper); 7040 } |
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| 7029 SDValue Imm = ConvertI1VectorToInteger(Op, DAG); 7030 if (Imm.getValueSizeInBits() == VT.getSizeInBits()) 7031 return DAG.getBitcast(VT, Imm); 7032 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm); 7033 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, 7034 DAG.getIntPtrConstant(0, dl)); 7035 } 7036 --- 27691 unchanged lines hidden (view full) --- 34728 // comparison with zero because that gets special treatment in EmitTest(). 34729 SDValue X = SetCC->getOperand(0); 34730 SDValue Y = SetCC->getOperand(1); 34731 EVT OpVT = X.getValueType(); 34732 unsigned OpSize = OpVT.getSizeInBits(); 34733 if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y)) 34734 return SDValue(); 34735 | 7041 SDValue Imm = ConvertI1VectorToInteger(Op, DAG); 7042 if (Imm.getValueSizeInBits() == VT.getSizeInBits()) 7043 return DAG.getBitcast(VT, Imm); 7044 SDValue ExtVec = DAG.getBitcast(MVT::v8i1, Imm); 7045 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, ExtVec, 7046 DAG.getIntPtrConstant(0, dl)); 7047 } 7048 --- 27691 unchanged lines hidden (view full) --- 34740 // comparison with zero because that gets special treatment in EmitTest(). 34741 SDValue X = SetCC->getOperand(0); 34742 SDValue Y = SetCC->getOperand(1); 34743 EVT OpVT = X.getValueType(); 34744 unsigned OpSize = OpVT.getSizeInBits(); 34745 if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y)) 34746 return SDValue(); 34747 |
| 34748 // Bail out if we know that this is not really just an oversized integer. 34749 if (peekThroughBitcasts(X).getValueType() == MVT::f128 || 34750 peekThroughBitcasts(Y).getValueType() == MVT::f128) 34751 return SDValue(); 34752 |
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| 34736 // TODO: Use PXOR + PTEST for SSE4.1 or later? 34737 // TODO: Add support for AVX-512. 34738 EVT VT = SetCC->getValueType(0); 34739 SDLoc DL(SetCC); 34740 if ((OpSize == 128 && Subtarget.hasSSE2()) || 34741 (OpSize == 256 && Subtarget.hasAVX2())) { 34742 EVT VecVT = OpSize == 128 ? MVT::v16i8 : MVT::v32i8; 34743 SDValue VecX = DAG.getBitcast(VecVT, X); --- 2029 unchanged lines hidden --- | 34753 // TODO: Use PXOR + PTEST for SSE4.1 or later? 34754 // TODO: Add support for AVX-512. 34755 EVT VT = SetCC->getValueType(0); 34756 SDLoc DL(SetCC); 34757 if ((OpSize == 128 && Subtarget.hasSSE2()) || 34758 (OpSize == 256 && Subtarget.hasAVX2())) { 34759 EVT VecVT = OpSize == 128 ? MVT::v16i8 : MVT::v32i8; 34760 SDValue VecX = DAG.getBitcast(VecVT, X); --- 2029 unchanged lines hidden --- |