Deleted Added
sdiff udiff text old ( 276479 ) new ( 280031 )
full compact
SparcInstrVIS.td (276479) SparcInstrVIS.td (280031)
1//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 57 unchanged lines hidden (view full) ---

66def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
67
68def FPACK16 : VISInst2<0b000111011, "fpack16">;
69def FPACK32 : VISInst <0b000111010, "fpack32">;
70def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
71def FEXPAND : VISInst2<0b001001101, "fexpand">;
72def FPMERGE : VISInst <0b001001011, "fpmerge">;
73
1//===---- SparcInstrVIS.td - Visual Instruction Set extensions (VIS) -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 57 unchanged lines hidden (view full) ---

66def FPSUB32S : VISInst<0b001010111, "fpsub32S">;
67
68def FPACK16 : VISInst2<0b000111011, "fpack16">;
69def FPACK32 : VISInst <0b000111010, "fpack32">;
70def FPACKFIX : VISInst2<0b000111101, "fpackfix">;
71def FEXPAND : VISInst2<0b001001101, "fexpand">;
72def FPMERGE : VISInst <0b001001011, "fpmerge">;
73
74def FMUL8X16 : VISInst<0b00110001, "fmul8x16">;
75def FMUL8X16AU : VISInst<0b00110011, "fmul8x16au">;
76def FMUL8X16AL : VISInst<0b00110101, "fmul8x16al">;
77def FMUL8SUX16 : VISInst<0b00110110, "fmul8sux16">;
78def FMUL8ULX16 : VISInst<0b00110111, "fmul8ulx16">;
79def FMULD8SUX16 : VISInst<0b00111000, "fmuld8sux16">;
80def FMULD8ULX16 : VISInst<0b00111001, "fmuld8ulx16">;
74def FMUL8X16 : VISInst<0b000110001, "fmul8x16">;
75def FMUL8X16AU : VISInst<0b000110011, "fmul8x16au">;
76def FMUL8X16AL : VISInst<0b000110101, "fmul8x16al">;
77def FMUL8SUX16 : VISInst<0b000110110, "fmul8sux16">;
78def FMUL8ULX16 : VISInst<0b000110111, "fmul8ulx16">;
79def FMULD8SUX16 : VISInst<0b000111000, "fmuld8sux16">;
80def FMULD8ULX16 : VISInst<0b000111001, "fmuld8ulx16">;
81
82def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
83def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
84def FALIGNADATA : VISInst<0b001001000, "faligndata">;
85
86def FZERO : VISInstD<0b001100000, "fzero">;
87def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
88def FONE : VISInstD<0b001111110, "fone">;

--- 40 unchanged lines hidden (view full) ---

129
130def EDGE8 : VISInst<0b000000000, "edge8", I64Regs>;
131def EDGE8L : VISInst<0b000000010, "edge8l", I64Regs>;
132def EDGE16 : VISInst<0b000000100, "edge16", I64Regs>;
133def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>;
134def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>;
135def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>;
136
81
82def ALIGNADDR : VISInst<0b000011000, "alignaddr", I64Regs>;
83def ALIGNADDRL : VISInst<0b000011010, "alignaddrl", I64Regs>;
84def FALIGNADATA : VISInst<0b001001000, "faligndata">;
85
86def FZERO : VISInstD<0b001100000, "fzero">;
87def FZEROS : VISInstD<0b001100001, "fzeros", FPRegs>;
88def FONE : VISInstD<0b001111110, "fone">;

--- 40 unchanged lines hidden (view full) ---

129
130def EDGE8 : VISInst<0b000000000, "edge8", I64Regs>;
131def EDGE8L : VISInst<0b000000010, "edge8l", I64Regs>;
132def EDGE16 : VISInst<0b000000100, "edge16", I64Regs>;
133def EDGE16L : VISInst<0b000000110, "edge16l", I64Regs>;
134def EDGE32 : VISInst<0b000001000, "edge32", I64Regs>;
135def EDGE32L : VISInst<0b000001010, "edge32l", I64Regs>;
136
137def PDIST : VISInst<0b00111110, "pdist">;
137def PDIST : VISInst<0b000111110, "pdist">;
138
139def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>;
140def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>;
141def ARRAY32 : VISInst<0b000010100, "array32", I64Regs>;
142
143def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
144
145} // Predicates = [HasVIS]

--- 30 unchanged lines hidden (view full) ---

176 "cmask8 $rs2", []>;
177def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
178 "cmask16 $rs2", []>;
179def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
180 "cmask32 $rs2", []>;
181
182}
183
138
139def ARRAY8 : VISInst<0b000010000, "array8", I64Regs>;
140def ARRAY16 : VISInst<0b000010010, "array16", I64Regs>;
141def ARRAY32 : VISInst<0b000010100, "array32", I64Regs>;
142
143def SHUTDOWN : VISInst0<0b010000000, "shutdown">;
144
145} // Predicates = [HasVIS]

--- 30 unchanged lines hidden (view full) ---

176 "cmask8 $rs2", []>;
177def CMASK16 : VISInstFormat<0b000011101, (outs), (ins I64Regs:$rs2),
178 "cmask16 $rs2", []>;
179def CMASK32 : VISInstFormat<0b000011111, (outs), (ins I64Regs:$rs2),
180 "cmask32 $rs2", []>;
181
182}
183
184def FCHKSM16 : VISInst<0b01000100, "fchksm16">;
184def FCHKSM16 : VISInst<0b001000100, "fchksm16">;
185
186def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
187 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
188 "fhadds $rs1, $rs2, $rd", []>;
189def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
190 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
191 "fhaddd $rs1, $rs2, $rd", []>;
192def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,

--- 31 unchanged lines hidden (view full) ---

224 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
225 "fnhaddd $rs1, $rs2, $rd", []>;
226def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
227 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
228 "fnhadds $rs1, $rs2, $rd", []>;
229
230def FPADD64 : VISInst<0b001000010, "fpadd64">;
231
185
186def FHADDS : F3_3<0b10, 0b110100, 0b001100001,
187 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
188 "fhadds $rs1, $rs2, $rd", []>;
189def FHADDD : F3_3<0b10, 0b110100, 0b001100010,
190 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
191 "fhaddd $rs1, $rs2, $rd", []>;
192def FHSUBS : F3_3<0b10, 0b110100, 0b001100101,

--- 31 unchanged lines hidden (view full) ---

224 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
225 "fnhaddd $rs1, $rs2, $rd", []>;
226def FNSMULD : F3_3<0b10, 0b110100, 0b001111001,
227 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
228 "fnhadds $rs1, $rs2, $rd", []>;
229
230def FPADD64 : VISInst<0b001000010, "fpadd64">;
231
232def FSLL16 : VISInst<0b00100001, "fsll16">;
233def FSRL16 : VISInst<0b00100011, "fsrl16">;
234def FSLL32 : VISInst<0b00100101, "fsll32">;
235def FSRL32 : VISInst<0b00100111, "fsrl32">;
236def FSLAS16 : VISInst<0b00101001, "fslas16">;
237def FSRA16 : VISInst<0b00101011, "fsra16">;
238def FSLAS32 : VISInst<0b00101101, "fslas32">;
239def FSRA32 : VISInst<0b00101111, "fsra32">;
232def FSLL16 : VISInst<0b000100001, "fsll16">;
233def FSRL16 : VISInst<0b000100011, "fsrl16">;
234def FSLL32 : VISInst<0b000100101, "fsll32">;
235def FSRL32 : VISInst<0b000100111, "fsrl32">;
236def FSLAS16 : VISInst<0b000101001, "fslas16">;
237def FSRA16 : VISInst<0b000101011, "fsra16">;
238def FSLAS32 : VISInst<0b000101101, "fslas32">;
239def FSRA32 : VISInst<0b000101111, "fsra32">;
240
241let rs1 = 0 in
242def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
243 (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
244
245let rs1 = 0 in {
246def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
247 (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;

--- 16 unchanged lines hidden --- 		240
241let rs1 = 0 in
242def LZCNT : VISInstFormat<0b000010111, (outs I64Regs:$rd),
243 (ins I64Regs:$rs2), "lzcnt $rs2, $rd", []>;
244
245let rs1 = 0 in {
246def MOVSTOSW : VISInstFormat<0b100010011, (outs I64Regs:$rd),
247 (ins DFPRegs:$rs2), "movstosw $rs2, $rd", []>;

--- 16 unchanged lines hidden ---