| MipsSEISelLowering.cpp (280031) | MipsSEISelLowering.cpp (283526) |
|---|---|
| 1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 2869 unchanged lines hidden (view full) --- 2878 const TargetInstrInfo *TII = 2879 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 2880 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2881 DebugLoc DL = MI->getDebugLoc(); 2882 unsigned Fd = MI->getOperand(0).getReg(); 2883 unsigned Ws = MI->getOperand(1).getReg(); 2884 unsigned Lane = MI->getOperand(2).getImm(); 2885 | 1//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 2869 unchanged lines hidden (view full) --- 2878 const TargetInstrInfo *TII = 2879 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 2880 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2881 DebugLoc DL = MI->getDebugLoc(); 2882 unsigned Fd = MI->getOperand(0).getReg(); 2883 unsigned Ws = MI->getOperand(1).getReg(); 2884 unsigned Lane = MI->getOperand(2).getImm(); 2885 |
| 2886 if (Lane == 0) 2887 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2888 else { 2889 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); | 2886 if (Lane == 0) { 2887 unsigned Wt = Ws; 2888 if (!Subtarget.useOddSPReg()) { 2889 // We must copy to an even-numbered MSA register so that the 2890 // single-precision sub-register is also guaranteed to be even-numbered. 2891 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); |
| 2890 | 2892 |
| 2893 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws); 2894 } 2895 2896 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2897 } else { 2898 unsigned Wt = RegInfo.createVirtualRegister( 2899 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : 2900 &Mips::MSA128WEvensRegClass); 2901 |
|
| 2891 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); 2892 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2893 } 2894 2895 MI->eraseFromParent(); // The pseudo instruction is gone now. 2896 return BB; 2897} 2898 --- 44 unchanged lines hidden (view full) --- 2943 const TargetInstrInfo *TII = 2944 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 2945 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2946 DebugLoc DL = MI->getDebugLoc(); 2947 unsigned Wd = MI->getOperand(0).getReg(); 2948 unsigned Wd_in = MI->getOperand(1).getReg(); 2949 unsigned Lane = MI->getOperand(2).getImm(); 2950 unsigned Fs = MI->getOperand(3).getReg(); | 2902 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane); 2903 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2904 } 2905 2906 MI->eraseFromParent(); // The pseudo instruction is gone now. 2907 return BB; 2908} 2909 --- 44 unchanged lines hidden (view full) --- 2954 const TargetInstrInfo *TII = 2955 getTargetMachine().getSubtargetImpl()->getInstrInfo(); 2956 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2957 DebugLoc DL = MI->getDebugLoc(); 2958 unsigned Wd = MI->getOperand(0).getReg(); 2959 unsigned Wd_in = MI->getOperand(1).getReg(); 2960 unsigned Lane = MI->getOperand(2).getImm(); 2961 unsigned Fs = MI->getOperand(3).getReg(); |
| 2951 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); | 2962 unsigned Wt = RegInfo.createVirtualRegister( 2963 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass : 2964 &Mips::MSA128WEvensRegClass); |
| 2952 2953 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2954 .addImm(0) 2955 .addReg(Fs) 2956 .addImm(Mips::sub_lo); 2957 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2958 .addReg(Wd_in) 2959 .addImm(Lane) --- 289 unchanged lines hidden --- | 2965 2966 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2967 .addImm(0) 2968 .addReg(Fs) 2969 .addImm(Mips::sub_lo); 2970 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2971 .addReg(Wd_in) 2972 .addImm(Lane) --- 289 unchanged lines hidden --- |