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MipsMachineFunction.h (208954) MipsMachineFunction.h (218893)
1//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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21
22namespace llvm {
23
24/// MipsFunctionInfo - This class is derived from MachineFunction private
25/// Mips target-specific information for each MachineFunction.
26class MipsFunctionInfo : public MachineFunctionInfo {
27
28private:
1//===-- MipsMachineFunctionInfo.h - Private data used for Mips ----*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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21
22namespace llvm {
23
24/// MipsFunctionInfo - This class is derived from MachineFunction private
25/// Mips target-specific information for each MachineFunction.
26class MipsFunctionInfo : public MachineFunctionInfo {
27
28private:
29 /// Holds for each function where on the stack the Frame Pointer must be
29 /// Holds for each function where on the stack the Frame Pointer must be
30 /// saved. This is used on Prologue and Epilogue to emit FP save/restore
31 int FPStackOffset;
32
30 /// saved. This is used on Prologue and Epilogue to emit FP save/restore
31 int FPStackOffset;
32
33 /// Holds for each function where on the stack the Return Address must be
33 /// Holds for each function where on the stack the Return Address must be
34 /// saved. This is used on Prologue and Epilogue to emit RA save/restore
35 int RAStackOffset;
36
37 /// At each function entry, two special bitmask directives must be emitted
38 /// to help debugging, for CPU and FPU callee saved registers. Both need
39 /// the negative offset from the final stack size and its higher registers
40 /// location on the stack.
41 int CPUTopSavedRegOff;

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46
47 int FI;
48 int SPOffset;
49
50 MipsFIHolder(int FrameIndex, int StackPointerOffset)
51 : FI(FrameIndex), SPOffset(StackPointerOffset) {}
52 };
53
34 /// saved. This is used on Prologue and Epilogue to emit RA save/restore
35 int RAStackOffset;
36
37 /// At each function entry, two special bitmask directives must be emitted
38 /// to help debugging, for CPU and FPU callee saved registers. Both need
39 /// the negative offset from the final stack size and its higher registers
40 /// location on the stack.
41 int CPUTopSavedRegOff;

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46
47 int FI;
48 int SPOffset;
49
50 MipsFIHolder(int FrameIndex, int StackPointerOffset)
51 : FI(FrameIndex), SPOffset(StackPointerOffset) {}
52 };
53
54 /// When PIC is used the GP must be saved on the stack on the function
55 /// prologue and must be reloaded from this stack location after every
56 /// call. A reference to its stack location and frame index must be kept
54 /// When PIC is used the GP must be saved on the stack on the function
55 /// prologue and must be reloaded from this stack location after every
56 /// call. A reference to its stack location and frame index must be kept
57 /// to be used on emitPrologue and processFunctionBeforeFrameFinalized.
58 MipsFIHolder GPHolder;
59
60 /// On LowerFormalArguments the stack size is unknown, so the Stack
57 /// to be used on emitPrologue and processFunctionBeforeFrameFinalized.
58 MipsFIHolder GPHolder;
59
60 /// On LowerFormalArguments the stack size is unknown, so the Stack
61 /// Pointer Offset calculation of "not in register arguments" must be
62 /// postponed to emitPrologue.
61 /// Pointer Offset calculation of "not in register arguments" must be
62 /// postponed to emitPrologue.
63 SmallVector<MipsFIHolder, 16> FnLoadArgs;
64 bool HasLoadArgs;
65
63 SmallVector<MipsFIHolder, 16> FnLoadArgs;
64 bool HasLoadArgs;
65
66 // When VarArgs, we must write registers back to caller stack, preserving
67 // on register arguments. Since the stack size is unknown on
66 // When VarArgs, we must write registers back to caller stack, preserving
67 // on register arguments. Since the stack size is unknown on
68 // LowerFormalArguments, the Stack Pointer Offset calculation must be
68 // LowerFormalArguments, the Stack Pointer Offset calculation must be
69 // postponed to emitPrologue.
69 // postponed to emitPrologue.
70 SmallVector<MipsFIHolder, 4> FnStoreVarArgs;
71 bool HasStoreVarArgs;
72
73 /// SRetReturnReg - Some subtargets require that sret lowering includes
74 /// returning the value of the returned struct in a register. This field
75 /// holds the virtual register into which the sret argument is passed.
76 unsigned SRetReturnReg;
77
78 /// GlobalBaseReg - keeps track of the virtual register initialized for
79 /// use as the global base register. This is used for PIC in some PIC
80 /// relocation models.
81 unsigned GlobalBaseReg;
82
83 /// VarArgsFrameIndex - FrameIndex for start of varargs area.
84 int VarArgsFrameIndex;
85
86public:
70 SmallVector<MipsFIHolder, 4> FnStoreVarArgs;
71 bool HasStoreVarArgs;
72
73 /// SRetReturnReg - Some subtargets require that sret lowering includes
74 /// returning the value of the returned struct in a register. This field
75 /// holds the virtual register into which the sret argument is passed.
76 unsigned SRetReturnReg;
77
78 /// GlobalBaseReg - keeps track of the virtual register initialized for
79 /// use as the global base register. This is used for PIC in some PIC
80 /// relocation models.
81 unsigned GlobalBaseReg;
82
83 /// VarArgsFrameIndex - FrameIndex for start of varargs area.
84 int VarArgsFrameIndex;
85
86public:
87 MipsFunctionInfo(MachineFunction& MF)
88 : FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0),
89 FPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false),
87 MipsFunctionInfo(MachineFunction& MF)
88 : FPStackOffset(0), RAStackOffset(0), CPUTopSavedRegOff(0),
89 FPUTopSavedRegOff(0), GPHolder(-1,-1), HasLoadArgs(false),
90 HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0),
91 VarArgsFrameIndex(0)
92 {}
93
94 int getFPStackOffset() const { return FPStackOffset; }
95 void setFPStackOffset(int Off) { FPStackOffset = Off; }
96
97 int getRAStackOffset() const { return RAStackOffset; }

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105
106 int getGPStackOffset() const { return GPHolder.SPOffset; }
107 int getGPFI() const { return GPHolder.FI; }
108 void setGPStackOffset(int Off) { GPHolder.SPOffset = Off; }
109 void setGPFI(int FI) { GPHolder.FI = FI; }
110 bool needGPSaveRestore() const { return GPHolder.SPOffset != -1; }
111
112 bool hasLoadArgs() const { return HasLoadArgs; }
90 HasStoreVarArgs(false), SRetReturnReg(0), GlobalBaseReg(0),
91 VarArgsFrameIndex(0)
92 {}
93
94 int getFPStackOffset() const { return FPStackOffset; }
95 void setFPStackOffset(int Off) { FPStackOffset = Off; }
96
97 int getRAStackOffset() const { return RAStackOffset; }

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105
106 int getGPStackOffset() const { return GPHolder.SPOffset; }
107 int getGPFI() const { return GPHolder.FI; }
108 void setGPStackOffset(int Off) { GPHolder.SPOffset = Off; }
109 void setGPFI(int FI) { GPHolder.FI = FI; }
110 bool needGPSaveRestore() const { return GPHolder.SPOffset != -1; }
111
112 bool hasLoadArgs() const { return HasLoadArgs; }
113 bool hasStoreVarArgs() const { return HasStoreVarArgs; }
113 bool hasStoreVarArgs() const { return HasStoreVarArgs; }
114
115 void recordLoadArgsFI(int FI, int SPOffset) {
116 if (!HasLoadArgs) HasLoadArgs=true;
117 FnLoadArgs.push_back(MipsFIHolder(FI, SPOffset));
118 }
119 void recordStoreVarArgsFI(int FI, int SPOffset) {
120 if (!HasStoreVarArgs) HasStoreVarArgs=true;
121 FnStoreVarArgs.push_back(MipsFIHolder(FI, SPOffset));
122 }
123
124 void adjustLoadArgsFI(MachineFrameInfo *MFI) const {
125 if (!hasLoadArgs()) return;
114
115 void recordLoadArgsFI(int FI, int SPOffset) {
116 if (!HasLoadArgs) HasLoadArgs=true;
117 FnLoadArgs.push_back(MipsFIHolder(FI, SPOffset));
118 }
119 void recordStoreVarArgsFI(int FI, int SPOffset) {
120 if (!HasStoreVarArgs) HasStoreVarArgs=true;
121 FnStoreVarArgs.push_back(MipsFIHolder(FI, SPOffset));
122 }
123
124 void adjustLoadArgsFI(MachineFrameInfo *MFI) const {
125 if (!hasLoadArgs()) return;
126 for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i)
126 for (unsigned i = 0, e = FnLoadArgs.size(); i != e; ++i)
127 MFI->setObjectOffset( FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset );
128 }
129 void adjustStoreVarArgsFI(MachineFrameInfo *MFI) const {
127 MFI->setObjectOffset( FnLoadArgs[i].FI, FnLoadArgs[i].SPOffset );
128 }
129 void adjustStoreVarArgsFI(MachineFrameInfo *MFI) const {
130 if (!hasStoreVarArgs()) return;
131 for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i)
130 if (!hasStoreVarArgs()) return;
131 for (unsigned i = 0, e = FnStoreVarArgs.size(); i != e; ++i)
132 MFI->setObjectOffset( FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset );
133 }
134
135 unsigned getSRetReturnReg() const { return SRetReturnReg; }
136 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
137
138 unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
139 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
140
141 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
142 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
143};
144
145} // end of namespace llvm
146
147#endif // MIPS_MACHINE_FUNCTION_INFO_H
132 MFI->setObjectOffset( FnStoreVarArgs[i].FI, FnStoreVarArgs[i].SPOffset );
133 }
134
135 unsigned getSRetReturnReg() const { return SRetReturnReg; }
136 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
137
138 unsigned getGlobalBaseReg() const { return GlobalBaseReg; }
139 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; }
140
141 int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
142 void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
143};
144
145} // end of namespace llvm
146
147#endif // MIPS_MACHINE_FUNCTION_INFO_H