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HexagonShuffler.cpp (341825) HexagonShuffler.cpp (344779)
1//===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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133 (*TUL)[HexagonII::TypeCVI_GATHER] =
134 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
135 (*TUL)[HexagonII::TypeCVI_SCATTER] =
136 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
137 (*TUL)[HexagonII::TypeCVI_SCATTER_DV] =
138 UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
139 (*TUL)[HexagonII::TypeCVI_SCATTER_NEW_ST] =
140 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
1//===- HexagonShuffler.cpp - Instruction bundle shuffling -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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133 (*TUL)[HexagonII::TypeCVI_GATHER] =
134 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
135 (*TUL)[HexagonII::TypeCVI_SCATTER] =
136 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
137 (*TUL)[HexagonII::TypeCVI_SCATTER_DV] =
138 UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
139 (*TUL)[HexagonII::TypeCVI_SCATTER_NEW_ST] =
140 UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
141 (*TUL)[HexagonII::TypeCVI_4SLOT_MPY] = UnitsAndLanes(CVI_XLANE, 4);
142 (*TUL)[HexagonII::TypeCVI_ZW] = UnitsAndLanes(CVI_ZW, 1);
141}
142
143HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL,
144 MCInstrInfo const &MCII, unsigned s,
145 MCInst const *id)
146 : HexagonResource(s) {
147 unsigned T = HexagonMCInstrInfo::getType(MCII, *id);
148

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295 slotThree = 0x8, // slotFirstJump = 0x8,
296 slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
297 // Highest slots for branches and stores used to keep their original order.
298 // unsigned slotJump = slotFirstJump;
299 unsigned slotLoadStore = slotFirstLoadStore;
300 // Number of memory operations, loads, solo loads, stores, solo stores, single
301 // stores.
302 unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
143}
144
145HexagonCVIResource::HexagonCVIResource(TypeUnitsAndLanes *TUL,
146 MCInstrInfo const &MCII, unsigned s,
147 MCInst const *id)
148 : HexagonResource(s) {
149 unsigned T = HexagonMCInstrInfo::getType(MCII, *id);
150

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297 slotThree = 0x8, // slotFirstJump = 0x8,
298 slotFirstLoadStore = 0x2, slotLastLoadStore = 0x1;
299 // Highest slots for branches and stores used to keep their original order.
300 // unsigned slotJump = slotFirstJump;
301 unsigned slotLoadStore = slotFirstLoadStore;
302 // Number of memory operations, loads, solo loads, stores, solo stores, single
303 // stores.
304 unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0;
305 unsigned NonZCVIloads = 0, AllCVIloads = 0, CVIstores = 0;
303 // Number of duplex insns
304 unsigned duplex = 0;
305 unsigned pSlot3Cnt = 0;
306 unsigned memops = 0;
307 iterator slot3ISJ = end();
308 std::vector<iterator> foundBranches;
309 unsigned reservedSlots = 0;
310

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326 case HexagonII::TypeJ:
327 foundBranches.push_back(ISJ);
328 break;
329 case HexagonII::TypeCVI_VM_VP_LDU:
330 case HexagonII::TypeCVI_VM_LD:
331 case HexagonII::TypeCVI_VM_TMP_LD:
332 case HexagonII::TypeCVI_GATHER:
333 case HexagonII::TypeCVI_GATHER_RST:
306 // Number of duplex insns
307 unsigned duplex = 0;
308 unsigned pSlot3Cnt = 0;
309 unsigned memops = 0;
310 iterator slot3ISJ = end();
311 std::vector<iterator> foundBranches;
312 unsigned reservedSlots = 0;
313

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329 case HexagonII::TypeJ:
330 foundBranches.push_back(ISJ);
331 break;
332 case HexagonII::TypeCVI_VM_VP_LDU:
333 case HexagonII::TypeCVI_VM_LD:
334 case HexagonII::TypeCVI_VM_TMP_LD:
335 case HexagonII::TypeCVI_GATHER:
336 case HexagonII::TypeCVI_GATHER_RST:
337 ++NonZCVIloads;
338 LLVM_FALLTHROUGH;
339 case HexagonII::TypeCVI_ZW:
340 ++AllCVIloads;
341 LLVM_FALLTHROUGH;
334 case HexagonII::TypeLD:
335 ++loads;
336 ++memory;
337 if (ISJ->Core.getUnits() == slotSingleLoad ||
338 HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU)
339 ++load0;
340 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn())
341 foundBranches.push_back(ISJ);
342 break;
343 case HexagonII::TypeCVI_VM_STU:
344 case HexagonII::TypeCVI_VM_ST:
345 case HexagonII::TypeCVI_VM_NEW_ST:
346 case HexagonII::TypeCVI_SCATTER:
347 case HexagonII::TypeCVI_SCATTER_DV:
348 case HexagonII::TypeCVI_SCATTER_RST:
349 case HexagonII::TypeCVI_SCATTER_NEW_RST:
350 case HexagonII::TypeCVI_SCATTER_NEW_ST:
342 case HexagonII::TypeLD:
343 ++loads;
344 ++memory;
345 if (ISJ->Core.getUnits() == slotSingleLoad ||
346 HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_VP_LDU)
347 ++load0;
348 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn())
349 foundBranches.push_back(ISJ);
350 break;
351 case HexagonII::TypeCVI_VM_STU:
352 case HexagonII::TypeCVI_VM_ST:
353 case HexagonII::TypeCVI_VM_NEW_ST:
354 case HexagonII::TypeCVI_SCATTER:
355 case HexagonII::TypeCVI_SCATTER_DV:
356 case HexagonII::TypeCVI_SCATTER_RST:
357 case HexagonII::TypeCVI_SCATTER_NEW_RST:
358 case HexagonII::TypeCVI_SCATTER_NEW_ST:
359 ++CVIstores;
360 LLVM_FALLTHROUGH;
351 case HexagonII::TypeST:
352 ++stores;
353 ++memory;
354 if (ISJ->Core.getUnits() == slotSingleStore ||
355 HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_STU)
356 ++store0;
357 break;
358 case HexagonII::TypeV4LDST:

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400 foundBranches.push_back(ISJ);
401 break;
402 }
403 }
404 }
405 applySlotRestrictions();
406
407 // Check if the packet is legal.
361 case HexagonII::TypeST:
362 ++stores;
363 ++memory;
364 if (ISJ->Core.getUnits() == slotSingleStore ||
365 HexagonMCInstrInfo::getType(MCII, ID) == HexagonII::TypeCVI_VM_STU)
366 ++store0;
367 break;
368 case HexagonII::TypeV4LDST:

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410 foundBranches.push_back(ISJ);
411 break;
412 }
413 }
414 }
415 applySlotRestrictions();
416
417 // Check if the packet is legal.
408 if ((load0 > 1 || store0 > 1) || (duplex > 1 || (duplex && memory))) {
418 const unsigned ZCVIloads = AllCVIloads - NonZCVIloads;
419 const bool ValidHVXMem =
420 NonZCVIloads <= 1 && ZCVIloads <= 1 && CVIstores <= 1;
421 if ((load0 > 1 || store0 > 1 || !ValidHVXMem) ||
422 (duplex > 1 || (duplex && memory))) {
409 reportError(llvm::Twine("invalid instruction packet"));
410 return false;
411 }
412
413 // Modify packet accordingly.
414 // TODO: need to reserve slots #0 and #1 for duplex insns.
415 bool bOnlySlot3 = false;
416 for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {

--- 249 unchanged lines hidden --- 		423 reportError(llvm::Twine("invalid instruction packet"));
424 return false;
425 }
426
427 // Modify packet accordingly.
428 // TODO: need to reserve slots #0 and #1 for duplex insns.
429 bool bOnlySlot3 = false;
430 for (iterator ISJ = begin(); ISJ != end(); ++ISJ) {

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