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HexagonMCCodeEmitter.cpp (327952) HexagonMCCodeEmitter.cpp (341825)
1//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 19 unchanged lines hidden (view full) ---

28#include "llvm/Support/Debug.h"
29#include "llvm/Support/Endian.h"
30#include "llvm/Support/EndianStream.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include <cassert>
34#include <cstddef>
35#include <cstdint>
1//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 19 unchanged lines hidden (view full) ---

28#include "llvm/Support/Debug.h"
29#include "llvm/Support/Endian.h"
30#include "llvm/Support/EndianStream.h"
31#include "llvm/Support/ErrorHandling.h"
32#include "llvm/Support/raw_ostream.h"
33#include <cassert>
34#include <cstddef>
35#include <cstdint>
36#include <map>
36#include <string>
37#include <string>
38#include <vector>
37
38#define DEBUG_TYPE "mccodeemitter"
39
40using namespace llvm;
41using namespace Hexagon;
42
43STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
44
39
40#define DEBUG_TYPE "mccodeemitter"
41
42using namespace llvm;
43using namespace Hexagon;
44
45STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
46
45HexagonMCCodeEmitter::HexagonMCCodeEmitter(MCInstrInfo const &aMII,
46 MCContext &aMCT)
47 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)),
48 Extended(new bool(false)), CurrentBundle(new MCInst const *),
49 CurrentIndex(new size_t(0)) {}
47static const unsigned fixup_Invalid = ~0u;
50
48
51uint32_t HexagonMCCodeEmitter::parseBits(size_t Last,
52 MCInst const &MCB,
49#define _ fixup_Invalid
50#define P(x) Hexagon::fixup_Hexagon##x
51static const std::map<unsigned, std::vector<unsigned>> ExtFixups = {
52 { MCSymbolRefExpr::VK_DTPREL,
53 { _, _, _, _,
54 _, _, P(_DTPREL_16_X), P(_DTPREL_11_X),
55 P(_DTPREL_11_X), P(_9_X), _, P(_DTPREL_11_X),
56 P(_DTPREL_16_X), _, _, _,
57 P(_DTPREL_16_X), _, _, _,
58 _, _, _, _,
59 _, _, _, _,
60 _, _, _, _,
61 P(_DTPREL_32_6_X) }},
62 { MCSymbolRefExpr::VK_GOT,
63 { _, _, _, _,
64 _, _, P(_GOT_11_X), _ /* [1] */,
65 _ /* [1] */, P(_9_X), _, P(_GOT_11_X),
66 P(_GOT_16_X), _, _, _,
67 P(_GOT_16_X), _, _, _,
68 _, _, _, _,
69 _, _, _, _,
70 _, _, _, _,
71 P(_GOT_32_6_X) }},
72 { MCSymbolRefExpr::VK_GOTREL,
73 { _, _, _, _,
74 _, _, P(_GOTREL_11_X), P(_GOTREL_11_X),
75 P(_GOTREL_11_X), P(_9_X), _, P(_GOTREL_11_X),
76 P(_GOTREL_16_X), _, _, _,
77 P(_GOTREL_16_X), _, _, _,
78 _, _, _, _,
79 _, _, _, _,
80 _, _, _, _,
81 P(_GOTREL_32_6_X) }},
82 { MCSymbolRefExpr::VK_TPREL,
83 { _, _, _, _,
84 _, _, P(_TPREL_16_X), P(_TPREL_11_X),
85 P(_TPREL_11_X), P(_9_X), _, P(_TPREL_11_X),
86 P(_TPREL_16_X), _, _, _,
87 P(_TPREL_16_X), _, _, _,
88 _, _, _, _,
89 _, _, _, _,
90 _, _, _, _,
91 P(_TPREL_32_6_X) }},
92 { MCSymbolRefExpr::VK_Hexagon_GD_GOT,
93 { _, _, _, _,
94 _, _, P(_GD_GOT_16_X), P(_GD_GOT_11_X),
95 P(_GD_GOT_11_X), P(_9_X), _, P(_GD_GOT_11_X),
96 P(_GD_GOT_16_X), _, _, _,
97 P(_GD_GOT_16_X), _, _, _,
98 _, _, _, _,
99 _, _, _, _,
100 _, _, _, _,
101 P(_GD_GOT_32_6_X) }},
102 { MCSymbolRefExpr::VK_Hexagon_GD_PLT,
103 { _, _, _, _,
104 _, _, _, _,
105 _, P(_9_X), _, P(_GD_PLT_B22_PCREL_X),
106 _, _, _, _,
107 _, _, _, _,
108 _, _, P(_GD_PLT_B22_PCREL_X), _,
109 _, _, _, _,
110 _, _, _, _,
111 _ }},
112 { MCSymbolRefExpr::VK_Hexagon_IE,
113 { _, _, _, _,
114 _, _, P(_IE_16_X), _,
115 _, P(_9_X), _, _,
116 P(_IE_16_X), _, _, _,
117 P(_IE_16_X), _, _, _,
118 _, _, _, _,
119 _, _, _, _,
120 _, _, _, _,
121 P(_IE_32_6_X) }},
122 { MCSymbolRefExpr::VK_Hexagon_IE_GOT,
123 { _, _, _, _,
124 _, _, P(_IE_GOT_11_X), P(_IE_GOT_11_X),
125 P(_IE_GOT_11_X), P(_9_X), _, P(_IE_GOT_11_X),
126 P(_IE_GOT_16_X), _, _, _,
127 P(_IE_GOT_16_X), _, _, _,
128 _, _, _, _,
129 _, _, _, _,
130 _, _, _, _,
131 P(_IE_GOT_32_6_X) }},
132 { MCSymbolRefExpr::VK_Hexagon_LD_GOT,
133 { _, _, _, _,
134 _, _, P(_LD_GOT_11_X), P(_LD_GOT_11_X),
135 P(_LD_GOT_11_X), P(_9_X), _, P(_LD_GOT_11_X),
136 P(_LD_GOT_16_X), _, _, _,
137 P(_LD_GOT_16_X), _, _, _,
138 _, _, _, _,
139 _, _, _, _,
140 _, _, _, _,
141 P(_LD_GOT_32_6_X) }},
142 { MCSymbolRefExpr::VK_Hexagon_LD_PLT,
143 { _, _, _, _,
144 _, _, _, _,
145 _, P(_9_X), _, P(_LD_PLT_B22_PCREL_X),
146 _, _, _, _,
147 _, _, _, _,
148 _, _, P(_LD_PLT_B22_PCREL_X), _,
149 _, _, _, _,
150 _, _, _, _,
151 _ }},
152 { MCSymbolRefExpr::VK_Hexagon_PCREL,
153 { _, _, _, _,
154 _, _, P(_6_PCREL_X), _,
155 _, P(_9_X), _, _,
156 _, _, _, _,
157 _, _, _, _,
158 _, _, _, _,
159 _, _, _, _,
160 _, _, _, _,
161 P(_32_PCREL) }},
162 { MCSymbolRefExpr::VK_None,
163 { _, _, _, _,
164 _, _, P(_6_X), P(_8_X),
165 P(_8_X), P(_9_X), P(_10_X), P(_11_X),
166 P(_12_X), P(_B13_PCREL), _, P(_B15_PCREL_X),
167 P(_16_X), _, _, _,
168 _, _, P(_B22_PCREL_X), _,
169 _, _, _, _,
170 _, _, _, _,
171 P(_32_6_X) }},
172};
173// [1] The fixup is GOT_16_X for signed values and GOT_11_X for unsigned.
174
175static const std::map<unsigned, std::vector<unsigned>> StdFixups = {
176 { MCSymbolRefExpr::VK_DTPREL,
177 { _, _, _, _,
178 _, _, _, _,
179 _, _, _, _,
180 _, _, _, _,
181 P(_DTPREL_16), _, _, _,
182 _, _, _, _,
183 _, _, _, _,
184 _, _, _, _,
185 P(_DTPREL_32) }},
186 { MCSymbolRefExpr::VK_GOT,
187 { _, _, _, _,
188 _, _, _, _,
189 _, _, _, _,
190 _, _, _, _,
191 _, _, _, _,
192 _, _, _, _,
193 _, _, _, _,
194 _, _, _, _,
195 P(_GOT_32) }},
196 { MCSymbolRefExpr::VK_GOTREL,
197 { _, _, _, _,
198 _, _, _, _,
199 _, _, _, _,
200 _, _, _, _,
201 _ /* [2] */, _, _, _,
202 _, _, _, _,
203 _, _, _, _,
204 _, _, _, _,
205 P(_GOTREL_32) }},
206 { MCSymbolRefExpr::VK_PLT,
207 { _, _, _, _,
208 _, _, _, _,
209 _, _, _, _,
210 _, _, _, _,
211 _, _, _, _,
212 _, _, P(_PLT_B22_PCREL), _,
213 _, _, _, _,
214 _, _, _, _,
215 _ }},
216 { MCSymbolRefExpr::VK_TPREL,
217 { _, _, _, _,
218 _, _, _, _,
219 _, _, _, P(_TPREL_11_X),
220 _, _, _, _,
221 P(_TPREL_16), _, _, _,
222 _, _, _, _,
223 _, _, _, _,
224 _, _, _, _,
225 P(_TPREL_32) }},
226 { MCSymbolRefExpr::VK_Hexagon_GD_GOT,
227 { _, _, _, _,
228 _, _, _, _,
229 _, _, _, _,
230 _, _, _, _,
231 P(_GD_GOT_16), _, _, _,
232 _, _, _, _,
233 _, _, _, _,
234 _, _, _, _,
235 P(_GD_GOT_32) }},
236 { MCSymbolRefExpr::VK_Hexagon_GD_PLT,
237 { _, _, _, _,
238 _, _, _, _,
239 _, _, _, _,
240 _, _, _, _,
241 _, _, _, _,
242 _, _, P(_GD_PLT_B22_PCREL), _,
243 _, _, _, _,
244 _, _, _, _,
245 _ }},
246 { MCSymbolRefExpr::VK_Hexagon_GPREL,
247 { _, _, _, _,
248 _, _, _, _,
249 _, _, _, _,
250 _, _, _, _,
251 P(_GPREL16_0), _, _, _,
252 _, _, _, _,
253 _, _, _, _,
254 _, _, _, _,
255 _ }},
256 { MCSymbolRefExpr::VK_Hexagon_HI16,
257 { _, _, _, _,
258 _, _, _, _,
259 _, _, _, _,
260 _, _, _, _,
261 P(_HI16), _, _, _,
262 _, _, _, _,
263 _, _, _, _,
264 _, _, _, _,
265 _ }},
266 { MCSymbolRefExpr::VK_Hexagon_IE,
267 { _, _, _, _,
268 _, _, _, _,
269 _, _, _, _,
270 _, _, _, _,
271 _, _, _, _,
272 _, _, _, _,
273 _, _, _, _,
274 _, _, _, _,
275 P(_IE_32) }},
276 { MCSymbolRefExpr::VK_Hexagon_IE_GOT,
277 { _, _, _, _,
278 _, _, _, _,
279 _, _, _, _,
280 _, _, _, _,
281 P(_IE_GOT_16), _, _, _,
282 _, _, _, _,
283 _, _, _, _,
284 _, _, _, _,
285 P(_IE_GOT_32) }},
286 { MCSymbolRefExpr::VK_Hexagon_LD_GOT,
287 { _, _, _, _,
288 _, _, _, _,
289 _, _, _, _,
290 _, _, _, _,
291 P(_LD_GOT_16), _, _, _,
292 _, _, _, _,
293 _, _, _, _,
294 _, _, _, _,
295 P(_LD_GOT_32) }},
296 { MCSymbolRefExpr::VK_Hexagon_LD_PLT,
297 { _, _, _, _,
298 _, _, _, _,
299 _, _, _, _,
300 _, _, _, _,
301 _, _, _, _,
302 _, _, P(_LD_PLT_B22_PCREL), _,
303 _, _, _, _,
304 _, _, _, _,
305 _ }},
306 { MCSymbolRefExpr::VK_Hexagon_LO16,
307 { _, _, _, _,
308 _, _, _, _,
309 _, _, _, _,
310 _, _, _, _,
311 P(_LO16), _, _, _,
312 _, _, _, _,
313 _, _, _, _,
314 _, _, _, _,
315 _ }},
316 { MCSymbolRefExpr::VK_Hexagon_PCREL,
317 { _, _, _, _,
318 _, _, _, _,
319 _, _, _, _,
320 _, _, _, _,
321 _, _, _, _,
322 _, _, _, _,
323 _, _, _, _,
324 _, _, _, _,
325 P(_32_PCREL) }},
326 { MCSymbolRefExpr::VK_None,
327 { _, _, _, _,
328 _, _, _, _,
329 _, _, _, _,
330 _, P(_B13_PCREL), _, P(_B15_PCREL),
331 _, _, _, _,
332 _, _, P(_B22_PCREL), _,
333 _, _, _, _,
334 _, _, _, _,
335 P(_32) }},
336};
337//
338// [2] The actual fixup is LO16 or HI16, depending on the instruction.
339#undef P
340#undef _
341
342uint32_t HexagonMCCodeEmitter::parseBits(size_t Last, MCInst const &MCB,
53 MCInst const &MCI) const {
54 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
343 MCInst const &MCI) const {
344 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI);
55 if (*CurrentIndex == 0) {
345 if (State.Index == 0) {
56 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
57 assert(!Duplex);
346 if (HexagonMCInstrInfo::isInnerLoop(MCB)) {
347 assert(!Duplex);
58 assert(*CurrentIndex != Last);
348 assert(State.Index != Last);
59 return HexagonII::INST_PARSE_LOOP_END;
60 }
61 }
349 return HexagonII::INST_PARSE_LOOP_END;
350 }
351 }
62 if (*CurrentIndex == 1) {
352 if (State.Index == 1) {
63 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
64 assert(!Duplex);
353 if (HexagonMCInstrInfo::isOuterLoop(MCB)) {
354 assert(!Duplex);
65 assert(*CurrentIndex != Last);
355 assert(State.Index != Last);
66 return HexagonII::INST_PARSE_LOOP_END;
67 }
68 }
69 if (Duplex) {
356 return HexagonII::INST_PARSE_LOOP_END;
357 }
358 }
359 if (Duplex) {
70 assert(*CurrentIndex == Last);
360 assert(State.Index == Last);
71 return HexagonII::INST_PARSE_DUPLEX;
72 }
361 return HexagonII::INST_PARSE_DUPLEX;
362 }
73 if(*CurrentIndex == Last)
363 if (State.Index == Last)
74 return HexagonII::INST_PARSE_PACKET_END;
75 return HexagonII::INST_PARSE_NOT_END;
76}
77
364 return HexagonII::INST_PARSE_PACKET_END;
365 return HexagonII::INST_PARSE_NOT_END;
366}
367
78/// EncodeInstruction - Emit the bundle
368/// Emit the bundle.
79void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
80 SmallVectorImpl<MCFixup> &Fixups,
81 const MCSubtargetInfo &STI) const {
82 MCInst &HMB = const_cast<MCInst &>(MI);
83
84 assert(HexagonMCInstrInfo::isBundle(HMB));
369void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
370 SmallVectorImpl<MCFixup> &Fixups,
371 const MCSubtargetInfo &STI) const {
372 MCInst &HMB = const_cast<MCInst &>(MI);
373
374 assert(HexagonMCInstrInfo::isBundle(HMB));
85 DEBUG(dbgs() << "Encoding bundle\n";);
86 *Addend = 0;
87 *Extended = false;
88 *CurrentBundle = &MI;
89 *CurrentIndex = 0;
375 LLVM_DEBUG(dbgs() << "Encoding bundle\n";);
376 State.Addend = 0;
377 State.Extended = false;
378 State.Bundle = &MI;
379 State.Index = 0;
90 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
380 size_t Last = HexagonMCInstrInfo::bundleSize(HMB) - 1;
381 uint64_t Features = computeAvailableFeatures(STI.getFeatureBits());
382
91 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
92 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
383 for (auto &I : HexagonMCInstrInfo::bundleInstructions(HMB)) {
384 MCInst &HMI = const_cast<MCInst &>(*I.getInst());
93 verifyInstructionPredicates(HMI,
94 computeAvailableFeatures(STI.getFeatureBits()));
385 verifyInstructionPredicates(HMI, Features);
95
386
96 EncodeSingleInstruction(HMI, OS, Fixups, STI,
97 parseBits(Last, HMB, HMI));
98 *Extended = HexagonMCInstrInfo::isImmext(HMI);
99 *Addend += HEXAGON_INSTR_SIZE;
100 ++*CurrentIndex;
387 EncodeSingleInstruction(HMI, OS, Fixups, STI, parseBits(Last, HMB, HMI));
388 State.Extended = HexagonMCInstrInfo::isImmext(HMI);
389 State.Addend += HEXAGON_INSTR_SIZE;
390 ++State.Index;
101 }
102}
103
104static bool RegisterMatches(unsigned Consumer, unsigned Producer,
105 unsigned Producer2) {
106 if (Consumer == Producer)
107 return true;
108 if (Consumer == Producer2)
109 return true;
110 // Calculate if we're a single vector consumer referencing a double producer
111 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
112 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
113 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
114 return false;
115}
116
117/// EncodeSingleInstruction - Emit a single
391 }
392}
393
394static bool RegisterMatches(unsigned Consumer, unsigned Producer,
395 unsigned Producer2) {
396 if (Consumer == Producer)
397 return true;
398 if (Consumer == Producer2)
399 return true;
400 // Calculate if we're a single vector consumer referencing a double producer
401 if (Producer >= Hexagon::W0 && Producer <= Hexagon::W15)
402 if (Consumer >= Hexagon::V0 && Consumer <= Hexagon::V31)
403 return ((Consumer - Hexagon::V0) >> 1) == (Producer - Hexagon::W0);
404 return false;
405}
406
407/// EncodeSingleInstruction - Emit a single
118void HexagonMCCodeEmitter::EncodeSingleInstruction(
119 const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
120 const MCSubtargetInfo &STI, uint32_t Parse) const {
408void HexagonMCCodeEmitter::EncodeSingleInstruction(const MCInst &MI,
409 raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups,
410 const MCSubtargetInfo &STI, uint32_t Parse) const {
121 assert(!HexagonMCInstrInfo::isBundle(MI));
122 uint64_t Binary;
123
124 // Pseudo instructions don't get encoded and shouldn't be here
125 // in the first place!
126 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
127 "pseudo-instruction found");
411 assert(!HexagonMCInstrInfo::isBundle(MI));
412 uint64_t Binary;
413
414 // Pseudo instructions don't get encoded and shouldn't be here
415 // in the first place!
416 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() &&
417 "pseudo-instruction found");
128 DEBUG(dbgs() << "Encoding insn"
129 " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
130 "\n");
418 LLVM_DEBUG(dbgs() << "Encoding insn `"
419 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
131
132 Binary = getBinaryCodeForInstr(MI, Fixups, STI);
420
421 Binary = getBinaryCodeForInstr(MI, Fixups, STI);
422 unsigned Opc = MI.getOpcode();
423
133 // Check for unimplemented instructions. Immediate extenders
134 // are encoded as zero, so they need to be accounted for.
424 // Check for unimplemented instructions. Immediate extenders
425 // are encoded as zero, so they need to be accounted for.
135 if (!Binary &&
136 MI.getOpcode() != DuplexIClass0 &&
137 MI.getOpcode() != A4_ext) {
138 DEBUG(dbgs() << "Unimplemented inst: "
139 " `" << HexagonMCInstrInfo::getName(MCII, MI) << "'"
140 "\n");
426 if (!Binary && Opc != DuplexIClass0 && Opc != A4_ext) {
427 LLVM_DEBUG(dbgs() << "Unimplemented inst `"
428 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n");
141 llvm_unreachable("Unimplemented Instruction");
142 }
143 Binary |= Parse;
144
145 // if we need to emit a duplexed instruction
429 llvm_unreachable("Unimplemented Instruction");
430 }
431 Binary |= Parse;
432
433 // if we need to emit a duplexed instruction
146 if (MI.getOpcode() >= Hexagon::DuplexIClass0 &&
147 MI.getOpcode() <= Hexagon::DuplexIClassF) {
434 if (Opc >= Hexagon::DuplexIClass0 && Opc <= Hexagon::DuplexIClassF) {
148 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
149 "Emitting duplex without duplex parse bits");
435 assert(Parse == HexagonII::INST_PARSE_DUPLEX &&
436 "Emitting duplex without duplex parse bits");
150 unsigned dupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
437 unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
151 // 29 is the bit position.
152 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
153 // Last bit is moved to bit position 13
438 // 29 is the bit position.
439 // 0b1110 =0xE bits are masked off and down shifted by 1 bit.
440 // Last bit is moved to bit position 13
154 Binary = ((dupIClass & 0xE) << (29 - 1)) | ((dupIClass & 0x1) << 13);
441 Binary = ((DupIClass & 0xE) << (29 - 1)) | ((DupIClass & 0x1) << 13);
155
442
156 const MCInst *subInst0 = MI.getOperand(0).getInst();
157 const MCInst *subInst1 = MI.getOperand(1).getInst();
443 const MCInst *Sub0 = MI.getOperand(0).getInst();
444 const MCInst *Sub1 = MI.getOperand(1).getInst();
158
445
159 // get subinstruction slot 0
160 unsigned subInstSlot0Bits = getBinaryCodeForInstr(*subInst0, Fixups, STI);
161 // get subinstruction slot 1
162 unsigned subInstSlot1Bits = getBinaryCodeForInstr(*subInst1, Fixups, STI);
446 // Get subinstruction slot 0.
447 unsigned SubBits0 = getBinaryCodeForInstr(*Sub0, Fixups, STI);
448 // Get subinstruction slot 1.
449 State.SubInst1 = true;
450 unsigned SubBits1 = getBinaryCodeForInstr(*Sub1, Fixups, STI);
451 State.SubInst1 = false;
163
452
164 Binary |= subInstSlot0Bits | (subInstSlot1Bits << 16);
453 Binary |= SubBits0 | (SubBits1 << 16);
165 }
454 }
166 support::endian::Writer<support::little>(OS).write<uint32_t>(Binary);
455 support::endian::write<uint32_t>(OS, Binary, support::little);
167 ++MCNumEmitted;
168}
169
170LLVM_ATTRIBUTE_NORETURN
456 ++MCNumEmitted;
457}
458
459LLVM_ATTRIBUTE_NORETURN
171static void raise_relocation_error(unsigned bits, unsigned kind) {
460static void raise_relocation_error(unsigned Width, unsigned Kind) {
172 std::string Text;
461 std::string Text;
173 {
174 raw_string_ostream Stream(Text);
175 Stream << "Unrecognized relocation combination bits: " << bits
176 << " kind: " << kind;
177 }
178 report_fatal_error(Text);
462 raw_string_ostream Stream(Text);
463 Stream << "Unrecognized relocation combination: width=" << Width
464 << " kind=" << Kind;
465 report_fatal_error(Stream.str());
179}
180
466}
467
181/// getFixupNoBits - Some insns are not extended and thus have no
182/// bits. These cases require a more brute force method for determining
183/// the correct relocation.
468/// Some insns are not extended and thus have no bits. These cases require
469/// a more brute force method for determining the correct relocation.
184Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
470Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits(
185 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
186 const MCSymbolRefExpr::VariantKind kind) const {
471 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO,
472 const MCSymbolRefExpr::VariantKind VarKind) const {
187 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
473 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
188 unsigned insnType = HexagonMCInstrInfo::getType(MCII, MI);
474 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI);
475 using namespace Hexagon;
189
476
190 if (insnType == HexagonII::TypeEXTENDER) {
191 switch (kind) {
192 case MCSymbolRefExpr::VK_GOTREL:
193 return Hexagon::fixup_Hexagon_GOTREL_32_6_X;
194 case MCSymbolRefExpr::VK_GOT:
195 return Hexagon::fixup_Hexagon_GOT_32_6_X;
196 case MCSymbolRefExpr::VK_TPREL:
197 return Hexagon::fixup_Hexagon_TPREL_32_6_X;
198 case MCSymbolRefExpr::VK_DTPREL:
199 return Hexagon::fixup_Hexagon_DTPREL_32_6_X;
200 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
201 return Hexagon::fixup_Hexagon_GD_GOT_32_6_X;
202 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
203 return Hexagon::fixup_Hexagon_LD_GOT_32_6_X;
204 case MCSymbolRefExpr::VK_Hexagon_IE:
205 return Hexagon::fixup_Hexagon_IE_32_6_X;
206 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
207 return Hexagon::fixup_Hexagon_IE_GOT_32_6_X;
208 case MCSymbolRefExpr::VK_Hexagon_PCREL:
209 return Hexagon::fixup_Hexagon_B32_PCREL_X;
210 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
211 return Hexagon::fixup_Hexagon_GD_PLT_B32_PCREL_X;
212 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
213 return Hexagon::fixup_Hexagon_LD_PLT_B32_PCREL_X;
214
215 case MCSymbolRefExpr::VK_None: {
216 auto Insts = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
217 for (auto I = Insts.begin(), N = Insts.end(); I != N; ++I) {
218 if (I->getInst() == &MI) {
219 const MCInst &NextI = *(I+1)->getInst();
220 const MCInstrDesc &D = HexagonMCInstrInfo::getDesc(MCII, NextI);
221 if (D.isBranch() || D.isCall() ||
222 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
223 return Hexagon::fixup_Hexagon_B32_PCREL_X;
224 return Hexagon::fixup_Hexagon_32_6_X;
225 }
477 if (InsnType == HexagonII::TypeEXTENDER) {
478 if (VarKind == MCSymbolRefExpr::VK_None) {
479 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
480 for (auto I = Instrs.begin(), N = Instrs.end(); I != N; ++I) {
481 if (I->getInst() != &MI)
482 continue;
483 assert(I+1 != N && "Extender cannot be last in packet");
484 const MCInst &NextI = *(I+1)->getInst();
485 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI);
486 if (NextD.isBranch() || NextD.isCall() ||
487 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR)
488 return fixup_Hexagon_B32_PCREL_X;
489 return fixup_Hexagon_32_6_X;
226 }
490 }
227 raise_relocation_error(0, kind);
228 }
491 }
229 default:
230 raise_relocation_error(0, kind);
231 }
232 } else if (MCID.isBranch())
233 return Hexagon::fixup_Hexagon_B13_PCREL;
234
492
235 switch (MCID.getOpcode()) {
236 case Hexagon::HI:
237 case Hexagon::A2_tfrih:
238 switch (kind) {
239 case MCSymbolRefExpr::VK_GOT:
240 return Hexagon::fixup_Hexagon_GOT_HI16;
241 case MCSymbolRefExpr::VK_GOTREL:
242 return Hexagon::fixup_Hexagon_GOTREL_HI16;
243 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
244 return Hexagon::fixup_Hexagon_GD_GOT_HI16;
245 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
246 return Hexagon::fixup_Hexagon_LD_GOT_HI16;
247 case MCSymbolRefExpr::VK_Hexagon_IE:
248 return Hexagon::fixup_Hexagon_IE_HI16;
249 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
250 return Hexagon::fixup_Hexagon_IE_GOT_HI16;
251 case MCSymbolRefExpr::VK_TPREL:
252 return Hexagon::fixup_Hexagon_TPREL_HI16;
253 case MCSymbolRefExpr::VK_DTPREL:
254 return Hexagon::fixup_Hexagon_DTPREL_HI16;
255 case MCSymbolRefExpr::VK_None:
256 return Hexagon::fixup_Hexagon_HI16;
257 default:
258 raise_relocation_error(0, kind);
259 }
493 static const std::map<unsigned,unsigned> Relocs = {
494 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_32_6_X },
495 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_32_6_X },
496 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_32_6_X },
497 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_32_6_X },
498 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_32_6_X },
499 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_32_6_X },
500 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_32_6_X },
501 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_32_6_X },
502 { MCSymbolRefExpr::VK_Hexagon_PCREL, fixup_Hexagon_B32_PCREL_X },
503 { MCSymbolRefExpr::VK_Hexagon_GD_PLT, fixup_Hexagon_GD_PLT_B32_PCREL_X },
504 { MCSymbolRefExpr::VK_Hexagon_LD_PLT, fixup_Hexagon_LD_PLT_B32_PCREL_X },
505 };
260
506
261 case Hexagon::LO:
262 case Hexagon::A2_tfril:
263 switch (kind) {
264 case MCSymbolRefExpr::VK_GOT:
265 return Hexagon::fixup_Hexagon_GOT_LO16;
266 case MCSymbolRefExpr::VK_GOTREL:
267 return Hexagon::fixup_Hexagon_GOTREL_LO16;
268 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
269 return Hexagon::fixup_Hexagon_GD_GOT_LO16;
270 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
271 return Hexagon::fixup_Hexagon_LD_GOT_LO16;
272 case MCSymbolRefExpr::VK_Hexagon_IE:
273 return Hexagon::fixup_Hexagon_IE_LO16;
274 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
275 return Hexagon::fixup_Hexagon_IE_GOT_LO16;
276 case MCSymbolRefExpr::VK_TPREL:
277 return Hexagon::fixup_Hexagon_TPREL_LO16;
278 case MCSymbolRefExpr::VK_DTPREL:
279 return Hexagon::fixup_Hexagon_DTPREL_LO16;
280 case MCSymbolRefExpr::VK_None:
281 return Hexagon::fixup_Hexagon_LO16;
282 default:
283 raise_relocation_error(0, kind);
284 }
285
286 // The only relocs left should be GP relative:
287 default:
288 if (MCID.mayStore() || MCID.mayLoad()) {
289 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
290 ++ImpUses) {
291 if (*ImpUses != Hexagon::GP)
292 continue;
293 switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
294 case 1:
295 return fixup_Hexagon_GPREL16_0;
296 case 2:
297 return fixup_Hexagon_GPREL16_1;
298 case 4:
299 return fixup_Hexagon_GPREL16_2;
300 case 8:
301 return fixup_Hexagon_GPREL16_3;
302 default:
303 raise_relocation_error(0, kind);
304 }
305 }
306 }
307 raise_relocation_error(0, kind);
507 auto F = Relocs.find(VarKind);
508 if (F != Relocs.end())
509 return Hexagon::Fixups(F->second);
510 raise_relocation_error(0, VarKind);
308 }
511 }
309 llvm_unreachable("Relocation exit not taken");
310}
311
512
312namespace llvm {
513 if (MCID.isBranch())
514 return fixup_Hexagon_B13_PCREL;
313
515
314extern const MCInstrDesc HexagonInsts[];
516 static const std::map<unsigned,unsigned> RelocsLo = {
517 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_LO16 },
518 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_LO16 },
519 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_LO16 },
520 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_LO16 },
521 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_LO16 },
522 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_LO16 },
523 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_LO16 },
524 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_LO16 },
525 { MCSymbolRefExpr::VK_None, fixup_Hexagon_LO16 },
526 };
315
527
316} // end namespace llvm
528 static const std::map<unsigned,unsigned> RelocsHi = {
529 { MCSymbolRefExpr::VK_GOT, fixup_Hexagon_GOT_HI16 },
530 { MCSymbolRefExpr::VK_GOTREL, fixup_Hexagon_GOTREL_HI16 },
531 { MCSymbolRefExpr::VK_Hexagon_GD_GOT, fixup_Hexagon_GD_GOT_HI16 },
532 { MCSymbolRefExpr::VK_Hexagon_LD_GOT, fixup_Hexagon_LD_GOT_HI16 },
533 { MCSymbolRefExpr::VK_Hexagon_IE, fixup_Hexagon_IE_HI16 },
534 { MCSymbolRefExpr::VK_Hexagon_IE_GOT, fixup_Hexagon_IE_GOT_HI16 },
535 { MCSymbolRefExpr::VK_TPREL, fixup_Hexagon_TPREL_HI16 },
536 { MCSymbolRefExpr::VK_DTPREL, fixup_Hexagon_DTPREL_HI16 },
537 { MCSymbolRefExpr::VK_None, fixup_Hexagon_HI16 },
538 };
317
539
318static bool isPCRel (unsigned Kind) {
319 switch(Kind){
540 switch (MCID.getOpcode()) {
541 case Hexagon::LO:
542 case Hexagon::A2_tfril: {
543 auto F = RelocsLo.find(VarKind);
544 if (F != RelocsLo.end())
545 return Hexagon::Fixups(F->second);
546 break;
547 }
548 case Hexagon::HI:
549 case Hexagon::A2_tfrih: {
550 auto F = RelocsHi.find(VarKind);
551 if (F != RelocsHi.end())
552 return Hexagon::Fixups(F->second);
553 break;
554 }
555 }
556
557 raise_relocation_error(0, VarKind);
558}
559
560static bool isPCRel(unsigned Kind) {
561 switch (Kind){
320 case fixup_Hexagon_B22_PCREL:
321 case fixup_Hexagon_B15_PCREL:
322 case fixup_Hexagon_B7_PCREL:
323 case fixup_Hexagon_B13_PCREL:
324 case fixup_Hexagon_B9_PCREL:
325 case fixup_Hexagon_B32_PCREL_X:
326 case fixup_Hexagon_B22_PCREL_X:
327 case fixup_Hexagon_B15_PCREL_X:

--- 9 unchanged lines hidden (view full) ---

337 case fixup_Hexagon_6_PCREL_X:
338 return true;
339 default:
340 return false;
341 }
342}
343
344unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
562 case fixup_Hexagon_B22_PCREL:
563 case fixup_Hexagon_B15_PCREL:
564 case fixup_Hexagon_B7_PCREL:
565 case fixup_Hexagon_B13_PCREL:
566 case fixup_Hexagon_B9_PCREL:
567 case fixup_Hexagon_B32_PCREL_X:
568 case fixup_Hexagon_B22_PCREL_X:
569 case fixup_Hexagon_B15_PCREL_X:

--- 9 unchanged lines hidden (view full) ---

579 case fixup_Hexagon_6_PCREL_X:
580 return true;
581 default:
582 return false;
583 }
584}
585
586unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI,
345 const MCOperand &MO,
346 const MCExpr *ME,
347 SmallVectorImpl<MCFixup> &Fixups,
348 const MCSubtargetInfo &STI) const
349{
587 const MCOperand &MO, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups,
588 const MCSubtargetInfo &STI) const {
350 if (isa<HexagonMCExpr>(ME))
351 ME = &HexagonMCInstrInfo::getExpr(*ME);
352 int64_t Value;
589 if (isa<HexagonMCExpr>(ME))
590 ME = &HexagonMCInstrInfo::getExpr(*ME);
591 int64_t Value;
353 if (ME->evaluateAsAbsolute(Value))
592 if (ME->evaluateAsAbsolute(Value)) {
593 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) ||
594 HexagonMCInstrInfo::isExtended(MCII, MI);
595 // Only sub-instruction #1 can be extended in a duplex. If MI is a
596 // sub-instruction #0, it is not extended even if Extended is true
597 // (it can be true for the duplex as a whole).
598 bool IsSub0 = HexagonMCInstrInfo::isSubInstruction(MI) && !State.SubInst1;
599 if (State.Extended && InstExtendable && !IsSub0) {
600 unsigned OpIdx = ~0u;
601 for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
602 if (&MO != &MI.getOperand(I))
603 continue;
604 OpIdx = I;
605 break;
606 }
607 assert(OpIdx != ~0u);
608 if (OpIdx == HexagonMCInstrInfo::getExtendableOp(MCII, MI)) {
609 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
610 Value = (Value & 0x3f) << Shift;
611 }
612 }
354 return Value;
613 return Value;
614 }
355 assert(ME->getKind() == MCExpr::SymbolRef ||
356 ME->getKind() == MCExpr::Binary);
357 if (ME->getKind() == MCExpr::Binary) {
358 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
359 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
360 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
361 return 0;
362 }
615 assert(ME->getKind() == MCExpr::SymbolRef ||
616 ME->getKind() == MCExpr::Binary);
617 if (ME->getKind() == MCExpr::Binary) {
618 MCBinaryExpr const *Binary = cast<MCBinaryExpr>(ME);
619 getExprOpValue(MI, MO, Binary->getLHS(), Fixups, STI);
620 getExprOpValue(MI, MO, Binary->getRHS(), Fixups, STI);
621 return 0;
622 }
363 Hexagon::Fixups FixupKind =
364 Hexagon::Fixups(Hexagon::fixup_Hexagon_TPREL_LO16);
623
624 unsigned FixupKind = fixup_Invalid;
365 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
366 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
625 const MCSymbolRefExpr *MCSRE = static_cast<const MCSymbolRefExpr *>(ME);
626 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI);
367 unsigned bits = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
368 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
369 const MCSymbolRefExpr::VariantKind kind = MCSRE->getKind();
627 unsigned FixupWidth = HexagonMCInstrInfo::getExtentBits(MCII, MI) -
628 HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
629 MCSymbolRefExpr::VariantKind VarKind = MCSRE->getKind();
630 unsigned Opc = MCID.getOpcode();
631 unsigned IType = HexagonMCInstrInfo::getType(MCII, MI);
370
632
371 DEBUG(dbgs() << "----------------------------------------\n");
372 DEBUG(dbgs() << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
373 << "\n");
374 DEBUG(dbgs() << "Opcode: " << MCID.getOpcode() << "\n");
375 DEBUG(dbgs() << "Relocation bits: " << bits << "\n");
376 DEBUG(dbgs() << "Addend: " << *Addend << "\n");
377 DEBUG(dbgs() << "----------------------------------------\n");
633 LLVM_DEBUG(dbgs() << "----------------------------------------\n"
634 << "Opcode Name: " << HexagonMCInstrInfo::getName(MCII, MI)
635 << "\nOpcode: " << Opc << "\nRelocation bits: "
636 << FixupWidth << "\nAddend: " << State.Addend
637 << "\nVariant: " << unsigned(VarKind)
638 << "\n----------------------------------------\n");
378
639
379 switch (bits) {
380 default:
381 raise_relocation_error(bits, kind);
382 case 32:
383 switch (kind) {
384 case MCSymbolRefExpr::VK_DTPREL:
385 FixupKind = *Extended ? Hexagon::fixup_Hexagon_DTPREL_32_6_X
386 : Hexagon::fixup_Hexagon_DTPREL_32;
387 break;
388 case MCSymbolRefExpr::VK_GOT:
389 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOT_32_6_X
390 : Hexagon::fixup_Hexagon_GOT_32;
391 break;
392 case MCSymbolRefExpr::VK_GOTREL:
393 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GOTREL_32_6_X
394 : Hexagon::fixup_Hexagon_GOTREL_32;
395 break;
396 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
397 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_GOT_32_6_X
398 : Hexagon::fixup_Hexagon_GD_GOT_32;
399 break;
400 case MCSymbolRefExpr::VK_Hexagon_IE:
401 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_32_6_X
402 : Hexagon::fixup_Hexagon_IE_32;
403 break;
404 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
405 FixupKind = *Extended ? Hexagon::fixup_Hexagon_IE_GOT_32_6_X
406 : Hexagon::fixup_Hexagon_IE_GOT_32;
407 break;
408 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
409 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_GOT_32_6_X
410 : Hexagon::fixup_Hexagon_LD_GOT_32;
411 break;
412 case MCSymbolRefExpr::VK_Hexagon_PCREL:
413 FixupKind = Hexagon::fixup_Hexagon_32_PCREL;
414 break;
415 case MCSymbolRefExpr::VK_None:
416 FixupKind =
417 *Extended ? Hexagon::fixup_Hexagon_32_6_X : Hexagon::fixup_Hexagon_32;
418 break;
419 case MCSymbolRefExpr::VK_TPREL:
420 FixupKind = *Extended ? Hexagon::fixup_Hexagon_TPREL_32_6_X
421 : Hexagon::fixup_Hexagon_TPREL_32;
422 break;
423 default:
424 raise_relocation_error(bits, kind);
425 }
426 break;
640 // Pick the applicable fixup kind for the symbol.
641 // Handle special cases first, the rest will be looked up in the tables.
427
642
428 case 22:
429 switch (kind) {
430 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
431 FixupKind = *Extended ? Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X
432 : Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL;
433 break;
434 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
435 FixupKind = *Extended ? Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X
436 : Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL;
437 break;
438 case MCSymbolRefExpr::VK_None:
439 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B22_PCREL_X
440 : Hexagon::fixup_Hexagon_B22_PCREL;
441 break;
442 case MCSymbolRefExpr::VK_PLT:
443 FixupKind = Hexagon::fixup_Hexagon_PLT_B22_PCREL;
444 break;
445 default:
446 raise_relocation_error(bits, kind);
447 }
448 break;
449
450 case 16:
451 if (*Extended) {
452 switch (kind) {
453 case MCSymbolRefExpr::VK_DTPREL:
454 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
455 break;
456 case MCSymbolRefExpr::VK_GOT:
457 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
458 break;
459 case MCSymbolRefExpr::VK_GOTREL:
460 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
461 break;
462 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
463 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16_X;
464 break;
465 case MCSymbolRefExpr::VK_Hexagon_IE:
466 FixupKind = Hexagon::fixup_Hexagon_IE_16_X;
467 break;
468 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
469 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16_X;
470 break;
471 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
472 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16_X;
473 break;
474 case MCSymbolRefExpr::VK_None:
475 FixupKind = Hexagon::fixup_Hexagon_16_X;
476 break;
477 case MCSymbolRefExpr::VK_TPREL:
478 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
479 break;
480 default:
481 raise_relocation_error(bits, kind);
643 if (FixupWidth == 16 && !State.Extended) {
644 if (VarKind == MCSymbolRefExpr::VK_None) {
645 if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) {
646 // A2_iconst.
647 FixupKind = Hexagon::fixup_Hexagon_27_REG;
648 } else {
649 // Look for GP-relative fixups.
650 unsigned Shift = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
651 static const Hexagon::Fixups GPRelFixups[] = {
652 Hexagon::fixup_Hexagon_GPREL16_0, Hexagon::fixup_Hexagon_GPREL16_1,
653 Hexagon::fixup_Hexagon_GPREL16_2, Hexagon::fixup_Hexagon_GPREL16_3
654 };
655 assert(Shift < array_lengthof(GPRelFixups));
656 auto UsesGP = [] (const MCInstrDesc &D) {
657 for (const MCPhysReg *U = D.getImplicitUses(); U && *U; ++U)
658 if (*U == Hexagon::GP)
659 return true;
660 return false;
661 };
662 if (UsesGP(MCID))
663 FixupKind = GPRelFixups[Shift];
482 }
664 }
483 } else
484 switch (kind) {
485 case MCSymbolRefExpr::VK_None:
486 if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr()))
487 FixupKind = Hexagon::fixup_Hexagon_27_REG;
488 else
489 if (MCID.mayStore() || MCID.mayLoad()) {
490 for (const MCPhysReg *ImpUses = MCID.getImplicitUses(); *ImpUses;
491 ++ImpUses) {
492 if (*ImpUses != Hexagon::GP)
493 continue;
494 switch (HexagonMCInstrInfo::getMemAccessSize(MCII, MI)) {
495 case 1:
496 FixupKind = fixup_Hexagon_GPREL16_0;
497 break;
498 case 2:
499 FixupKind = fixup_Hexagon_GPREL16_1;
500 break;
501 case 4:
502 FixupKind = fixup_Hexagon_GPREL16_2;
503 break;
504 case 8:
505 FixupKind = fixup_Hexagon_GPREL16_3;
506 break;
507 default:
508 raise_relocation_error(bits, kind);
509 }
510 }
511 } else
512 raise_relocation_error(bits, kind);
513 break;
514 case MCSymbolRefExpr::VK_DTPREL:
515 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16;
516 break;
517 case MCSymbolRefExpr::VK_GOTREL:
518 if (MCID.getOpcode() == Hexagon::HI)
519 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
520 else
521 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
522 break;
523 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
524 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_16;
525 break;
526 case MCSymbolRefExpr::VK_Hexagon_GPREL:
527 FixupKind = Hexagon::fixup_Hexagon_GPREL16_0;
528 break;
529 case MCSymbolRefExpr::VK_Hexagon_HI16:
530 FixupKind = Hexagon::fixup_Hexagon_HI16;
531 break;
532 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
533 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_16;
534 break;
535 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
536 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_16;
537 break;
538 case MCSymbolRefExpr::VK_Hexagon_LO16:
539 FixupKind = Hexagon::fixup_Hexagon_LO16;
540 break;
541 case MCSymbolRefExpr::VK_TPREL:
542 FixupKind = Hexagon::fixup_Hexagon_TPREL_16;
543 break;
544 default:
545 raise_relocation_error(bits, kind);
546 }
547 break;
548
549 case 15:
550 switch (kind) {
551 case MCSymbolRefExpr::VK_None:
552 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B15_PCREL_X
553 : Hexagon::fixup_Hexagon_B15_PCREL;
554 break;
555 default:
556 raise_relocation_error(bits, kind);
665 } else if (VarKind == MCSymbolRefExpr::VK_GOTREL) {
666 // Select between LO/HI.
667 if (Opc == Hexagon::LO)
668 FixupKind = Hexagon::fixup_Hexagon_GOTREL_LO16;
669 else if (Opc == Hexagon::HI)
670 FixupKind = Hexagon::fixup_Hexagon_GOTREL_HI16;
557 }
671 }
558 break;
559
560 case 13:
561 switch (kind) {
562 case MCSymbolRefExpr::VK_None:
563 FixupKind = Hexagon::fixup_Hexagon_B13_PCREL;
564 break;
565 default:
566 raise_relocation_error(bits, kind);
567 }
568 break;
569
570 case 12:
571 if (*Extended)
572 switch (kind) {
573 // There isn't a GOT_12_X, both 11_X and 16_X resolve to 6/26
574 case MCSymbolRefExpr::VK_GOT:
575 FixupKind = Hexagon::fixup_Hexagon_GOT_16_X;
672 } else {
673 bool BranchOrCR = MCID.isBranch() || IType == HexagonII::TypeCR;
674 switch (FixupWidth) {
675 case 9:
676 if (BranchOrCR)
677 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
678 : Hexagon::fixup_Hexagon_B9_PCREL;
576 break;
679 break;
577 case MCSymbolRefExpr::VK_GOTREL:
578 FixupKind = Hexagon::fixup_Hexagon_GOTREL_16_X;
680 case 8:
681 case 7:
682 if (State.Extended && VarKind == MCSymbolRefExpr::VK_GOT)
683 FixupKind = HexagonMCInstrInfo::isExtentSigned(MCII, MI)
684 ? Hexagon::fixup_Hexagon_GOT_16_X
685 : Hexagon::fixup_Hexagon_GOT_11_X;
686 else if (FixupWidth == 7 && BranchOrCR)
687 FixupKind = State.Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
688 : Hexagon::fixup_Hexagon_B7_PCREL;
579 break;
689 break;
580 case MCSymbolRefExpr::VK_None:
581 FixupKind = Hexagon::fixup_Hexagon_12_X;
690 case 0:
691 FixupKind = getFixupNoBits(MCII, MI, MO, VarKind);
582 break;
692 break;
583 default:
584 raise_relocation_error(bits, kind);
585 }
586 else
587 raise_relocation_error(bits, kind);
588 break;
589
590 case 11:
591 if (*Extended)
592 switch (kind) {
593 case MCSymbolRefExpr::VK_DTPREL:
594 FixupKind = Hexagon::fixup_Hexagon_DTPREL_11_X;
595 break;
596 case MCSymbolRefExpr::VK_GOT:
597 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
598 break;
599 case MCSymbolRefExpr::VK_GOTREL:
600 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
601 break;
602 case MCSymbolRefExpr::VK_Hexagon_GD_GOT:
603 FixupKind = Hexagon::fixup_Hexagon_GD_GOT_11_X;
604 break;
605 case MCSymbolRefExpr::VK_Hexagon_IE_GOT:
606 FixupKind = Hexagon::fixup_Hexagon_IE_GOT_11_X;
607 break;
608 case MCSymbolRefExpr::VK_Hexagon_LD_GOT:
609 FixupKind = Hexagon::fixup_Hexagon_LD_GOT_11_X;
610 break;
611 case MCSymbolRefExpr::VK_Hexagon_GD_PLT:
612 FixupKind = Hexagon::fixup_Hexagon_GD_PLT_B22_PCREL_X;
613 break;
614 case MCSymbolRefExpr::VK_Hexagon_LD_PLT:
615 FixupKind = Hexagon::fixup_Hexagon_LD_PLT_B22_PCREL_X;
616 break;
617 case MCSymbolRefExpr::VK_None:
618 FixupKind = Hexagon::fixup_Hexagon_11_X;
619 break;
620 case MCSymbolRefExpr::VK_TPREL:
621 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
622 break;
623 default:
624 raise_relocation_error(bits, kind);
625 }
626 else {
627 switch (kind) {
628 case MCSymbolRefExpr::VK_TPREL:
629 FixupKind = Hexagon::fixup_Hexagon_TPREL_11_X;
630 break;
631 default:
632 raise_relocation_error(bits, kind);
633 }
634 }
693 }
635 break;
694 }
636
695
637 case 10:
638 if (*Extended) {
639 switch (kind) {
640 case MCSymbolRefExpr::VK_None:
641 FixupKind = Hexagon::fixup_Hexagon_10_X;
642 break;
643 default:
644 raise_relocation_error(bits, kind);
645 }
646 } else
647 raise_relocation_error(bits, kind);
648 break;
696 if (FixupKind == fixup_Invalid) {
697 const auto &FixupTable = State.Extended ? ExtFixups : StdFixups;
649
698
650 case 9:
651 if (MCID.isBranch() ||
652 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
653 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B9_PCREL_X
654 : Hexagon::fixup_Hexagon_B9_PCREL;
655 else if (*Extended)
656 FixupKind = Hexagon::fixup_Hexagon_9_X;
657 else
658 raise_relocation_error(bits, kind);
659 break;
699 auto FindVK = FixupTable.find(VarKind);
700 if (FindVK != FixupTable.end())
701 FixupKind = FindVK->second[FixupWidth];
702 }
660
703
661 case 8:
662 if (*Extended)
663 FixupKind = Hexagon::fixup_Hexagon_8_X;
664 else
665 raise_relocation_error(bits, kind);
666 break;
704 if (FixupKind == fixup_Invalid)
705 raise_relocation_error(FixupWidth, VarKind);
667
706
668 case 7:
669 if (MCID.isBranch() ||
670 (HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCR))
671 FixupKind = *Extended ? Hexagon::fixup_Hexagon_B7_PCREL_X
672 : Hexagon::fixup_Hexagon_B7_PCREL;
673 else if (*Extended)
674 FixupKind = Hexagon::fixup_Hexagon_7_X;
675 else
676 raise_relocation_error(bits, kind);
677 break;
678
679 case 6:
680 if (*Extended) {
681 switch (kind) {
682 case MCSymbolRefExpr::VK_DTPREL:
683 FixupKind = Hexagon::fixup_Hexagon_DTPREL_16_X;
684 break;
685 // This is part of an extender, GOT_11 is a
686 // Word32_U6 unsigned/truncated reloc.
687 case MCSymbolRefExpr::VK_GOT:
688 FixupKind = Hexagon::fixup_Hexagon_GOT_11_X;
689 break;
690 case MCSymbolRefExpr::VK_GOTREL:
691 FixupKind = Hexagon::fixup_Hexagon_GOTREL_11_X;
692 break;
693 case MCSymbolRefExpr::VK_Hexagon_PCREL:
694 FixupKind = Hexagon::fixup_Hexagon_6_PCREL_X;
695 break;
696 case MCSymbolRefExpr::VK_TPREL:
697 FixupKind = Hexagon::fixup_Hexagon_TPREL_16_X;
698 break;
699 case MCSymbolRefExpr::VK_None:
700 FixupKind = Hexagon::fixup_Hexagon_6_X;
701 break;
702 default:
703 raise_relocation_error(bits, kind);
704 }
705 } else
706 raise_relocation_error(bits, kind);
707 break;
708
709 case 0:
710 FixupKind = getFixupNoBits(MCII, MI, MO, kind);
711 break;
707 const MCExpr *FixupExpr = MO.getExpr();
708 if (State.Addend != 0 && isPCRel(FixupKind)) {
709 const MCExpr *C = MCConstantExpr::create(State.Addend, MCT);
710 FixupExpr = MCBinaryExpr::createAdd(FixupExpr, C, MCT);
712 }
713
711 }
712
714 MCExpr const *FixupExpression =
715 (*Addend > 0 && isPCRel(FixupKind))
716 ? MCBinaryExpr::createAdd(MO.getExpr(),
717 MCConstantExpr::create(*Addend, MCT), MCT)
718 : MO.getExpr();
719
720 MCFixup fixup = MCFixup::create(*Addend, FixupExpression,
713 MCFixup Fixup = MCFixup::create(State.Addend, FixupExpr,
721 MCFixupKind(FixupKind), MI.getLoc());
714 MCFixupKind(FixupKind), MI.getLoc());
722 Fixups.push_back(fixup);
715 Fixups.push_back(Fixup);
723 // All of the information is in the fixup.
724 return 0;
725}
726
727unsigned
728HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
729 SmallVectorImpl<MCFixup> &Fixups,
730 MCSubtargetInfo const &STI) const {
731#ifndef NDEBUG
732 size_t OperandNumber = ~0U;
733 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
734 if (&MI.getOperand(i) == &MO) {
735 OperandNumber = i;
736 break;
737 }
738 assert((OperandNumber != ~0U) && "Operand not found");
739#endif
740
741 if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
716 // All of the information is in the fixup.
717 return 0;
718}
719
720unsigned
721HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
722 SmallVectorImpl<MCFixup> &Fixups,
723 MCSubtargetInfo const &STI) const {
724#ifndef NDEBUG
725 size_t OperandNumber = ~0U;
726 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i)
727 if (&MI.getOperand(i) == &MO) {
728 OperandNumber = i;
729 break;
730 }
731 assert((OperandNumber != ~0U) && "Operand not found");
732#endif
733
734 if (HexagonMCInstrInfo::isNewValue(MCII, MI) &&
742 &MO == &MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI))) {
735 &MO == &HexagonMCInstrInfo::getNewValueOperand(MCII, MI)) {
743 // Calculate the new value distance to the associated producer
736 // Calculate the new value distance to the associated producer
744 MCOperand const &MCO =
745 MI.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, MI));
746 unsigned SOffset = 0;
747 unsigned VOffset = 0;
737 unsigned SOffset = 0;
738 unsigned VOffset = 0;
748 unsigned Register = MCO.getReg();
749 unsigned Register1;
750 unsigned Register2;
751 auto Instructions = HexagonMCInstrInfo::bundleInstructions(**CurrentBundle);
752 auto i = Instructions.begin() + *CurrentIndex - 1;
753 for (;; --i) {
754 assert(i != Instructions.begin() - 1 && "Couldn't find producer");
755 MCInst const &Inst = *i->getInst();
739 unsigned UseReg = MO.getReg();
740 unsigned DefReg1, DefReg2;
741
742 auto Instrs = HexagonMCInstrInfo::bundleInstructions(*State.Bundle);
743 const MCOperand *I = Instrs.begin() + State.Index - 1;
744
745 for (;; --I) {
746 assert(I != Instrs.begin() - 1 && "Couldn't find producer");
747 MCInst const &Inst = *I->getInst();
756 if (HexagonMCInstrInfo::isImmext(Inst))
757 continue;
748 if (HexagonMCInstrInfo::isImmext(Inst))
749 continue;
750
751 DefReg1 = DefReg2 = 0;
758 ++SOffset;
752 ++SOffset;
759 if (HexagonMCInstrInfo::isVector(MCII, Inst))
760 // Vector instructions don't count scalars
753 if (HexagonMCInstrInfo::isVector(MCII, Inst)) {
754 // Vector instructions don't count scalars.
761 ++VOffset;
755 ++VOffset;
762 Register1 =
763 HexagonMCInstrInfo::hasNewValue(MCII, Inst)
764 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg()
765 : static_cast<unsigned>(Hexagon::NoRegister);
766 Register2 =
767 HexagonMCInstrInfo::hasNewValue2(MCII, Inst)
768 ? HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg()
769 : static_cast<unsigned>(Hexagon::NoRegister);
770 if (!RegisterMatches(Register, Register1, Register2))
756 }
757 if (HexagonMCInstrInfo::hasNewValue(MCII, Inst))
758 DefReg1 = HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg();
759 if (HexagonMCInstrInfo::hasNewValue2(MCII, Inst))
760 DefReg2 = HexagonMCInstrInfo::getNewValueOperand2(MCII, Inst).getReg();
761 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) {
771 // This isn't the register we're looking for
772 continue;
762 // This isn't the register we're looking for
763 continue;
773 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst))
764 }
765 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) {
774 // Producer is unpredicated
775 break;
766 // Producer is unpredicated
767 break;
768 }
776 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
769 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) &&
777 "Unpredicated consumer depending on predicated producer");
770 "Unpredicated consumer depending on predicated producer");
778 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
771 if (HexagonMCInstrInfo::isPredicatedTrue(MCII, Inst) ==
779 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
780 // Producer predicate sense matched ours
772 HexagonMCInstrInfo::isPredicatedTrue(MCII, MI))
773 // Producer predicate sense matched ours.
781 break;
782 }
783 // Hexagon PRM 10.11 Construct Nt from distance
774 break;
775 }
776 // Hexagon PRM 10.11 Construct Nt from distance
784 unsigned Offset =
785 HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset : SOffset;
777 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset
778 : SOffset;
786 Offset <<= 1;
779 Offset <<= 1;
787 Offset |=
788 HexagonMCInstrInfo::SubregisterBit(Register, Register1, Register2);
780 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2);
789 return Offset;
790 }
781 return Offset;
782 }
783
791 assert(!MO.isImm());
792 if (MO.isReg()) {
793 unsigned Reg = MO.getReg();
794 if (HexagonMCInstrInfo::isSubInstruction(MI) ||
795 HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
796 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
797 return MCT.getRegisterInfo()->getEncodingValue(Reg);
798 }

--- 12 unchanged lines hidden --- 		784 assert(!MO.isImm());
785 if (MO.isReg()) {
786 unsigned Reg = MO.getReg();
787 if (HexagonMCInstrInfo::isSubInstruction(MI) ||
788 HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ)
789 return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg);
790 return MCT.getRegisterInfo()->getEncodingValue(Reg);
791 }

--- 12 unchanged lines hidden ---