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AVRInstrInfo.td (321369) AVRInstrInfo.td (326496)
1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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1147 "ld\t$reg, $ptrreg",
1148 [(set GPR8:$reg, (load i16:$ptrreg))]>,
1149 Requires<[HasSRAM]>;
1150
1151 // LDW Rd+1:Rd, P
1152 //
1153 // Expands to:
1154 // ld Rd, P+
1//===-- AVRInstrInfo.td - AVR Instruction defs -------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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1147 "ld\t$reg, $ptrreg",
1148 [(set GPR8:$reg, (load i16:$ptrreg))]>,
1149 Requires<[HasSRAM]>;
1150
1151 // LDW Rd+1:Rd, P
1152 //
1153 // Expands to:
1154 // ld Rd, P+
1155 // ld Rd+1, P+
1155 // ld Rd+1, P
1156 let Constraints = "@earlyclobber $reg" in
1157 def LDWRdPtr : Pseudo<(outs DREGS:$reg),
1156 let Constraints = "@earlyclobber $reg" in
1157 def LDWRdPtr : Pseudo<(outs DREGS:$reg),
1158 (ins PTRDISPREGS:$ptrreg),
1158 (ins PTRREGS:$ptrreg),
1159 "ldw\t$reg, $ptrreg",
1160 [(set i16:$reg, (load i16:$ptrreg))]>,
1161 Requires<[HasSRAM]>;
1162}
1163
1164// Indirect loads (with postincrement or predecrement).
1165let mayLoad = 1,
1166hasSideEffects = 0,
1159 "ldw\t$reg, $ptrreg",
1160 [(set i16:$reg, (load i16:$ptrreg))]>,
1161 Requires<[HasSRAM]>;
1162}
1163
1164// Indirect loads (with postincrement or predecrement).
1165let mayLoad = 1,
1166hasSideEffects = 0,
1167Constraints = "$ptrreg = $base_wb,@earlyclobber $reg,@earlyclobber $base_wb" in
1167Constraints = "$ptrreg = $base_wb,@earlyclobber $reg" in
1168{
1169 def LDRdPtrPi : FSTLD<0,
1170 0b01,
1171 (outs GPR8:$reg, PTRREGS:$base_wb),
1172 (ins LDSTPtrReg:$ptrreg),
1173 "ld\t$reg, $ptrreg+",
1174 []>,
1175 Requires<[HasSRAM]>;

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1233 Constraints = "@earlyclobber $dst" in
1234 def LDDWRdYQ : Pseudo<(outs DREGS:$dst),
1235 (ins memri:$memri),
1236 "lddw\t$dst, $memri",
1237 []>,
1238 Requires<[HasSRAM]>;
1239}
1240
1168{
1169 def LDRdPtrPi : FSTLD<0,
1170 0b01,
1171 (outs GPR8:$reg, PTRREGS:$base_wb),
1172 (ins LDSTPtrReg:$ptrreg),
1173 "ld\t$reg, $ptrreg+",
1174 []>,
1175 Requires<[HasSRAM]>;

--- 57 unchanged lines hidden (view full) ---

1233 Constraints = "@earlyclobber $dst" in
1234 def LDDWRdYQ : Pseudo<(outs DREGS:$dst),
1235 (ins memri:$memri),
1236 "lddw\t$dst, $memri",
1237 []>,
1238 Requires<[HasSRAM]>;
1239}
1240
1241class AtomicLoad<PatFrag Op, RegisterClass DRC> :
1242 Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr), "atomic_op",
1241class AtomicLoad<PatFrag Op, RegisterClass DRC,
1242 RegisterClass PTRRC> :
1243 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1243 [(set DRC:$rd, (Op i16:$rr))]>;
1244
1244 [(set DRC:$rd, (Op i16:$rr))]>;
1245
1245class AtomicStore<PatFrag Op, RegisterClass DRC> :
1246 Pseudo<(outs), (ins PTRDISPREGS:$rd, DRC:$rr), "atomic_op",
1246class AtomicStore<PatFrag Op, RegisterClass DRC,
1247 RegisterClass PTRRC> :
1248 Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1247 [(Op i16:$rd, DRC:$rr)]>;
1248
1249 [(Op i16:$rd, DRC:$rr)]>;
1250
1249class AtomicLoadOp<PatFrag Op, RegisterClass DRC> :
1250 Pseudo<(outs DRC:$rd), (ins PTRREGS:$rr, DRC:$operand),
1251class AtomicLoadOp<PatFrag Op, RegisterClass DRC,
1252 RegisterClass PTRRC> :
1253 Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand),
1251 "atomic_op",
1252 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
1253
1254 "atomic_op",
1255 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
1256
1254def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8>;
1255def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS>;
1257// FIXME: I think 16-bit atomic binary ops need to mark
1258// r0 as clobbered.
1256
1259
1257def AtomicStore8 : AtomicStore<atomic_store_8, GPR8>;
1258def AtomicStore16 : AtomicStore<atomic_store_16, DREGS>;
1260// Atomic instructions
1261// ===================
1262//
1263// These are all expanded by AVRExpandPseudoInsts
1264//
1265// 8-bit operations can use any pointer register because
1266// they are expanded directly into an LD/ST instruction.
1267//
1268// 16-bit operations use 16-bit load/store postincrement instructions,
1269// which require PTRDISPREGS.
1259
1270
1260def AtomicLoadAdd8 : AtomicLoadOp<atomic_load_add_8, GPR8>;
1261def AtomicLoadAdd16 : AtomicLoadOp<atomic_load_add_16, DREGS>;
1262def AtomicLoadSub8 : AtomicLoadOp<atomic_load_sub_8, GPR8>;
1263def AtomicLoadSub16 : AtomicLoadOp<atomic_load_sub_16, DREGS>;
1264def AtomicLoadAnd8 : AtomicLoadOp<atomic_load_and_8, GPR8>;
1265def AtomicLoadAnd16 : AtomicLoadOp<atomic_load_and_16, DREGS>;
1266def AtomicLoadOr8 : AtomicLoadOp<atomic_load_or_8, GPR8>;
1267def AtomicLoadOr16 : AtomicLoadOp<atomic_load_or_16, DREGS>;
1268def AtomicLoadXor8 : AtomicLoadOp<atomic_load_xor_8, GPR8>;
1269def AtomicLoadXor16 : AtomicLoadOp<atomic_load_xor_16, DREGS>;
1271def AtomicLoad8 : AtomicLoad<atomic_load_8, GPR8, PTRREGS>;
1272def AtomicLoad16 : AtomicLoad<atomic_load_16, DREGS, PTRDISPREGS>;
1273
1274def AtomicStore8 : AtomicStore<atomic_store_8, GPR8, PTRREGS>;
1275def AtomicStore16 : AtomicStore<atomic_store_16, DREGS, PTRDISPREGS>;
1276
1277class AtomicLoadOp8<PatFrag Op> : AtomicLoadOp<Op, GPR8, PTRREGS>;
1278class AtomicLoadOp16<PatFrag Op> : AtomicLoadOp<Op, DREGS, PTRDISPREGS>;
1279
1280def AtomicLoadAdd8 : AtomicLoadOp8<atomic_load_add_8>;
1281def AtomicLoadAdd16 : AtomicLoadOp16<atomic_load_add_16>;
1282def AtomicLoadSub8 : AtomicLoadOp8<atomic_load_sub_8>;
1283def AtomicLoadSub16 : AtomicLoadOp16<atomic_load_sub_16>;
1284def AtomicLoadAnd8 : AtomicLoadOp8<atomic_load_and_8>;
1285def AtomicLoadAnd16 : AtomicLoadOp16<atomic_load_and_16>;
1286def AtomicLoadOr8 : AtomicLoadOp8<atomic_load_or_8>;
1287def AtomicLoadOr16 : AtomicLoadOp16<atomic_load_or_16>;
1288def AtomicLoadXor8 : AtomicLoadOp8<atomic_load_xor_8>;
1289def AtomicLoadXor16 : AtomicLoadOp16<atomic_load_xor_16>;
1270def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
1271 [(atomic_fence imm, imm)]>;
1272
1273// Indirect store from register to data space.
1274def STSKRr : F32DM<0b1,
1275 (outs),
1276 (ins imm16:$k, GPR8:$rd),
1277 "sts\t$k, $rd",

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1392 "stdw\t$memri, $src",
1393 [(store i16:$src, addr:$memri)]>,
1394 Requires<[HasSRAM]>;
1395
1396
1397// Load program memory operations.
1398let canFoldAsLoad = 1,
1399isReMaterializable = 1,
1290def AtomicFence : Pseudo<(outs), (ins), "atomic_fence",
1291 [(atomic_fence imm, imm)]>;
1292
1293// Indirect store from register to data space.
1294def STSKRr : F32DM<0b1,
1295 (outs),
1296 (ins imm16:$k, GPR8:$rd),
1297 "sts\t$k, $rd",

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1412 "stdw\t$memri, $src",
1413 [(store i16:$src, addr:$memri)]>,
1414 Requires<[HasSRAM]>;
1415
1416
1417// Load program memory operations.
1418let canFoldAsLoad = 1,
1419isReMaterializable = 1,
1420mayLoad = 1,
1400hasSideEffects = 0 in
1401{
1402 let Defs = [R0],
1403 Uses = [R31R30] in
1404 def LPM : F16<0b1001010111001000,
1405 (outs),
1406 (ins),
1407 "lpm",

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1412 0,
1413 (outs GPR8:$dst),
1414 (ins ZREG:$z),
1415 "lpm\t$dst, $z",
1416 []>,
1417 Requires<[HasLPMX]>;
1418
1419 // Load program memory, while postincrementing the Z register.
1421hasSideEffects = 0 in
1422{
1423 let Defs = [R0],
1424 Uses = [R31R30] in
1425 def LPM : F16<0b1001010111001000,
1426 (outs),
1427 (ins),
1428 "lpm",

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1433 0,
1434 (outs GPR8:$dst),
1435 (ins ZREG:$z),
1436 "lpm\t$dst, $z",
1437 []>,
1438 Requires<[HasLPMX]>;
1439
1440 // Load program memory, while postincrementing the Z register.
1420 let mayLoad = 1,
1421 Defs = [R31R30] in
1441 let Defs = [R31R30] in
1422 {
1423 def LPMRdZPi : FLPMX<0,
1424 1,
1425 (outs GPR8:$dst),
1426 (ins ZREG:$z),
1427 "lpm\t$dst, $z+",
1428 []>,
1429 Requires<[HasLPMX]>;

--- 646 unchanged lines hidden --- 		1442 {
1443 def LPMRdZPi : FLPMX<0,
1444 1,
1445 (outs GPR8:$dst),
1446 (ins ZREG:$z),
1447 "lpm\t$dst, $z+",
1448 []>,
1449 Requires<[HasLPMX]>;

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