Thumb2InstrInfo.cpp (208954) | Thumb2InstrInfo.cpp (210299) |
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1//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Thumb2InstrInfo.h" 15#include "ARM.h" 16#include "ARMConstantPoolValue.h" 17#include "ARMAddressingModes.h" 18#include "ARMGenInstrInfo.inc" 19#include "ARMMachineFunctionInfo.h" | 1//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Thumb2InstrInfo.h" 15#include "ARM.h" 16#include "ARMConstantPoolValue.h" 17#include "ARMAddressingModes.h" 18#include "ARMGenInstrInfo.inc" 19#include "ARMMachineFunctionInfo.h" |
20#include "Thumb2HazardRecognizer.h" 21#include "Thumb2InstrInfo.h" |
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20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineMemOperand.h" 23#include "llvm/CodeGen/PseudoSourceValue.h" 24#include "llvm/ADT/SmallVector.h" | 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineMemOperand.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/ADT/SmallVector.h" |
25#include "Thumb2InstrInfo.h" | 27#include "llvm/Support/CommandLine.h" |
26 27using namespace llvm; 28 | 28 29using namespace llvm; 30 |
31static cl::opt<unsigned> 32IfCvtLimit("thumb2-ifcvt-limit", cl::Hidden, 33 cl::desc("Thumb2 if-conversion limit (default 3)"), 34 cl::init(3)); 35 36static cl::opt<unsigned> 37IfCvtDiamondLimit("thumb2-ifcvt-diamond-limit", cl::Hidden, 38 cl::desc("Thumb2 diamond if-conversion limit (default 3)"), 39 cl::init(3)); 40 |
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29Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) 30 : ARMBaseInstrInfo(STI), RI(*this, STI) { 31} 32 33unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { 34 // FIXME 35 return 0; 36} 37 | 41Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI) 42 : ARMBaseInstrInfo(STI), RI(*this, STI) { 43} 44 45unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { 46 // FIXME 47 return 0; 48} 49 |
38bool 39Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 40 MachineBasicBlock::iterator I, 41 unsigned DestReg, unsigned SrcReg, 42 const TargetRegisterClass *DestRC, 43 const TargetRegisterClass *SrcRC, 44 DebugLoc DL) const { 45 if (DestRC == ARM::GPRRegisterClass) { 46 if (SrcRC == ARM::GPRRegisterClass) { 47 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg); 48 return true; 49 } else if (SrcRC == ARM::tGPRRegisterClass) { 50 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg); 51 return true; | 50void 51Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 52 MachineBasicBlock *NewDest) const { 53 MachineBasicBlock *MBB = Tail->getParent(); 54 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 55 if (!AFI->hasITBlocks()) { 56 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 57 return; 58 } 59 60 // If the first instruction of Tail is predicated, we may have to update 61 // the IT instruction. 62 unsigned PredReg = 0; 63 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg); 64 MachineBasicBlock::iterator MBBI = Tail; 65 if (CC != ARMCC::AL) 66 // Expecting at least the t2IT instruction before it. 67 --MBBI; 68 69 // Actually replace the tail. 70 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest); 71 72 // Fix up IT. 73 if (CC != ARMCC::AL) { 74 MachineBasicBlock::iterator E = MBB->begin(); 75 unsigned Count = 4; // At most 4 instructions in an IT block. 76 while (Count && MBBI != E) { 77 if (MBBI->isDebugValue()) { 78 --MBBI; 79 continue; 80 } 81 if (MBBI->getOpcode() == ARM::t2IT) { 82 unsigned Mask = MBBI->getOperand(1).getImm(); 83 if (Count == 4) 84 MBBI->eraseFromParent(); 85 else { 86 unsigned MaskOn = 1 << Count; 87 unsigned MaskOff = ~(MaskOn - 1); 88 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn); 89 } 90 return; 91 } 92 --MBBI; 93 --Count; |
52 } | 94 } |
53 } else if (DestRC == ARM::tGPRRegisterClass) { 54 if (SrcRC == ARM::GPRRegisterClass) { 55 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg); 56 return true; 57 } else if (SrcRC == ARM::tGPRRegisterClass) { 58 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg); 59 return true; 60 } | 95 96 // Ctrl flow can reach here if branch folding is run before IT block 97 // formation pass. |
61 } | 98 } |
99} |
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62 | 100 |
101bool 102Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, 103 MachineBasicBlock::iterator MBBI) const { 104 unsigned PredReg = 0; 105 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 106} 107 108bool Thumb2InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, 109 unsigned NumInstrs) const { 110 return NumInstrs && NumInstrs <= IfCvtLimit; 111} 112 113bool Thumb2InstrInfo:: 114isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT, 115 MachineBasicBlock &FMBB, unsigned NumF) const { 116 // FIXME: Catch optimization such as: 117 // r0 = movne 118 // r0 = moveq 119 return NumT && NumF && 120 NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit); 121} 122 123void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 124 MachineBasicBlock::iterator I, DebugLoc DL, 125 unsigned DestReg, unsigned SrcReg, 126 bool KillSrc) const { |
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63 // Handle SPR, DPR, and QPR copies. | 127 // Handle SPR, DPR, and QPR copies. |
64 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC, DL); | 128 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 129 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); 130 131 bool tDest = ARM::tGPRRegClass.contains(DestReg); 132 bool tSrc = ARM::tGPRRegClass.contains(SrcReg); 133 unsigned Opc = ARM::tMOVgpr2gpr; 134 if (tDest && tSrc) 135 Opc = ARM::tMOVr; 136 else if (tSrc) 137 Opc = ARM::tMOVtgpr2gpr; 138 else if (tDest) 139 Opc = ARM::tMOVgpr2tgpr; 140 141 BuildMI(MBB, I, DL, get(Opc), DestReg) 142 .addReg(SrcReg, getKillRegState(KillSrc)); |
65} 66 67void Thumb2InstrInfo:: 68storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 69 unsigned SrcReg, bool isKill, int FI, 70 const TargetRegisterClass *RC, 71 const TargetRegisterInfo *TRI) const { | 143} 144 145void Thumb2InstrInfo:: 146storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 147 unsigned SrcReg, bool isKill, int FI, 148 const TargetRegisterClass *RC, 149 const TargetRegisterInfo *TRI) const { |
72 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { | 150 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 151 RC == ARM::tcGPRRegisterClass) { |
73 DebugLoc DL; 74 if (I != MBB.end()) DL = I->getDebugLoc(); 75 76 MachineFunction &MF = *MBB.getParent(); 77 MachineFrameInfo &MFI = *MF.getFrameInfo(); 78 MachineMemOperand *MMO = 79 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 80 MachineMemOperand::MOStore, 0, --- 8 unchanged lines hidden (view full) --- 89 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 90} 91 92void Thumb2InstrInfo:: 93loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 94 unsigned DestReg, int FI, 95 const TargetRegisterClass *RC, 96 const TargetRegisterInfo *TRI) const { | 152 DebugLoc DL; 153 if (I != MBB.end()) DL = I->getDebugLoc(); 154 155 MachineFunction &MF = *MBB.getParent(); 156 MachineFrameInfo &MFI = *MF.getFrameInfo(); 157 MachineMemOperand *MMO = 158 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 159 MachineMemOperand::MOStore, 0, --- 8 unchanged lines hidden (view full) --- 168 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 169} 170 171void Thumb2InstrInfo:: 172loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 173 unsigned DestReg, int FI, 174 const TargetRegisterClass *RC, 175 const TargetRegisterInfo *TRI) const { |
97 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) { | 176 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 177 RC == ARM::tcGPRRegisterClass) { |
98 DebugLoc DL; 99 if (I != MBB.end()) DL = I->getDebugLoc(); 100 101 MachineFunction &MF = *MBB.getParent(); 102 MachineFrameInfo &MFI = *MF.getFrameInfo(); 103 MachineMemOperand *MMO = 104 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 105 MachineMemOperand::MOLoad, 0, 106 MFI.getObjectSize(FI), 107 MFI.getObjectAlignment(FI)); 108 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) 109 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 110 return; 111 } 112 113 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); 114} 115 | 178 DebugLoc DL; 179 if (I != MBB.end()) DL = I->getDebugLoc(); 180 181 MachineFunction &MF = *MBB.getParent(); 182 MachineFrameInfo &MFI = *MF.getFrameInfo(); 183 MachineMemOperand *MMO = 184 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI), 185 MachineMemOperand::MOLoad, 0, 186 MFI.getObjectSize(FI), 187 MFI.getObjectAlignment(FI)); 188 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) 189 .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); 190 return; 191 } 192 193 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); 194} 195 |
196ScheduleHazardRecognizer *Thumb2InstrInfo:: 197CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const { 198 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II); 199} 200 |
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116void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, 117 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 118 unsigned DestReg, unsigned BaseReg, int NumBytes, 119 ARMCC::CondCodes Pred, unsigned PredReg, 120 const ARMBaseInstrInfo &TII) { 121 bool isSub = NumBytes < 0; 122 if (isSub) NumBytes = -NumBytes; 123 124 // If profitable, use a movw or movt to materialize the offset. 125 // FIXME: Use the scavenger to grab a scratch register. 126 if (DestReg != ARM::SP && DestReg != BaseReg && 127 NumBytes >= 4096 && 128 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 129 bool Fits = false; 130 if (NumBytes < 65536) { 131 // Use a movw to materialize the 16-bit constant. 132 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) 133 .addImm(NumBytes) | 201void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB, 202 MachineBasicBlock::iterator &MBBI, DebugLoc dl, 203 unsigned DestReg, unsigned BaseReg, int NumBytes, 204 ARMCC::CondCodes Pred, unsigned PredReg, 205 const ARMBaseInstrInfo &TII) { 206 bool isSub = NumBytes < 0; 207 if (isSub) NumBytes = -NumBytes; 208 209 // If profitable, use a movw or movt to materialize the offset. 210 // FIXME: Use the scavenger to grab a scratch register. 211 if (DestReg != ARM::SP && DestReg != BaseReg && 212 NumBytes >= 4096 && 213 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 214 bool Fits = false; 215 if (NumBytes < 65536) { 216 // Use a movw to materialize the 16-bit constant. 217 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) 218 .addImm(NumBytes) |
134 .addImm((unsigned)Pred).addReg(PredReg).addReg(0); | 219 .addImm((unsigned)Pred).addReg(PredReg); |
135 Fits = true; 136 } else if ((NumBytes & 0xffff) == 0) { 137 // Use a movt to materialize the 32-bit constant. 138 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) 139 .addReg(DestReg) 140 .addImm(NumBytes >> 16) | 220 Fits = true; 221 } else if ((NumBytes & 0xffff) == 0) { 222 // Use a movt to materialize the 32-bit constant. 223 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) 224 .addReg(DestReg) 225 .addImm(NumBytes >> 16) |
141 .addImm((unsigned)Pred).addReg(PredReg).addReg(0); | 226 .addImm((unsigned)Pred).addReg(PredReg); |
142 Fits = true; 143 } 144 145 if (Fits) { 146 if (isSub) { 147 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) 148 .addReg(BaseReg, RegState::Kill) 149 .addReg(DestReg, RegState::Kill) --- 347 unchanged lines hidden (view full) --- 497 } 498 ImmOp.ChangeToImmediate(ImmedOffset); 499 Offset &= ~(Mask*Scale); 500 } 501 502 Offset = (isSub) ? -Offset : Offset; 503 return Offset == 0; 504} | 227 Fits = true; 228 } 229 230 if (Fits) { 231 if (isSub) { 232 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) 233 .addReg(BaseReg, RegState::Kill) 234 .addReg(DestReg, RegState::Kill) --- 347 unchanged lines hidden (view full) --- 582 } 583 ImmOp.ChangeToImmediate(ImmedOffset); 584 Offset &= ~(Mask*Scale); 585 } 586 587 Offset = (isSub) ? -Offset : Offset; 588 return Offset == 0; 589} |
590 591/// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 592/// two-addrss instruction inserted by two-address pass. 593void 594Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI, 595 MachineInstr *UseMI, 596 const TargetRegisterInfo &TRI) const { 597 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr || 598 SrcMI->getOperand(1).isKill()) 599 return; 600 601 unsigned PredReg = 0; 602 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg); 603 if (CC == ARMCC::AL || PredReg != ARM::CPSR) 604 return; 605 606 // Schedule the copy so it doesn't come between previous instructions 607 // and UseMI which can form an IT block. 608 unsigned SrcReg = SrcMI->getOperand(1).getReg(); 609 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC); 610 MachineBasicBlock *MBB = UseMI->getParent(); 611 MachineBasicBlock::iterator MBBI = SrcMI; 612 unsigned NumInsts = 0; 613 while (--MBBI != MBB->begin()) { 614 if (MBBI->isDebugValue()) 615 continue; 616 617 MachineInstr *NMI = &*MBBI; 618 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg); 619 if (!(NCC == CC || NCC == OCC) || 620 NMI->modifiesRegister(SrcReg, &TRI) || 621 NMI->definesRegister(ARM::CPSR)) 622 break; 623 if (++NumInsts == 4) 624 // Too many in a row! 625 return; 626 } 627 628 if (NumInsts) { 629 MBB->remove(SrcMI); 630 MBB->insert(++MBBI, SrcMI); 631 } 632} 633 634ARMCC::CondCodes 635llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { 636 unsigned Opc = MI->getOpcode(); 637 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) 638 return ARMCC::AL; 639 return llvm::getInstrPredicate(MI, PredReg); 640} |
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