1//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Thumb2InstrInfo.h"
15#include "ARM.h"
16#include "ARMConstantPoolValue.h"
17#include "ARMAddressingModes.h"
18#include "ARMGenInstrInfo.inc"
19#include "ARMMachineFunctionInfo.h"
20#include "llvm/CodeGen/MachineFrameInfo.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineMemOperand.h"
23#include "llvm/CodeGen/PseudoSourceValue.h"
24#include "llvm/ADT/SmallVector.h"
25#include "Thumb2InstrInfo.h"
26
27using namespace llvm;
28
29Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
30 : ARMBaseInstrInfo(STI), RI(*this, STI) {
31}
32
33unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 // FIXME
35 return 0;
36}
37
38bool
39Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator I,
41 unsigned DestReg, unsigned SrcReg,
42 const TargetRegisterClass *DestRC,
43 const TargetRegisterClass *SrcRC,
44 DebugLoc DL) const {
45 if (DestRC == ARM::GPRRegisterClass) {
46 if (SrcRC == ARM::GPRRegisterClass) {
47 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
48 return true;
49 } else if (SrcRC == ARM::tGPRRegisterClass) {
50 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
51 return true;
52 }
53 } else if (DestRC == ARM::tGPRRegisterClass) {
54 if (SrcRC == ARM::GPRRegisterClass) {
55 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
56 return true;
57 } else if (SrcRC == ARM::tGPRRegisterClass) {
58 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
59 return true;
60 }
61 }
62
63 // Handle SPR, DPR, and QPR copies.
64 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC, DL);
65}
66
67void Thumb2InstrInfo::
68storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
69 unsigned SrcReg, bool isKill, int FI,
70 const TargetRegisterClass *RC,
71 const TargetRegisterInfo *TRI) const {
72 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
73 DebugLoc DL;
74 if (I != MBB.end()) DL = I->getDebugLoc();
75
76 MachineFunction &MF = *MBB.getParent();
77 MachineFrameInfo &MFI = *MF.getFrameInfo();
78 MachineMemOperand *MMO =
79 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
80 MachineMemOperand::MOStore, 0,

--- 8 unchanged lines hidden (view full) ---

89 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
90}
91
92void Thumb2InstrInfo::
93loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
94 unsigned DestReg, int FI,
95 const TargetRegisterClass *RC,
96 const TargetRegisterInfo *TRI) const {
97 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass) {
98 DebugLoc DL;
99 if (I != MBB.end()) DL = I->getDebugLoc();
100
101 MachineFunction &MF = *MBB.getParent();
102 MachineFrameInfo &MFI = *MF.getFrameInfo();
103 MachineMemOperand *MMO =
104 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
105 MachineMemOperand::MOLoad, 0,
106 MFI.getObjectSize(FI),
107 MFI.getObjectAlignment(FI));
108 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
109 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
110 return;
111 }
112
113 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
114}
115
116void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
117 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
118 unsigned DestReg, unsigned BaseReg, int NumBytes,
119 ARMCC::CondCodes Pred, unsigned PredReg,
120 const ARMBaseInstrInfo &TII) {
121 bool isSub = NumBytes < 0;
122 if (isSub) NumBytes = -NumBytes;
123
124 // If profitable, use a movw or movt to materialize the offset.
125 // FIXME: Use the scavenger to grab a scratch register.
126 if (DestReg != ARM::SP && DestReg != BaseReg &&
127 NumBytes >= 4096 &&
128 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
129 bool Fits = false;
130 if (NumBytes < 65536) {
131 // Use a movw to materialize the 16-bit constant.
132 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
133 .addImm(NumBytes)
134 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
135 Fits = true;
136 } else if ((NumBytes & 0xffff) == 0) {
137 // Use a movt to materialize the 32-bit constant.
138 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
139 .addReg(DestReg)
140 .addImm(NumBytes >> 16)
141 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
142 Fits = true;
143 }
144
145 if (Fits) {
146 if (isSub) {
147 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
148 .addReg(BaseReg, RegState::Kill)
149 .addReg(DestReg, RegState::Kill)

--- 347 unchanged lines hidden (view full) ---

497 }
498 ImmOp.ChangeToImmediate(ImmedOffset);
499 Offset &= ~(Mask*Scale);
500 }
501
502 Offset = (isSub) ? -Offset : Offset;
503 return Offset == 0;
504}