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ARMScheduleV6.td (208954) ARMScheduleV6.td (210299)
1//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v6 processors.
11//
12//===----------------------------------------------------------------------===//
13
14// Model based on ARM1176
15//
16// Functional Units
17def V6_Pipe : FuncUnit; // pipeline
18
1//===- ARMScheduleV6.td - ARM v6 Scheduling Definitions ----*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the ARM v6 processors.
11//
12//===----------------------------------------------------------------------===//
13
14// Model based on ARM1176
15//
16// Functional Units
17def V6_Pipe : FuncUnit; // pipeline
18
19// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual".
19// Scheduling information derived from "ARM1176JZF-S Technical Reference Manual"
20//
21def ARMV6Itineraries : ProcessorItineraries<
22 [V6_Pipe], [
23 //
24 // No operand cycles
25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
26 //
27 // Binary Instructions that produce a result

--- 177 unchanged lines hidden --- 		20//
21def ARMV6Itineraries : ProcessorItineraries<
22 [V6_Pipe], [
23 //
24 // No operand cycles
25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
26 //
27 // Binary Instructions that produce a result

--- 177 unchanged lines hidden ---