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ARMInstrThumb.td (223017) ARMInstrThumb.td (224145)
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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21
22def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24}]>;
25def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
27}]>;
28
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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21
22def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24}]>;
25def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
27}]>;
28
29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30def imm0_7 : ImmLeaf<i32, [{
31 return Imm >= 0 && Imm < 8;
32}]>;
33def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
35}], imm_neg_XFORM>;
36
29def imm0_7_neg : PatLeaf<(i32 imm), [{
30 return (uint32_t)-N->getZExtValue() < 8;
31}], imm_neg_XFORM>;
32
37def imm0_255 : ImmLeaf<i32, [{
38 return Imm >= 0 && Imm < 256;
39}]>;
33def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
34def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
35 let ParserMatchClass = imm0_255_asmoperand;
36}
40def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
42}]>;
43
44def imm8_255 : ImmLeaf<i32, [{
45 return Imm >= 8 && Imm < 256;
46}]>;
47def imm8_255_neg : PatLeaf<(i32 imm), [{

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69// ADR instruction labels.
70def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
72}
73
74// Scaled 4 immediate.
75def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
37def imm0_255_comp : PatLeaf<(i32 imm), [{
38 return ~((uint32_t)N->getZExtValue()) < 256;
39}]>;
40
41def imm8_255 : ImmLeaf<i32, [{
42 return Imm >= 8 && Imm < 256;
43}]>;
44def imm8_255_neg : PatLeaf<(i32 imm), [{

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66// ADR instruction labels.
67def t_adrlabel : Operand<i32> {
68 let EncoderMethod = "getThumbAdrLabelOpValue";
69}
70
71// Scaled 4 immediate.
72def t_imm_s4 : Operand<i32> {
73 let PrintMethod = "printThumbS4ImmOperand";
74 let OperandType = "OPERAND_IMMEDIATE";
77}
78
79// Define Thumb specific addressing modes.
80
75}
76
77// Define Thumb specific addressing modes.
78
79let OperandType = "OPERAND_PCREL" in {
81def t_brtarget : Operand<OtherVT> {
82 let EncoderMethod = "getThumbBRTargetOpValue";
83}
84
85def t_bcctarget : Operand<i32> {
86 let EncoderMethod = "getThumbBCCTargetOpValue";
87}
88
89def t_cbtarget : Operand<i32> {
90 let EncoderMethod = "getThumbCBTargetOpValue";
91}
92
93def t_bltarget : Operand<i32> {
94 let EncoderMethod = "getThumbBLTargetOpValue";
95}
96
97def t_blxtarget : Operand<i32> {
98 let EncoderMethod = "getThumbBLXTargetOpValue";
99}
80def t_brtarget : Operand<OtherVT> {
81 let EncoderMethod = "getThumbBRTargetOpValue";
82}
83
84def t_bcctarget : Operand<i32> {
85 let EncoderMethod = "getThumbBCCTargetOpValue";
86}
87
88def t_cbtarget : Operand<i32> {
89 let EncoderMethod = "getThumbCBTargetOpValue";
90}
91
92def t_bltarget : Operand<i32> {
93 let EncoderMethod = "getThumbBLTargetOpValue";
94}
95
96def t_blxtarget : Operand<i32> {
97 let EncoderMethod = "getThumbBLXTargetOpValue";
98}
99}
100
101def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
104}
105
106def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";

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355 let Inst{6-3} = dst;
356 let Inst{2-0} = 0b101;
357}
358
359//===----------------------------------------------------------------------===//
360// Control Flow Instructions.
361//
362
100
101def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
104}
105
106def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";

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355 let Inst{6-3} = dst;
356 let Inst{2-0} = 0b101;
357}
358
359//===----------------------------------------------------------------------===//
360// Control Flow Instructions.
361//
362
363let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
364 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
365 [(ARMretflag)]>,
366 T1Special<{1,1,0,?}> {
367 // A6.2.3 & A8.6.25
368 let Inst{6-3} = 0b1110; // Rm = lr
369 let Inst{2-0} = 0b000;
370 }
371
372 // Alternative return instruction used by vararg functions.
373 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
374 IIC_Br, "bx\t$Rm",
375 []>,
376 T1Special<{1,1,0,?}> {
377 // A6.2.3 & A8.6.25
378 bits<4> Rm;
379 let Inst{6-3} = Rm;
380 let Inst{2-0} = 0b000;
381 }
382}
383
384// Indirect branches
385let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
386 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
387 T1Special<{1,1,0,?}> {
388 // A6.2.3 & A8.6.25
389 bits<4> Rm;
390 let Inst{6-3} = Rm;
391 let Inst{2-0} = 0b000;
392 }
363// Indirect branches
364let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
365 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
366 T1Special<{1,1,0,?}> {
367 // A6.2.3 & A8.6.25
368 bits<4> Rm;
369 let Inst{6-3} = Rm;
370 let Inst{2-0} = 0b000;
371 }
393
394 def tBRIND : TI<(outs), (ins GPR:$Rm),
395 IIC_Br,
396 "mov\tpc, $Rm",
397 [(brind GPR:$Rm)]>,
398 T1Special<{1,0,?,?}> {
399 // A8.6.97
400 bits<4> Rm;
401 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
402 let Inst{6-3} = Rm;
403 let Inst{2-0} = 0b111;
404 }
405}
406
372}
373
407// FIXME: remove when we have a way to marking a MI with these properties.
408let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
409 hasExtraDefRegAllocReq = 1 in
410def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
411 IIC_iPop_Br,
412 "pop${p}\t$regs", []>,
413 T1Misc<{1,1,0,?,?,?,?}> {
414 // A8.6.121
415 bits<16> regs;
416 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
417 let Inst{7-0} = regs{7-0};
374let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
375 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
376 [(ARMretflag)], (tBX LR, pred:$p)>;
377
378 // Alternative return instruction used by vararg functions.
379 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
380 2, IIC_Br, [],
381 (tBX GPR:$Rm, pred:$p)>;
418}
419
420// All calls clobber the non-callee saved registers. SP is marked as a use to
421// prevent stack-pointer assignments that appear immediately before calls from
422// potentially appearing dead.
423let isCall = 1,
424 // On non-Darwin platforms R9 is callee-saved.
425 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],

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459 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
460 bits<4> func;
461 let Inst{6-3} = func;
462 let Inst{2-0} = 0b000;
463 }
464
465 // ARMv4T
466 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
382}
383
384// All calls clobber the non-callee saved registers. SP is marked as a use to
385// prevent stack-pointer assignments that appear immediately before calls from
386// potentially appearing dead.
387let isCall = 1,
388 // On non-Darwin platforms R9 is callee-saved.
389 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],

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423 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
424 bits<4> func;
425 let Inst{6-3} = func;
426 let Inst{2-0} = 0b000;
427 }
428
429 // ARMv4T
430 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
467 Size4Bytes, IIC_Br,
431 4, IIC_Br,
468 [(ARMcall_nolink tGPR:$func)]>,
469 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
470}
471
472let isCall = 1,
473 // On Darwin R9 is call-clobbered.
474 // R7 is marked as a use to prevent frame-pointer assignments from being
475 // moved above / below calls.

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511 // A6.2.3 & A8.6.24
512 bits<4> func;
513 let Inst{6-3} = func;
514 let Inst{2-0} = 0b000;
515 }
516
517 // ARMv4T
518 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
432 [(ARMcall_nolink tGPR:$func)]>,
433 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
434}
435
436let isCall = 1,
437 // On Darwin R9 is call-clobbered.
438 // R7 is marked as a use to prevent frame-pointer assignments from being
439 // moved above / below calls.

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475 // A6.2.3 & A8.6.24
476 bits<4> func;
477 let Inst{6-3} = func;
478 let Inst{2-0} = 0b000;
479 }
480
481 // ARMv4T
482 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
519 Size4Bytes, IIC_Br,
483 4, IIC_Br,
520 [(ARMcall_nolink tGPR:$func)]>,
521 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
522}
523
524let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
525 let isPredicable = 1 in
526 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
527 "b\t$target", [(br bb:$target)]>,
528 T1Encoding<{1,1,1,0,0,?}> {
529 bits<11> target;
530 let Inst{10-0} = target;
531 }
532
533 // Far jump
534 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
535 // the clobber of LR.
536 let Defs = [LR] in
484 [(ARMcall_nolink tGPR:$func)]>,
485 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
486}
487
488let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
489 let isPredicable = 1 in
490 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
491 "b\t$target", [(br bb:$target)]>,
492 T1Encoding<{1,1,1,0,0,?}> {
493 bits<11> target;
494 let Inst{10-0} = target;
495 }
496
497 // Far jump
498 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
499 // the clobber of LR.
500 let Defs = [LR] in
537 def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
538 Size4Bytes, IIC_Br, []>;
501 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target),
502 4, IIC_Br, [], (tBL t_bltarget:$target)>;
539
540 def tBR_JTr : tPseudoInst<(outs),
541 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
503
504 def tBR_JTr : tPseudoInst<(outs),
505 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
542 SizeSpecial, IIC_Br,
506 0, IIC_Br,
543 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
544 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
545 }
546}
547
548// FIXME: should be able to write a pattern for ARMBrcond, but can't use
549// a two-value operand where a dag node expects two operands. :(
550let isBranch = 1, isTerminator = 1 in

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578 bits<6> target;
579 bits<3> Rn;
580 let Inst{9} = target{5};
581 let Inst{7-3} = target{4-0};
582 let Inst{2-0} = Rn;
583 }
584}
585
507 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
508 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
509 }
510}
511
512// FIXME: should be able to write a pattern for ARMBrcond, but can't use
513// a two-value operand where a dag node expects two operands. :(
514let isBranch = 1, isTerminator = 1 in

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542 bits<6> target;
543 bits<3> Rn;
544 let Inst{9} = target{5};
545 let Inst{7-3} = target{4-0};
546 let Inst{2-0} = Rn;
547 }
548}
549
550// Tail calls
551let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
552 // Darwin versions.
553 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
554 Uses = [SP] in {
555 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
556 // on Darwin), so it's in ARMInstrThumb2.td.
557 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
558 4, IIC_Br, [],
559 (tBX GPR:$dst, (ops 14, zero_reg))>,
560 Requires<[IsThumb, IsDarwin]>;
561 }
562 // Non-Darwin versions (the difference is R9).
563 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
564 Uses = [SP] in {
565 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
566 4, IIC_Br, [],
567 (tB t_brtarget:$dst)>,
568 Requires<[IsThumb, IsNotDarwin]>;
569 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
570 4, IIC_Br, [],
571 (tBX GPR:$dst, (ops 14, zero_reg))>,
572 Requires<[IsThumb, IsNotDarwin]>;
573 }
574}
575
576
586// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
587// A8.6.16 B: Encoding T1
588// If Inst{11-8} == 0b1111 then SEE SVC
589let isCall = 1, Uses = [SP] in
590def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
591 "svc", "\t$imm", []>, Encoding16 {
592 bits<8> imm;
593 let Inst{15-12} = 0b1101;

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680 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
681 T1LdStSP<{1,?,?}> {
682 bits<3> Rt;
683 bits<8> addr;
684 let Inst{10-8} = Rt;
685 let Inst{7-0} = addr;
686}
687
577// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
578// A8.6.16 B: Encoding T1
579// If Inst{11-8} == 0b1111 then SEE SVC
580let isCall = 1, Uses = [SP] in
581def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
582 "svc", "\t$imm", []>, Encoding16 {
583 bits<8> imm;
584 let Inst{15-12} = 0b1101;

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671 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
672 T1LdStSP<{1,?,?}> {
673 bits<3> Rt;
674 bits<8> addr;
675 let Inst{10-8} = Rt;
676 let Inst{7-0} = addr;
677}
678
688// Special instruction for restore. It cannot clobber condition register
689// when it's expanded by eliminateCallFramePseudoInstr().
690let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
691// FIXME: Pseudo for tLDRspi
692def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
693 "ldr", "\t$dst, $addr", []>,
694 T1LdStSP<{1,?,?}> {
695 bits<3> Rt;
696 bits<8> addr;
697 let Inst{10-8} = Rt;
698 let Inst{7-0} = addr;
699}
700
701// Load tconstpool
702// FIXME: Use ldr.n to work around a Darwin assembler bug.
703let canFoldAsLoad = 1, isReMaterializable = 1 in
704def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
705 "ldr", ".n\t$Rt, $addr",
706 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
707 T1Encoding<{0,1,0,0,1,?}> {
708 // A6.2 & A8.6.59

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734// A8.6.197 & A8.6.195
735defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
736 t_addrmode_is1, AddrModeT1_1,
737 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
738 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
739
740// A8.6.207 & A8.6.205
741defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
679// Load tconstpool
680// FIXME: Use ldr.n to work around a Darwin assembler bug.
681let canFoldAsLoad = 1, isReMaterializable = 1 in
682def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
683 "ldr", ".n\t$Rt, $addr",
684 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
685 T1Encoding<{0,1,0,0,1,?}> {
686 // A6.2 & A8.6.59

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712// A8.6.197 & A8.6.195
713defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
714 t_addrmode_is1, AddrModeT1_1,
715 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
716 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
717
718// A8.6.207 & A8.6.205
719defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
742 t_addrmode_is2, AddrModeT1_2,
743 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
744 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
720 t_addrmode_is2, AddrModeT1_2,
721 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
722 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
745
746
747def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
748 "str", "\t$Rt, $addr",
749 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
750 T1LdStSP<{0,?,?}> {
751 bits<3> Rt;
752 bits<8> addr;
753 let Inst{10-8} = Rt;
754 let Inst{7-0} = addr;
755}
756
723
724
725def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
726 "str", "\t$Rt, $addr",
727 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
728 T1LdStSP<{0,?,?}> {
729 bits<3> Rt;
730 bits<8> addr;
731 let Inst{10-8} = Rt;
732 let Inst{7-0} = addr;
733}
734
757let mayStore = 1, neverHasSideEffects = 1 in
758// Special instruction for spill. It cannot clobber condition register when it's
759// expanded by eliminateCallFramePseudoInstr().
760// FIXME: Pseudo for tSTRspi
761def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
762 "str", "\t$src, $addr", []>,
763 T1LdStSP<{0,?,?}> {
764 bits<3> Rt;
765 bits<8> addr;
766 let Inst{10-8} = Rt;
767 let Inst{7-0} = addr;
768}
769
770//===----------------------------------------------------------------------===//
771// Load / store multiple Instructions.
772//
773
774multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
775 InstrItinClass itin_upd, bits<6> T1Enc,
776 bit L_bit> {
777 def IA :

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906let isCommutable = 1, Uses = [CPSR] in
907def tADC : // A8.6.2
908 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
909 "adc", "\t$Rdn, $Rm",
910 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
911
912// Add immediate
913def tADDi3 : // A8.6.4 T1
735//===----------------------------------------------------------------------===//
736// Load / store multiple Instructions.
737//
738
739multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
740 InstrItinClass itin_upd, bits<6> T1Enc,
741 bit L_bit> {
742 def IA :

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871let isCommutable = 1, Uses = [CPSR] in
872def tADC : // A8.6.2
873 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
874 "adc", "\t$Rdn, $Rm",
875 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
876
877// Add immediate
878def tADDi3 : // A8.6.4 T1
914 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
879 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
880 IIC_iALUi,
915 "add", "\t$Rd, $Rm, $imm3",
916 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
917 bits<3> imm3;
918 let Inst{8-6} = imm3;
919}
920
921def tADDi8 : // A8.6.4 T2
922 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),

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1066def tLSRrr : // A8.6.91
1067 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1068 IIC_iMOVsr,
1069 "lsr", "\t$Rdn, $Rm",
1070 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1071
1072// Move register
1073let isMoveImm = 1 in
881 "add", "\t$Rd, $Rm, $imm3",
882 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
883 bits<3> imm3;
884 let Inst{8-6} = imm3;
885}
886
887def tADDi8 : // A8.6.4 T2
888 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),

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1032def tLSRrr : // A8.6.91
1033 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1034 IIC_iMOVsr,
1035 "lsr", "\t$Rdn, $Rm",
1036 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1037
1038// Move register
1039let isMoveImm = 1 in
1074def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1040def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1075 "mov", "\t$Rd, $imm8",
1076 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1077 T1General<{1,0,0,?,?}> {
1078 // A8.6.96
1079 bits<3> Rd;
1080 bits<8> imm8;
1081 let Inst{10-8} = Rd;
1082 let Inst{7-0} = imm8;
1083}
1084
1041 "mov", "\t$Rd, $imm8",
1042 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1043 T1General<{1,0,0,?,?}> {
1044 // A8.6.96
1045 bits<3> Rd;
1046 bits<8> imm8;
1047 let Inst{10-8} = Rd;
1048 let Inst{7-0} = imm8;
1049}
1050
1085// TODO: A7-73: MOV(2) - mov setting flag.
1051// A7-73: MOV(2) - mov setting flag.
1086
1087let neverHasSideEffects = 1 in {
1052
1053let neverHasSideEffects = 1 in {
1088// FIXME: Make this predicable.
1089def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1090 "mov\t$Rd, $Rm", []>,
1091 T1Special<0b1000> {
1054def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1055 2, IIC_iMOVr,
1056 "mov", "\t$Rd, $Rm", "", []>,
1057 T1Special<{1,0,?,?}> {
1092 // A8.6.97
1093 bits<4> Rd;
1094 bits<4> Rm;
1058 // A8.6.97
1059 bits<4> Rd;
1060 bits<4> Rm;
1095 // Bits {7-6} are encoded by the T1Special value.
1096 let Inst{5-3} = Rm{2-0};
1061 let Inst{7} = Rd{3};
1062 let Inst{6-3} = Rm;
1097 let Inst{2-0} = Rd{2-0};
1098}
1099let Defs = [CPSR] in
1100def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1101 "movs\t$Rd, $Rm", []>, Encoding16 {
1102 // A8.6.97
1103 bits<3> Rd;
1104 bits<3> Rm;
1105 let Inst{15-6} = 0b0000000000;
1106 let Inst{5-3} = Rm;
1107 let Inst{2-0} = Rd;
1108}
1063 let Inst{2-0} = Rd{2-0};
1064}
1065let Defs = [CPSR] in
1066def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1067 "movs\t$Rd, $Rm", []>, Encoding16 {
1068 // A8.6.97
1069 bits<3> Rd;
1070 bits<3> Rm;
1071 let Inst{15-6} = 0b0000000000;
1072 let Inst{5-3} = Rm;
1073 let Inst{2-0} = Rd;
1074}
1109
1110// FIXME: Make these predicable.
1111def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1112 "mov\t$Rd, $Rm", []>,
1113 T1Special<{1,0,0,?}> {
1114 // A8.6.97
1115 bits<4> Rd;
1116 bits<4> Rm;
1117 // Bit {7} is encoded by the T1Special value.
1118 let Inst{6-3} = Rm;
1119 let Inst{2-0} = Rd{2-0};
1120}
1121def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1122 "mov\t$Rd, $Rm", []>,
1123 T1Special<{1,0,?,0}> {
1124 // A8.6.97
1125 bits<4> Rd;
1126 bits<4> Rm;
1127 // Bit {6} is encoded by the T1Special value.
1128 let Inst{7} = Rd{3};
1129 let Inst{5-3} = Rm{2-0};
1130 let Inst{2-0} = Rd{2-0};
1131}
1132def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1133 "mov\t$Rd, $Rm", []>,
1134 T1Special<{1,0,?,?}> {
1135 // A8.6.97
1136 bits<4> Rd;
1137 bits<4> Rm;
1138 let Inst{7} = Rd{3};
1139 let Inst{6-3} = Rm;
1140 let Inst{2-0} = Rd{2-0};
1141}
1142} // neverHasSideEffects
1143
1144// Multiply register
1145let isCommutable = 1 in
1146def tMUL : // A8.6.105 T1
1147 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1148 IIC_iMUL32,
1149 "mul", "\t$Rdn, $Rm, $Rdn",

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1170 "rev", "\t$Rd, $Rm",
1171 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1172 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173
1174def tREV16 : // A8.6.135
1175 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1176 IIC_iUNAr,
1177 "rev16", "\t$Rd, $Rm",
1075} // neverHasSideEffects
1076
1077// Multiply register
1078let isCommutable = 1 in
1079def tMUL : // A8.6.105 T1
1080 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1081 IIC_iMUL32,
1082 "mul", "\t$Rdn, $Rm, $Rdn",

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1103 "rev", "\t$Rd, $Rm",
1104 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1105 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1106
1107def tREV16 : // A8.6.135
1108 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1109 IIC_iUNAr,
1110 "rev16", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd,
1179 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1180 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1181 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1182 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1111 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1183 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1184
1185def tREVSH : // A8.6.136
1186 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1187 IIC_iUNAr,
1188 "revsh", "\t$Rd, $Rm",
1112 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1113
1114def tREVSH : // A8.6.136
1115 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1116 IIC_iUNAr,
1117 "revsh", "\t$Rd, $Rm",
1189 [(set tGPR:$Rd,
1190 (sext_inreg
1191 (or (srl tGPR:$Rm, (i32 8)),
1192 (shl tGPR:$Rm, (i32 8))), i16))]>,
1118 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1193 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1194
1119 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1120
1195def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1196 (shl tGPR:$Rm, (i32 8))), i16),
1197 (tREVSH tGPR:$Rm)>,
1198 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1199
1200def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
1201 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1202
1203// Rotate right register
1204def tROR : // A8.6.139
1205 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1206 IIC_iMOVsr,
1207 "ror", "\t$Rdn, $Rm",
1208 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1209
1210// Negate register

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1289// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1290// Expanded after instruction selection into a branch sequence.
1291let usesCustomInserter = 1 in // Expanded after instruction selection.
1292 def tMOVCCr_pseudo :
1293 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1294 NoItinerary,
1295 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1296
1121// Rotate right register
1122def tROR : // A8.6.139
1123 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1124 IIC_iMOVsr,
1125 "ror", "\t$Rdn, $Rm",
1126 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1127
1128// Negate register

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1207// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1208// Expanded after instruction selection into a branch sequence.
1209let usesCustomInserter = 1 in // Expanded after instruction selection.
1210 def tMOVCCr_pseudo :
1211 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1212 NoItinerary,
1213 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1214
1297
1298// 16-bit movcc in IT blocks for Thumb2.
1299let neverHasSideEffects = 1 in {
1300def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1301 "mov", "\t$Rdn, $Rm", []>,
1302 T1Special<{1,0,?,?}> {
1303 bits<4> Rdn;
1304 bits<4> Rm;
1305 let Inst{7} = Rdn{3};
1306 let Inst{6-3} = Rm;
1307 let Inst{2-0} = Rdn{2-0};
1308}
1309
1310let isMoveImm = 1 in
1311def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1312 "mov", "\t$Rdn, $Rm", []>,
1313 T1General<{1,0,0,?,?}> {
1314 bits<3> Rdn;
1315 bits<8> Rm;
1316 let Inst{10-8} = Rdn;
1317 let Inst{7-0} = Rm;
1318}
1319
1320} // neverHasSideEffects
1321
1322// tLEApcrel - Load a pc-relative address into a register without offending the
1323// assembler.
1324
1325def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1326 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1327 T1Encoding<{1,0,1,0,0,?}> {
1328 bits<3> Rd;
1329 bits<8> addr;
1330 let Inst{10-8} = Rd;
1331 let Inst{7-0} = addr;
1332}
1333
1334let neverHasSideEffects = 1, isReMaterializable = 1 in
1335def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1215// tLEApcrel - Load a pc-relative address into a register without offending the
1216// assembler.
1217
1218def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1219 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1220 T1Encoding<{1,0,1,0,0,?}> {
1221 bits<3> Rd;
1222 bits<8> addr;
1223 let Inst{10-8} = Rd;
1224 let Inst{7-0} = addr;
1225}
1226
1227let neverHasSideEffects = 1, isReMaterializable = 1 in
1228def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1336 Size2Bytes, IIC_iALUi, []>;
1229 2, IIC_iALUi, []>;
1337
1338def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1339 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1230
1231def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1232 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1340 Size2Bytes, IIC_iALUi, []>;
1233 2, IIC_iALUi, []>;
1341
1342//===----------------------------------------------------------------------===//
1234
1235//===----------------------------------------------------------------------===//
1343// Move between coprocessor and ARM core register -- for disassembly only
1344//
1345
1346class tMovRCopro<string opc, bit direction, dag oops, dag iops,
1347 list<dag> pattern>
1348 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1349 pattern> {
1350 let Inst{27-24} = 0b1110;
1351 let Inst{20} = direction;
1352 let Inst{4} = 1;
1353
1354 bits<4> Rt;
1355 bits<4> cop;
1356 bits<3> opc1;
1357 bits<3> opc2;
1358 bits<4> CRm;
1359 bits<4> CRn;
1360
1361 let Inst{15-12} = Rt;
1362 let Inst{11-8} = cop;
1363 let Inst{23-21} = opc1;
1364 let Inst{7-5} = opc2;
1365 let Inst{3-0} = CRm;
1366 let Inst{19-16} = CRn;
1367}
1368
1369def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1370 (outs),
1371 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1372 c_imm:$CRm, i32imm:$opc2),
1373 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1374 imm:$CRm, imm:$opc2)]>;
1375def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1376 (outs GPR:$Rt),
1377 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1378 []>;
1379
1380def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
1381 (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
1382 Requires<[IsThumb, HasV6T2]>;
1383
1384class tMovRRCopro<string opc, bit direction,
1385 list<dag> pattern = [/* For disassembly only */]>
1386 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1387 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
1388 let Inst{27-24} = 0b1100;
1389 let Inst{23-21} = 0b010;
1390 let Inst{20} = direction;
1391
1392 bits<4> Rt;
1393 bits<4> Rt2;
1394 bits<4> cop;
1395 bits<4> opc1;
1396 bits<4> CRm;
1397
1398 let Inst{15-12} = Rt;
1399 let Inst{19-16} = Rt2;
1400 let Inst{11-8} = cop;
1401 let Inst{7-4} = opc1;
1402 let Inst{3-0} = CRm;
1403}
1404
1405def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
1406 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
1407 imm:$CRm)]>;
1408def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1409
1410//===----------------------------------------------------------------------===//
1411// Other Coprocessor Instructions. For disassembly only.
1412//
1413def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1414 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1415 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1416 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1417 imm:$CRm, imm:$opc2)]> {
1418 let Inst{27-24} = 0b1110;
1419
1420 bits<4> opc1;
1421 bits<4> CRn;
1422 bits<4> CRd;
1423 bits<4> cop;
1424 bits<3> opc2;
1425 bits<4> CRm;
1426
1427 let Inst{3-0} = CRm;
1428 let Inst{4} = 0;
1429 let Inst{7-5} = opc2;
1430 let Inst{11-8} = cop;
1431 let Inst{15-12} = CRd;
1432 let Inst{19-16} = CRn;
1433 let Inst{23-20} = opc1;
1434}
1435
1436//===----------------------------------------------------------------------===//
1437// TLS Instructions
1438//
1439
1440// __aeabi_read_tp preserves the registers r1-r3.
1236// TLS Instructions
1237//
1238
1239// __aeabi_read_tp preserves the registers r1-r3.
1441let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1442def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1443 "bl\t__aeabi_read_tp",
1444 [(set R0, ARMthread_pointer)]> {
1445 // Encoding is 0xf7fffffe.
1446 let Inst = 0xf7fffffe;
1447}
1240// This is a pseudo inst so that we can get the encoding right,
1241// complete with fixup for the aeabi_read_tp function.
1242let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1243def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1244 [(set R0, ARMthread_pointer)]>;
1448
1449//===----------------------------------------------------------------------===//
1450// SJLJ Exception handling intrinsics
1451//
1452
1453// eh_sjlj_setjmp() is an instruction sequence to store the return address and
1454// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1455// from some other function to get here, and we're using the stack frame for the
1456// containing function to save/restore registers, we can't keep anything live in
1457// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1458// tromped upon when we get here from a longjmp(). We force everything out of
1459// registers except for our own input by listing the relevant registers in
1460// Defs. By doing so, we also cause the prologue/epilogue code to actively
1461// preserve all of the callee-saved resgisters, which is exactly what we want.
1462// $val is a scratch register for our use.
1463let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1464 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1465def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1245
1246//===----------------------------------------------------------------------===//
1247// SJLJ Exception handling intrinsics
1248//
1249
1250// eh_sjlj_setjmp() is an instruction sequence to store the return address and
1251// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1252// from some other function to get here, and we're using the stack frame for the
1253// containing function to save/restore registers, we can't keep anything live in
1254// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1255// tromped upon when we get here from a longjmp(). We force everything out of
1256// registers except for our own input by listing the relevant registers in
1257// Defs. By doing so, we also cause the prologue/epilogue code to actively
1258// preserve all of the callee-saved resgisters, which is exactly what we want.
1259// $val is a scratch register for our use.
1260let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1261 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1262def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1466 AddrModeNone, SizeSpecial, NoItinerary, "","",
1263 AddrModeNone, 0, NoItinerary, "","",
1467 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1468
1469// FIXME: Non-Darwin version(s)
1470let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1471 Defs = [ R7, LR, SP ] in
1472def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1264 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1265
1266// FIXME: Non-Darwin version(s)
1267let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1268 Defs = [ R7, LR, SP ] in
1269def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1473 AddrModeNone, SizeSpecial, IndexModeNone,
1270 AddrModeNone, 0, IndexModeNone,
1474 Pseudo, NoItinerary, "", "",
1475 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1476 Requires<[IsThumb, IsDarwin]>;
1477
1478//===----------------------------------------------------------------------===//
1479// Non-Instruction Patterns
1480//
1481

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1578// be expanded into two instructions late to allow if-conversion and
1579// scheduling.
1580let isReMaterializable = 1 in
1581def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1582 NoItinerary,
1583 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1584 imm:$cp))]>,
1585 Requires<[IsThumb, IsThumb1Only]>;
1271 Pseudo, NoItinerary, "", "",
1272 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1273 Requires<[IsThumb, IsDarwin]>;
1274
1275//===----------------------------------------------------------------------===//
1276// Non-Instruction Patterns
1277//
1278

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1375// be expanded into two instructions late to allow if-conversion and
1376// scheduling.
1377let isReMaterializable = 1 in
1378def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1379 NoItinerary,
1380 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1381 imm:$cp))]>,
1382 Requires<[IsThumb, IsThumb1Only]>;
1383
1384// Pseudo-instruction for merged POP and return.
1385// FIXME: remove when we have a way to marking a MI with these properties.
1386let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1387 hasExtraDefRegAllocReq = 1 in
1388def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1389 2, IIC_iPop_Br, [],
1390 (tPOP pred:$p, reglist:$regs)>;
1391
1392// Indirect branch using "mov pc, $Rm"
1393let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1394 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1395 2, IIC_Br, [(brind GPR:$Rm)],
1396 (tMOVr PC, GPR:$Rm, pred:$p)>;
1397}