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AArch64SchedA57WriteRes.td (276479) AArch64SchedA57WriteRes.td (280031)
1//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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23//===----------------------------------------------------------------------===//
24// Define Generic 1 micro-op types
25
26def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
1//=- AArch64SchedA57WriteRes.td - ARM Cortex-A57 Write Res ---*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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23//===----------------------------------------------------------------------===//
24// Define Generic 1 micro-op types
25
26def A57Write_5cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 5; }
27def A57Write_5cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 5; }
28def A57Write_5cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 5; }
29def A57Write_5cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 5; }
30def A57Write_10cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 10; }
31def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18; }
32def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; }
31def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
32 let ResourceCycles = [18]; }
33def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
34 let ResourceCycles = [19]; }
33def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
34def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
35def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
36def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
35def A57Write_1cyc_1B : SchedWriteRes<[A57UnitB]> { let Latency = 1; }
36def A57Write_1cyc_1I : SchedWriteRes<[A57UnitI]> { let Latency = 1; }
37def A57Write_1cyc_1S : SchedWriteRes<[A57UnitS]> { let Latency = 1; }
38def A57Write_2cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 2; }
37def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; }
38def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; }
39def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
40 let ResourceCycles = [32]; }
41def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
42 let ResourceCycles = [35]; }
39def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
40def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
41def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
42def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
43def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
44def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
45def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
46def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
47def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
48
49
50//===----------------------------------------------------------------------===//
51// Define Generic 2 micro-op types
52
53def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
54 let Latency = 64;
55 let NumMicroOps = 2;
43def A57Write_3cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 3; }
44def A57Write_3cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 3; }
45def A57Write_3cyc_1W : SchedWriteRes<[A57UnitW]> { let Latency = 3; }
46def A57Write_3cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 3; }
47def A57Write_4cyc_1L : SchedWriteRes<[A57UnitL]> { let Latency = 4; }
48def A57Write_4cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
49def A57Write_9cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 9; }
50def A57Write_6cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 6; }
51def A57Write_6cyc_1V : SchedWriteRes<[A57UnitV]> { let Latency = 6; }
52
53
54//===----------------------------------------------------------------------===//
55// Define Generic 2 micro-op types
56
57def A57Write_64cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
58 let Latency = 64;
59 let NumMicroOps = 2;
60 let ResourceCycles = [32, 32];
56}
57def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
58 A57UnitL]> {
59 let Latency = 6;
60 let NumMicroOps = 2;
61}
62def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
63 A57UnitX]> {

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132}
133def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
134 let Latency = 2;
135 let NumMicroOps = 2;
136}
137def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
138 let Latency = 36;
139 let NumMicroOps = 2;
61}
62def A57Write_6cyc_1I_1L : SchedWriteRes<[A57UnitI,
63 A57UnitL]> {
64 let Latency = 6;
65 let NumMicroOps = 2;
66}
67def A57Write_7cyc_1V_1X : SchedWriteRes<[A57UnitV,
68 A57UnitX]> {

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137}
138def A57Write_2cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
139 let Latency = 2;
140 let NumMicroOps = 2;
141}
142def A57Write_36cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
143 let Latency = 36;
144 let NumMicroOps = 2;
145 let ResourceCycles = [18, 18];
140}
141def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
142 A57UnitM]> {
143 let Latency = 3;
144 let NumMicroOps = 2;
145}
146def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
147 A57UnitS]> {
148 let Latency = 3;
149 let NumMicroOps = 2;
150}
151def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
152 A57UnitV]> {
153 let Latency = 3;
154 let NumMicroOps = 2;
155}
146}
147def A57Write_3cyc_1I_1M : SchedWriteRes<[A57UnitI,
148 A57UnitM]> {
149 let Latency = 3;
150 let NumMicroOps = 2;
151}
152def A57Write_3cyc_1I_1S : SchedWriteRes<[A57UnitI,
153 A57UnitS]> {
154 let Latency = 3;
155 let NumMicroOps = 2;
156}
157def A57Write_3cyc_1S_1V : SchedWriteRes<[A57UnitS,
158 A57UnitV]> {
159 let Latency = 3;
160 let NumMicroOps = 2;
161}
162def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
163 let Latency = 3;
164 let NumMicroOps = 2;
165}
156def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
157 A57UnitL]> {
158 let Latency = 4;
159 let NumMicroOps = 2;
160}
161def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
162 let Latency = 4;
163 let NumMicroOps = 2;

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290 let Latency = 9;
291 let NumMicroOps = 4;
292}
293def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
294 A57UnitV, A57UnitV, A57UnitV]> {
295 let Latency = 9;
296 let NumMicroOps = 4;
297}
166def A57Write_4cyc_1I_1L : SchedWriteRes<[A57UnitI,
167 A57UnitL]> {
168 let Latency = 4;
169 let NumMicroOps = 2;
170}
171def A57Write_4cyc_2X : SchedWriteRes<[A57UnitX, A57UnitX]> {
172 let Latency = 4;
173 let NumMicroOps = 2;

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300 let Latency = 9;
301 let NumMicroOps = 4;
302}
303def A57Write_9cyc_1L_3V : SchedWriteRes<[A57UnitL,
304 A57UnitV, A57UnitV, A57UnitV]> {
305 let Latency = 9;
306 let NumMicroOps = 4;
307}
308def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV,
309 A57UnitV, A57UnitV]> {
310 let Latency = 12;
311 let NumMicroOps = 4;
312}
298
299
300//===----------------------------------------------------------------------===//
301// Define Generic 5 micro-op types
302
303def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
304 A57UnitV, A57UnitV]> {
305 let Latency = 3;

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329 let Latency = 9;
330 let NumMicroOps = 5;
331}
332def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
333 A57UnitV, A57UnitV, A57UnitV]> {
334 let Latency = 9;
335 let NumMicroOps = 5;
336}
313
314
315//===----------------------------------------------------------------------===//
316// Define Generic 5 micro-op types
317
318def A57Write_3cyc_3S_2V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
319 A57UnitV, A57UnitV]> {
320 let Latency = 3;

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344 let Latency = 9;
345 let NumMicroOps = 5;
346}
347def A57Write_9cyc_2L_3V : SchedWriteRes<[A57UnitL, A57UnitL,
348 A57UnitV, A57UnitV, A57UnitV]> {
349 let Latency = 9;
350 let NumMicroOps = 5;
351}
352def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
353 A57UnitV, A57UnitV]> {
354 let Latency = 9;
355 let NumMicroOps = 5;
356}
337
338
339//===----------------------------------------------------------------------===//
340// Define Generic 6 micro-op types
341
342def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
343 A57UnitS, A57UnitS, A57UnitS,
344 A57UnitV, A57UnitV]> {

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394}
395def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
396 A57UnitS, A57UnitS,
397 A57UnitS, A57UnitS,
398 A57UnitV, A57UnitV]> {
399 let Latency = 4;
400 let NumMicroOps = 7;
401}
357
358
359//===----------------------------------------------------------------------===//
360// Define Generic 6 micro-op types
361
362def A57Write_3cyc_1I_3S_2V : SchedWriteRes<[A57UnitI,
363 A57UnitS, A57UnitS, A57UnitS,
364 A57UnitV, A57UnitV]> {

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414}
415def A57Write_4cyc_1I_4S_2V : SchedWriteRes<[A57UnitI,
416 A57UnitS, A57UnitS,
417 A57UnitS, A57UnitS,
418 A57UnitV, A57UnitV]> {
419 let Latency = 4;
420 let NumMicroOps = 7;
421}
402def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
422def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
403 A57UnitS, A57UnitS, A57UnitS,
404 A57UnitS, A57UnitS, A57UnitS]> {
405 let Latency = 6;
406 let NumMicroOps = 7;
407}
408def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
409 A57UnitL, A57UnitL,
410 A57UnitV, A57UnitV,
411 A57UnitV, A57UnitV]> {
412 let Latency = 9;
413 let NumMicroOps = 7;
414}
423 A57UnitS, A57UnitS, A57UnitS,
424 A57UnitS, A57UnitS, A57UnitS]> {
425 let Latency = 6;
426 let NumMicroOps = 7;
427}
428def A57Write_9cyc_1I_2L_4V : SchedWriteRes<[A57UnitI,
429 A57UnitL, A57UnitL,
430 A57UnitV, A57UnitV,
431 A57UnitV, A57UnitV]> {
432 let Latency = 9;
433 let NumMicroOps = 7;
434}
435def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
436 A57UnitV, A57UnitV,
437 A57UnitV, A57UnitV]> {
438 let Latency = 12;
439 let NumMicroOps = 7;
440}
415
416
417//===----------------------------------------------------------------------===//
418// Define Generic 8 micro-op types
419
420def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
421 A57UnitL, A57UnitL, A57UnitL,
422 A57UnitV, A57UnitV,

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438 let Latency = 8;
439 let NumMicroOps = 8;
440}
441
442
443//===----------------------------------------------------------------------===//
444// Define Generic 9 micro-op types
445
441
442
443//===----------------------------------------------------------------------===//
444// Define Generic 8 micro-op types
445
446def A57Write_10cyc_1I_3L_4V : SchedWriteRes<[A57UnitI,
447 A57UnitL, A57UnitL, A57UnitL,
448 A57UnitV, A57UnitV,

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464 let Latency = 8;
465 let NumMicroOps = 8;
466}
467
468
469//===----------------------------------------------------------------------===//
470// Define Generic 9 micro-op types
471
446def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
447 A57UnitS, A57UnitS,
448 A57UnitS, A57UnitS,
449 A57UnitS, A57UnitS,
450 A57UnitS, A57UnitS]> {
472def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
473 A57UnitS, A57UnitS,
474 A57UnitS, A57UnitS,
475 A57UnitS, A57UnitS,
476 A57UnitS, A57UnitS]> {
451 let Latency = 8;
452 let NumMicroOps = 9;
453}
454def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
455 A57UnitL, A57UnitL,
456 A57UnitL, A57UnitL,
457 A57UnitV, A57UnitV,
458 A57UnitV, A57UnitV]> {
459 let Latency = 11;
460 let NumMicroOps = 9;
461}
477 let Latency = 8;
478 let NumMicroOps = 9;
479}
480def A57Write_11cyc_1I_4L_4V : SchedWriteRes<[A57UnitI,
481 A57UnitL, A57UnitL,
482 A57UnitL, A57UnitL,
483 A57UnitV, A57UnitV,
484 A57UnitV, A57UnitV]> {
485 let Latency = 11;
486 let NumMicroOps = 9;
487}
488def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
489 A57UnitV, A57UnitV, A57UnitV,
490 A57UnitV, A57UnitV, A57UnitV]> {
491 let Latency = 15;
492 let NumMicroOps = 9;
493}
462
463
464//===----------------------------------------------------------------------===//
465// Define Generic 10 micro-op types
466
467def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
468 A57UnitS, A57UnitS, A57UnitS,
469 A57UnitV, A57UnitV,

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495
496//===----------------------------------------------------------------------===//
497// Define Generic 10 micro-op types
498
499def A57Write_6cyc_6S_4V : SchedWriteRes<[A57UnitS, A57UnitS, A57UnitS,
500 A57UnitS, A57UnitS, A57UnitS,
501 A57UnitV, A57UnitV,

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