31,32c31,34
< def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18; }
< def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19; }
---
> def A57Write_18cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 18;
> let ResourceCycles = [18]; }
> def A57Write_19cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 19;
> let ResourceCycles = [19]; }
37,38c39,42
< def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32; }
< def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35; }
---
> def A57Write_32cyc_1X : SchedWriteRes<[A57UnitX]> { let Latency = 32;
> let ResourceCycles = [32]; }
> def A57Write_35cyc_1M : SchedWriteRes<[A57UnitM]> { let Latency = 35;
> let ResourceCycles = [35]; }
55a60
> let ResourceCycles = [32, 32];
139a145
> let ResourceCycles = [18, 18];
155a162,165
> def A57Write_3cyc_2V : SchedWriteRes<[A57UnitV, A57UnitV]> {
> let Latency = 3;
> let NumMicroOps = 2;
> }
297a308,312
> def A57Write_12cyc_4V : SchedWriteRes<[A57UnitV, A57UnitV,
> A57UnitV, A57UnitV]> {
> let Latency = 12;
> let NumMicroOps = 4;
> }
336a352,356
> def A57Write_9cyc_5V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
> A57UnitV, A57UnitV]> {
> let Latency = 9;
> let NumMicroOps = 5;
> }
402c422
< def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
---
> def A57Write_6cyc_1I_6S : SchedWriteRes<[A57UnitI,
414a435,440
> def A57Write_12cyc_7V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
> A57UnitV, A57UnitV,
> A57UnitV, A57UnitV]> {
> let Latency = 12;
> let NumMicroOps = 7;
> }
446,450c472,476
< def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
< A57UnitS, A57UnitS,
< A57UnitS, A57UnitS,
< A57UnitS, A57UnitS,
< A57UnitS, A57UnitS]> {
---
> def A57Write_8cyc_1I_8S : SchedWriteRes<[A57UnitI,
> A57UnitS, A57UnitS,
> A57UnitS, A57UnitS,
> A57UnitS, A57UnitS,
> A57UnitS, A57UnitS]> {
461a488,493
> def A57Write_15cyc_9V : SchedWriteRes<[A57UnitV, A57UnitV, A57UnitV,
> A57UnitV, A57UnitV, A57UnitV,
> A57UnitV, A57UnitV, A57UnitV]> {
> let Latency = 15;
> let NumMicroOps = 9;
> }