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RegAllocBase.cpp (321369) RegAllocBase.cpp (321723)
1//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 119 unchanged lines hidden (view full) ---

128 VRM->assignVirt2Phys(VirtReg->reg,
129 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
130 continue;
131 }
132
133 if (AvailablePhysReg)
134 Matrix->assign(*VirtReg, AvailablePhysReg);
135
1//===-- RegAllocBase.cpp - Register Allocator Base Class ------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

--- 119 unchanged lines hidden (view full) ---

128 VRM->assignVirt2Phys(VirtReg->reg,
129 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
130 continue;
131 }
132
133 if (AvailablePhysReg)
134 Matrix->assign(*VirtReg, AvailablePhysReg);
135
136 for (VirtRegVec::iterator I = SplitVRegs.begin(), E = SplitVRegs.end();
137 I != E; ++I) {
138 LiveInterval *SplitVirtReg = &LIS->getInterval(*I);
136 for (unsigned Reg : SplitVRegs) {
137 assert(LIS->hasInterval(Reg));
138
139 LiveInterval *SplitVirtReg = &LIS->getInterval(Reg);
139 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
140 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
140 assert(!VRM->hasPhys(SplitVirtReg->reg) && "Register already assigned");
141 if (MRI->reg_nodbg_empty(SplitVirtReg->reg)) {
142 assert(SplitVirtReg->empty() && "Non-empty but used interval");
141 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
142 aboutToRemoveInterval(*SplitVirtReg);
143 LIS->removeInterval(SplitVirtReg->reg);
144 continue;
145 }
146 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
143 DEBUG(dbgs() << "not queueing unused " << *SplitVirtReg << '\n');
144 aboutToRemoveInterval(*SplitVirtReg);
145 LIS->removeInterval(SplitVirtReg->reg);
146 continue;
147 }
148 DEBUG(dbgs() << "queuing new interval: " << *SplitVirtReg << "\n");
147 assert(!SplitVirtReg->empty() && "expecting non-empty interval");
148 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
149 "expect split value in virtual register");
150 enqueue(SplitVirtReg);
151 ++NumNewQueued;
152 }
153 }
154}
155
156void RegAllocBase::postOptimization() {
157 spiller().postOptimization();
158 for (auto DeadInst : DeadRemats) {
159 LIS->RemoveMachineInstrFromMaps(*DeadInst);
160 DeadInst->eraseFromParent();
161 }
162 DeadRemats.clear();
163}
149 assert(TargetRegisterInfo::isVirtualRegister(SplitVirtReg->reg) &&
150 "expect split value in virtual register");
151 enqueue(SplitVirtReg);
152 ++NumNewQueued;
153 }
154 }
155}
156
157void RegAllocBase::postOptimization() {
158 spiller().postOptimization();
159 for (auto DeadInst : DeadRemats) {
160 LIS->RemoveMachineInstrFromMaps(*DeadInst);
161 DeadInst->eraseFromParent();
162 }
163 DeadRemats.clear();
164}