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InterferenceCache.h (221345) InterferenceCache.h (224145)
1//===-- InterferenceCache.h - Caching per-block interference ---*- C++ -*--===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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38 class Entry {
39 /// PhysReg - The register currently represented.
40 unsigned PhysReg;
41
42 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
43 /// change.
44 unsigned Tag;
45
1//===-- InterferenceCache.h - Caching per-block interference ---*- C++ -*--===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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38 class Entry {
39 /// PhysReg - The register currently represented.
40 unsigned PhysReg;
41
42 /// Tag - Cache tag is changed when any of the underlying LiveIntervalUnions
43 /// change.
44 unsigned Tag;
45
46 /// RefCount - The total number of Cursor instances referring to this Entry.
47 unsigned RefCount;
48
46 /// MF - The current function.
47 MachineFunction *MF;
48
49 /// Indexes - Mapping block numbers to SlotIndex ranges.
50 SlotIndexes *Indexes;
51
52 /// PrevPos - The previous position the iterators were moved to.
53 SlotIndex PrevPos;

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63
64 /// Blocks - Interference for each block in the function.
65 SmallVector<BlockInterference, 8> Blocks;
66
67 /// update - Recompute Blocks[MBBNum]
68 void update(unsigned MBBNum);
69
70 public:
49 /// MF - The current function.
50 MachineFunction *MF;
51
52 /// Indexes - Mapping block numbers to SlotIndex ranges.
53 SlotIndexes *Indexes;
54
55 /// PrevPos - The previous position the iterators were moved to.
56 SlotIndex PrevPos;

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66
67 /// Blocks - Interference for each block in the function.
68 SmallVector<BlockInterference, 8> Blocks;
69
70 /// update - Recompute Blocks[MBBNum]
71 void update(unsigned MBBNum);
72
73 public:
71 Entry() : PhysReg(0), Tag(0), Indexes(0) {}
74 Entry() : PhysReg(0), Tag(0), RefCount(0), Indexes(0) {}
72
73 void clear(MachineFunction *mf, SlotIndexes *indexes) {
75
76 void clear(MachineFunction *mf, SlotIndexes *indexes) {
77 assert(!hasRefs() && "Cannot clear cache entry with references");
74 PhysReg = 0;
75 MF = mf;
76 Indexes = indexes;
77 }
78
79 unsigned getPhysReg() const { return PhysReg; }
80
78 PhysReg = 0;
79 MF = mf;
80 Indexes = indexes;
81 }
82
83 unsigned getPhysReg() const { return PhysReg; }
84
85 void addRef(int Delta) { RefCount += Delta; }
86
87 bool hasRefs() const { return RefCount > 0; }
88
81 void revalidate();
82
83 /// valid - Return true if this is a valid entry for physReg.
84 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
85
86 /// reset - Initialize entry to represent physReg's aliases.
87 void reset(unsigned physReg,
88 LiveIntervalUnion *LIUArray,

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117
118public:
119 InterferenceCache() : TRI(0), LIUArray(0), Indexes(0), MF(0), RoundRobin(0) {}
120
121 /// init - Prepare cache for a new function.
122 void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*,
123 const TargetRegisterInfo *);
124
89 void revalidate();
90
91 /// valid - Return true if this is a valid entry for physReg.
92 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
93
94 /// reset - Initialize entry to represent physReg's aliases.
95 void reset(unsigned physReg,
96 LiveIntervalUnion *LIUArray,

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125
126public:
127 InterferenceCache() : TRI(0), LIUArray(0), Indexes(0), MF(0), RoundRobin(0) {}
128
129 /// init - Prepare cache for a new function.
130 void init(MachineFunction*, LiveIntervalUnion*, SlotIndexes*,
131 const TargetRegisterInfo *);
132
133 /// getMaxCursors - Return the maximum number of concurrent cursors that can
134 /// be supported.
135 unsigned getMaxCursors() const { return CacheEntries; }
136
125 /// Cursor - The primary query interface for the block interference cache.
126 class Cursor {
127 Entry *CacheEntry;
128 BlockInterference *Current;
137 /// Cursor - The primary query interface for the block interference cache.
138 class Cursor {
139 Entry *CacheEntry;
140 BlockInterference *Current;
141
142 void setEntry(Entry *E) {
143 Current = 0;
144 // Update reference counts. Nothing happens when RefCount reaches 0, so
145 // we don't have to check for E == CacheEntry etc.
146 if (CacheEntry)
147 CacheEntry->addRef(-1);
148 CacheEntry = E;
149 if (CacheEntry)
150 CacheEntry->addRef(+1);
151 }
152
129 public:
153 public:
130 /// Cursor - Create a cursor for the interference allocated to PhysReg and
131 /// all its aliases.
132 Cursor(InterferenceCache &Cache, unsigned PhysReg)
133 : CacheEntry(Cache.get(PhysReg)), Current(0) {}
154 /// Cursor - Create a dangling cursor.
155 Cursor() : CacheEntry(0), Current(0) {}
156 ~Cursor() { setEntry(0); }
134
157
158 Cursor(const Cursor &O) : CacheEntry(0), Current(0) {
159 setEntry(O.CacheEntry);
160 }
161
162 Cursor &operator=(const Cursor &O) {
163 setEntry(O.CacheEntry);
164 return *this;
165 }
166
167 /// setPhysReg - Point this cursor to PhysReg's interference.
168 void setPhysReg(InterferenceCache &Cache, unsigned PhysReg) {
169 // Release reference before getting a new one. That guarantees we can
170 // actually have CacheEntries live cursors.
171 setEntry(0);
172 if (PhysReg)
173 setEntry(Cache.get(PhysReg));
174 }
175
135 /// moveTo - Move cursor to basic block MBBNum.
136 void moveToBlock(unsigned MBBNum) {
137 Current = CacheEntry->get(MBBNum);
138 }
139
140 /// hasInterference - Return true if the current block has any interference.
141 bool hasInterference() {
142 return Current->First.isValid();

--- 21 unchanged lines hidden --- 		176 /// moveTo - Move cursor to basic block MBBNum.
177 void moveToBlock(unsigned MBBNum) {
178 Current = CacheEntry->get(MBBNum);
179 }
180
181 /// hasInterference - Return true if the current block has any interference.
182 bool hasInterference() {
183 return Current->First.isValid();

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