| ARMDefines.h (276479) | ARMDefines.h (280031) |
|---|---|
| 1//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 31 unchanged lines hidden (view full) --- 40#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1 41#define COND_GE 0xA // Greater than or equal Greater than or equal N == V 42#define COND_LT 0xB // Less than Less than, or unordered N != V 43#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V 44#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V 45#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any 46#define COND_UNCOND 0xF 47 | 1//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// --- 31 unchanged lines hidden (view full) --- 40#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1 41#define COND_GE 0xA // Greater than or equal Greater than or equal N == V 42#define COND_LT 0xB // Less than Less than, or unordered N != V 43#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V 44#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V 45#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any 46#define COND_UNCOND 0xF 47 |
| 48static inline const char *ARMCondCodeToString(uint32_t CC) | 48static inline const char * 49ARMCondCodeToString(uint32_t CC) |
| 49{ 50 switch (CC) { 51 default: assert(0 && "Unknown condition code"); 52 case COND_EQ: return "eq"; 53 case COND_NE: return "ne"; 54 case COND_HS: return "hs"; 55 case COND_LO: return "lo"; 56 case COND_MI: return "mi"; --- 5 unchanged lines hidden (view full) --- 62 case COND_GE: return "ge"; 63 case COND_LT: return "lt"; 64 case COND_GT: return "gt"; 65 case COND_LE: return "le"; 66 case COND_AL: return "al"; 67 } 68} 69 | 50{ 51 switch (CC) { 52 default: assert(0 && "Unknown condition code"); 53 case COND_EQ: return "eq"; 54 case COND_NE: return "ne"; 55 case COND_HS: return "hs"; 56 case COND_LO: return "lo"; 57 case COND_MI: return "mi"; --- 5 unchanged lines hidden (view full) --- 63 case COND_GE: return "ge"; 64 case COND_LT: return "lt"; 65 case COND_GT: return "gt"; 66 case COND_LE: return "le"; 67 case COND_AL: return "al"; 68 } 69} 70 |
| 71static inline bool 72ARMConditionPassed(const uint32_t condition, const uint32_t cpsr) 73{ 74 const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag 75 const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag 76 const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag 77 const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag 78 79 switch (condition) { 80 case COND_EQ: return (cpsr_z == 1); 81 case COND_NE: return (cpsr_z == 0); 82 case COND_CS: return (cpsr_c == 1); 83 case COND_CC: return (cpsr_c == 0); 84 case COND_MI: return (cpsr_n == 1); 85 case COND_PL: return (cpsr_n == 0); 86 case COND_VS: return (cpsr_v == 1); 87 case COND_VC: return (cpsr_v == 0); 88 case COND_HI: return ((cpsr_c == 1) && (cpsr_z == 0)); 89 case COND_LS: return ((cpsr_c == 0) || (cpsr_z == 1)); 90 case COND_GE: return (cpsr_n == cpsr_v); 91 case COND_LT: return (cpsr_n != cpsr_v); 92 case COND_GT: return ((cpsr_z == 0) && (cpsr_n == cpsr_v)); 93 case COND_LE: return ((cpsr_z == 1) || (cpsr_n != cpsr_v)); 94 case COND_AL: 95 case COND_UNCOND: 96 default: 97 return true; 98 } 99 return false; 100} 101 |
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| 70// Bit positions for CPSR 71#define CPSR_T_POS 5 72#define CPSR_F_POS 6 73#define CPSR_I_POS 7 74#define CPSR_A_POS 8 75#define CPSR_E_POS 9 76#define CPSR_J_POS 24 77#define CPSR_Q_POS 27 --- 33 unchanged lines hidden --- | 102// Bit positions for CPSR 103#define CPSR_T_POS 5 104#define CPSR_F_POS 6 105#define CPSR_I_POS 7 106#define CPSR_A_POS 8 107#define CPSR_E_POS 9 108#define CPSR_J_POS 24 109#define CPSR_Q_POS 27 --- 33 unchanged lines hidden --- |