Deleted Added
sdiff udiff text old ( 276479 ) new ( 280031 )
full compact
ARMDefines.h (276479) ARMDefines.h (280031)
1//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef lldb_ARMDefines_h_
11#define lldb_ARMDefines_h_
12
13// Common definitions for the ARM/Thumb Instruction Set Architecture.
14
15namespace lldb_private {
16
17// ARM shifter types
18typedef enum
19{
20 SRType_LSL,
21 SRType_LSR,
22 SRType_ASR,
23 SRType_ROR,
24 SRType_RRX,
25 SRType_Invalid
26} ARM_ShifterType;
27
28// ARM conditions // Meaning (integer) Meaning (floating-point) Condition flags
29#define COND_EQ 0x0 // Equal Equal Z == 1
30#define COND_NE 0x1 // Not equal Not equal, or unordered Z == 0
31#define COND_CS 0x2 // Carry set >, ==, or unordered C == 1
32#define COND_HS 0x2
33#define COND_CC 0x3 // Carry clear Less than C == 0
34#define COND_LO 0x3
35#define COND_MI 0x4 // Minus, negative Less than N == 1
36#define COND_PL 0x5 // Plus, positive or zero >, ==, or unordered N == 0
37#define COND_VS 0x6 // Overflow Unordered V == 1
38#define COND_VC 0x7 // No overflow Not unordered V == 0
39#define COND_HI 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 0
40#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1
41#define COND_GE 0xA // Greater than or equal Greater than or equal N == V
42#define COND_LT 0xB // Less than Less than, or unordered N != V
43#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V
44#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V
45#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any
46#define COND_UNCOND 0xF
47
1//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef lldb_ARMDefines_h_
11#define lldb_ARMDefines_h_
12
13// Common definitions for the ARM/Thumb Instruction Set Architecture.
14
15namespace lldb_private {
16
17// ARM shifter types
18typedef enum
19{
20 SRType_LSL,
21 SRType_LSR,
22 SRType_ASR,
23 SRType_ROR,
24 SRType_RRX,
25 SRType_Invalid
26} ARM_ShifterType;
27
28// ARM conditions // Meaning (integer) Meaning (floating-point) Condition flags
29#define COND_EQ 0x0 // Equal Equal Z == 1
30#define COND_NE 0x1 // Not equal Not equal, or unordered Z == 0
31#define COND_CS 0x2 // Carry set >, ==, or unordered C == 1
32#define COND_HS 0x2
33#define COND_CC 0x3 // Carry clear Less than C == 0
34#define COND_LO 0x3
35#define COND_MI 0x4 // Minus, negative Less than N == 1
36#define COND_PL 0x5 // Plus, positive or zero >, ==, or unordered N == 0
37#define COND_VS 0x6 // Overflow Unordered V == 1
38#define COND_VC 0x7 // No overflow Not unordered V == 0
39#define COND_HI 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 0
40#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1
41#define COND_GE 0xA // Greater than or equal Greater than or equal N == V
42#define COND_LT 0xB // Less than Less than, or unordered N != V
43#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V
44#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V
45#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any
46#define COND_UNCOND 0xF
47
48static inline const char *ARMCondCodeToString(uint32_t CC)
48static inline const char *
49ARMCondCodeToString(uint32_t CC)
49{
50 switch (CC) {
51 default: assert(0 && "Unknown condition code");
52 case COND_EQ: return "eq";
53 case COND_NE: return "ne";
54 case COND_HS: return "hs";
55 case COND_LO: return "lo";
56 case COND_MI: return "mi";
57 case COND_PL: return "pl";
58 case COND_VS: return "vs";
59 case COND_VC: return "vc";
60 case COND_HI: return "hi";
61 case COND_LS: return "ls";
62 case COND_GE: return "ge";
63 case COND_LT: return "lt";
64 case COND_GT: return "gt";
65 case COND_LE: return "le";
66 case COND_AL: return "al";
67 }
68}
69
50{
51 switch (CC) {
52 default: assert(0 && "Unknown condition code");
53 case COND_EQ: return "eq";
54 case COND_NE: return "ne";
55 case COND_HS: return "hs";
56 case COND_LO: return "lo";
57 case COND_MI: return "mi";
58 case COND_PL: return "pl";
59 case COND_VS: return "vs";
60 case COND_VC: return "vc";
61 case COND_HI: return "hi";
62 case COND_LS: return "ls";
63 case COND_GE: return "ge";
64 case COND_LT: return "lt";
65 case COND_GT: return "gt";
66 case COND_LE: return "le";
67 case COND_AL: return "al";
68 }
69}
70
71static inline bool
72ARMConditionPassed(const uint32_t condition, const uint32_t cpsr)
73{
74 const uint32_t cpsr_n = (cpsr >> 31) & 1u; // Negative condition code flag
75 const uint32_t cpsr_z = (cpsr >> 30) & 1u; // Zero condition code flag
76 const uint32_t cpsr_c = (cpsr >> 29) & 1u; // Carry condition code flag
77 const uint32_t cpsr_v = (cpsr >> 28) & 1u; // Overflow condition code flag
78
79 switch (condition) {
80 case COND_EQ: return (cpsr_z == 1);
81 case COND_NE: return (cpsr_z == 0);
82 case COND_CS: return (cpsr_c == 1);
83 case COND_CC: return (cpsr_c == 0);
84 case COND_MI: return (cpsr_n == 1);
85 case COND_PL: return (cpsr_n == 0);
86 case COND_VS: return (cpsr_v == 1);
87 case COND_VC: return (cpsr_v == 0);
88 case COND_HI: return ((cpsr_c == 1) && (cpsr_z == 0));
89 case COND_LS: return ((cpsr_c == 0) || (cpsr_z == 1));
90 case COND_GE: return (cpsr_n == cpsr_v);
91 case COND_LT: return (cpsr_n != cpsr_v);
92 case COND_GT: return ((cpsr_z == 0) && (cpsr_n == cpsr_v));
93 case COND_LE: return ((cpsr_z == 1) || (cpsr_n != cpsr_v));
94 case COND_AL:
95 case COND_UNCOND:
96 default:
97 return true;
98 }
99 return false;
100}
101
70// Bit positions for CPSR
71#define CPSR_T_POS 5
72#define CPSR_F_POS 6
73#define CPSR_I_POS 7
74#define CPSR_A_POS 8
75#define CPSR_E_POS 9
76#define CPSR_J_POS 24
77#define CPSR_Q_POS 27
78#define CPSR_V_POS 28
79#define CPSR_C_POS 29
80#define CPSR_Z_POS 30
81#define CPSR_N_POS 31
82
83// CPSR mode definitions
84#define CPSR_MODE_USR 0x10u
85#define CPSR_MODE_FIQ 0x11u
86#define CPSR_MODE_IRQ 0x12u
87#define CPSR_MODE_SVC 0x13u
88#define CPSR_MODE_ABT 0x17u
89#define CPSR_MODE_UND 0x1bu
90#define CPSR_MODE_SYS 0x1fu
91
92// Masks for CPSR
93#define MASK_CPSR_MODE_MASK (0x0000001fu)
94#define MASK_CPSR_IT_MASK (0x0600fc00u)
95#define MASK_CPSR_T (1u << CPSR_T_POS)
96#define MASK_CPSR_F (1u << CPSR_F_POS)
97#define MASK_CPSR_I (1u << CPSR_I_POS)
98#define MASK_CPSR_A (1u << CPSR_A_POS)
99#define MASK_CPSR_E (1u << CPSR_E_POS)
100#define MASK_CPSR_GE_MASK (0x000f0000u)
101#define MASK_CPSR_J (1u << CPSR_J_POS)
102#define MASK_CPSR_Q (1u << CPSR_Q_POS)
103#define MASK_CPSR_V (1u << CPSR_V_POS)
104#define MASK_CPSR_C (1u << CPSR_C_POS)
105#define MASK_CPSR_Z (1u << CPSR_Z_POS)
106#define MASK_CPSR_N (1u << CPSR_N_POS)
107
108} // namespace lldb_private
109
110#endif // lldb_ARMDefines_h_
102// Bit positions for CPSR
103#define CPSR_T_POS 5
104#define CPSR_F_POS 6
105#define CPSR_I_POS 7
106#define CPSR_A_POS 8
107#define CPSR_E_POS 9
108#define CPSR_J_POS 24
109#define CPSR_Q_POS 27
110#define CPSR_V_POS 28
111#define CPSR_C_POS 29
112#define CPSR_Z_POS 30
113#define CPSR_N_POS 31
114
115// CPSR mode definitions
116#define CPSR_MODE_USR 0x10u
117#define CPSR_MODE_FIQ 0x11u
118#define CPSR_MODE_IRQ 0x12u
119#define CPSR_MODE_SVC 0x13u
120#define CPSR_MODE_ABT 0x17u
121#define CPSR_MODE_UND 0x1bu
122#define CPSR_MODE_SYS 0x1fu
123
124// Masks for CPSR
125#define MASK_CPSR_MODE_MASK (0x0000001fu)
126#define MASK_CPSR_IT_MASK (0x0600fc00u)
127#define MASK_CPSR_T (1u << CPSR_T_POS)
128#define MASK_CPSR_F (1u << CPSR_F_POS)
129#define MASK_CPSR_I (1u << CPSR_I_POS)
130#define MASK_CPSR_A (1u << CPSR_A_POS)
131#define MASK_CPSR_E (1u << CPSR_E_POS)
132#define MASK_CPSR_GE_MASK (0x000f0000u)
133#define MASK_CPSR_J (1u << CPSR_J_POS)
134#define MASK_CPSR_Q (1u << CPSR_Q_POS)
135#define MASK_CPSR_V (1u << CPSR_V_POS)
136#define MASK_CPSR_C (1u << CPSR_C_POS)
137#define MASK_CPSR_Z (1u << CPSR_Z_POS)
138#define MASK_CPSR_N (1u << CPSR_N_POS)
139
140} // namespace lldb_private
141
142#endif // lldb_ARMDefines_h_