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EmulateInstructionMIPS.cpp (287506) EmulateInstructionMIPS.cpp (287521)
1//===-- EmulateInstructionMIPS.cpp -------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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28#include "lldb/Core/PluginManager.h"
29#include "lldb/Core/DataExtractor.h"
30#include "lldb/Core/Stream.h"
31#include "lldb/Symbol/UnwindPlan.h"
32
33#include "llvm/ADT/STLExtras.h"
34
35#include "Plugins/Process/Utility/InstructionUtils.h"
1//===-- EmulateInstructionMIPS.cpp -------------------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//

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28#include "lldb/Core/PluginManager.h"
29#include "lldb/Core/DataExtractor.h"
30#include "lldb/Core/Stream.h"
31#include "lldb/Symbol/UnwindPlan.h"
32
33#include "llvm/ADT/STLExtras.h"
34
35#include "Plugins/Process/Utility/InstructionUtils.h"
36#include "Plugins/Process/Utility/RegisterContext_mips64.h" //mips32 has same registers nos as mips64
36#include "Plugins/Process/Utility/RegisterContext_mips.h" //mips32 has same registers nos as mips64
37
38using namespace lldb;
39using namespace lldb_private;
40
41#define UInt(x) ((uint64_t)x)
42#define integer int64_t
43
44

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119 cpu = "mips64r5"; break;
120 case ArchSpec::eCore_mips64r6:
121 case ArchSpec::eCore_mips64r6el:
122 cpu = "mips64r6"; break;
123 default:
124 cpu = "generic"; break;
125 }
126
37
38using namespace lldb;
39using namespace lldb_private;
40
41#define UInt(x) ((uint64_t)x)
42#define integer int64_t
43
44

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119 cpu = "mips64r5"; break;
120 case ArchSpec::eCore_mips64r6:
121 case ArchSpec::eCore_mips64r6el:
122 cpu = "mips64r6"; break;
123 default:
124 cpu = "generic"; break;
125 }
126
127 std::string features = "";
128 uint32_t arch_flags = arch.GetFlags ();
129 if (arch_flags & ArchSpec::eMIPSAse_msa)
130 features += "+msa,";
131 if (arch_flags & ArchSpec::eMIPSAse_dsp)
132 features += "+dsp,";
133 if (arch_flags & ArchSpec::eMIPSAse_dspr2)
134 features += "+dspr2,";
135 if (arch_flags & ArchSpec::eMIPSAse_mips16)
136 features += "+mips16,";
137 if (arch_flags & ArchSpec::eMIPSAse_micromips)
138 features += "+micromips,";
139
127 m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
128 assert (m_reg_info.get());
129
130 m_insn_info.reset (target->createMCInstrInfo());
131 assert (m_insn_info.get());
132
133 m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
140 m_reg_info.reset (target->createMCRegInfo (triple.getTriple()));
141 assert (m_reg_info.get());
142
143 m_insn_info.reset (target->createMCInstrInfo());
144 assert (m_insn_info.get());
145
146 m_asm_info.reset (target->createMCAsmInfo (*m_reg_info, triple.getTriple()));
134 m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, ""));
147 m_subtype_info.reset (target->createMCSubtargetInfo (triple.getTriple(), cpu, features));
135 assert (m_asm_info.get() && m_subtype_info.get());
136
137 m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
138 assert (m_context.get());
139
140 m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
141 assert (m_disasm.get());
142}

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284 case gcc_dwarf_r30_mips: return "fp";
285 case gcc_dwarf_ra_mips: return "ra";
286 case gcc_dwarf_sr_mips: return "sr";
287 case gcc_dwarf_lo_mips: return "lo";
288 case gcc_dwarf_hi_mips: return "hi";
289 case gcc_dwarf_bad_mips: return "bad";
290 case gcc_dwarf_cause_mips: return "cause";
291 case gcc_dwarf_pc_mips: return "pc";
148 assert (m_asm_info.get() && m_subtype_info.get());
149
150 m_context.reset (new llvm::MCContext (m_asm_info.get(), m_reg_info.get(), nullptr));
151 assert (m_context.get());
152
153 m_disasm.reset (target->createMCDisassembler (*m_subtype_info, *m_context));
154 assert (m_disasm.get());
155}

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297 case gcc_dwarf_r30_mips: return "fp";
298 case gcc_dwarf_ra_mips: return "ra";
299 case gcc_dwarf_sr_mips: return "sr";
300 case gcc_dwarf_lo_mips: return "lo";
301 case gcc_dwarf_hi_mips: return "hi";
302 case gcc_dwarf_bad_mips: return "bad";
303 case gcc_dwarf_cause_mips: return "cause";
304 case gcc_dwarf_pc_mips: return "pc";
292 case gcc_dwarf_f0_mips: return "fp_reg[0]";
293 case gcc_dwarf_f1_mips: return "fp_reg[1]";
294 case gcc_dwarf_f2_mips: return "fp_reg[2]";
295 case gcc_dwarf_f3_mips: return "fp_reg[3]";
296 case gcc_dwarf_f4_mips: return "fp_reg[4]";
297 case gcc_dwarf_f5_mips: return "fp_reg[5]";
298 case gcc_dwarf_f6_mips: return "fp_reg[6]";
299 case gcc_dwarf_f7_mips: return "fp_reg[7]";
300 case gcc_dwarf_f8_mips: return "fp_reg[8]";
301 case gcc_dwarf_f9_mips: return "fp_reg[9]";
302 case gcc_dwarf_f10_mips: return "fp_reg[10]";
303 case gcc_dwarf_f11_mips: return "fp_reg[11]";
304 case gcc_dwarf_f12_mips: return "fp_reg[12]";
305 case gcc_dwarf_f13_mips: return "fp_reg[13]";
306 case gcc_dwarf_f14_mips: return "fp_reg[14]";
307 case gcc_dwarf_f15_mips: return "fp_reg[15]";
308 case gcc_dwarf_f16_mips: return "fp_reg[16]";
309 case gcc_dwarf_f17_mips: return "fp_reg[17]";
310 case gcc_dwarf_f18_mips: return "fp_reg[18]";
311 case gcc_dwarf_f19_mips: return "fp_reg[19]";
312 case gcc_dwarf_f20_mips: return "fp_reg[20]";
313 case gcc_dwarf_f21_mips: return "fp_reg[21]";
314 case gcc_dwarf_f22_mips: return "fp_reg[22]";
315 case gcc_dwarf_f23_mips: return "fp_reg[23]";
316 case gcc_dwarf_f24_mips: return "fp_reg[24]";
317 case gcc_dwarf_f25_mips: return "fp_reg[25]";
318 case gcc_dwarf_f26_mips: return "fp_reg[26]";
319 case gcc_dwarf_f27_mips: return "fp_reg[27]";
320 case gcc_dwarf_f28_mips: return "fp_reg[28]";
321 case gcc_dwarf_f29_mips: return "fp_reg[29]";
322 case gcc_dwarf_f30_mips: return "fp_reg[30]";
323 case gcc_dwarf_f31_mips: return "fp_reg[31]";
305 case gcc_dwarf_f0_mips: return "f0";
306 case gcc_dwarf_f1_mips: return "f1";
307 case gcc_dwarf_f2_mips: return "f2";
308 case gcc_dwarf_f3_mips: return "f3";
309 case gcc_dwarf_f4_mips: return "f4";
310 case gcc_dwarf_f5_mips: return "f5";
311 case gcc_dwarf_f6_mips: return "f6";
312 case gcc_dwarf_f7_mips: return "f7";
313 case gcc_dwarf_f8_mips: return "f8";
314 case gcc_dwarf_f9_mips: return "f9";
315 case gcc_dwarf_f10_mips: return "f10";
316 case gcc_dwarf_f11_mips: return "f11";
317 case gcc_dwarf_f12_mips: return "f12";
318 case gcc_dwarf_f13_mips: return "f13";
319 case gcc_dwarf_f14_mips: return "f14";
320 case gcc_dwarf_f15_mips: return "f15";
321 case gcc_dwarf_f16_mips: return "f16";
322 case gcc_dwarf_f17_mips: return "f17";
323 case gcc_dwarf_f18_mips: return "f18";
324 case gcc_dwarf_f19_mips: return "f19";
325 case gcc_dwarf_f20_mips: return "f20";
326 case gcc_dwarf_f21_mips: return "f21";
327 case gcc_dwarf_f22_mips: return "f22";
328 case gcc_dwarf_f23_mips: return "f23";
329 case gcc_dwarf_f24_mips: return "f24";
330 case gcc_dwarf_f25_mips: return "f25";
331 case gcc_dwarf_f26_mips: return "f26";
332 case gcc_dwarf_f27_mips: return "f27";
333 case gcc_dwarf_f28_mips: return "f28";
334 case gcc_dwarf_f29_mips: return "f29";
335 case gcc_dwarf_f30_mips: return "f30";
336 case gcc_dwarf_f31_mips: return "f31";
324 case gcc_dwarf_fcsr_mips: return "fcsr";
325 case gcc_dwarf_fir_mips: return "fir";
326 }
327 return nullptr;
328}
329
330bool
331EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo &reg_info)

--- 2587 unchanged lines hidden --- 		337 case gcc_dwarf_fcsr_mips: return "fcsr";
338 case gcc_dwarf_fir_mips: return "fir";
339 }
340 return nullptr;
341}
342
343bool
344EmulateInstructionMIPS::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_num, RegisterInfo &reg_info)

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