| mips.c (169690) | mips.c (208737) |
|---|---|
| 1/* Subroutines used for MIPS code generation. 2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by A. Lichnewsky, lich@inria.inria.fr. 5 Changes by Michael Meissner, meissner@osf.org. 6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 7 Brendan Eich, brendan@microunity.com. 8 --- 699 unchanged lines hidden (view full) --- 708 /* Entries for generic ISAs */ 709 { "mips1", PROCESSOR_R3000, 1 }, 710 { "mips2", PROCESSOR_R6000, 2 }, 711 { "mips3", PROCESSOR_R4000, 3 }, 712 { "mips4", PROCESSOR_R8000, 4 }, 713 { "mips32", PROCESSOR_4KC, 32 }, 714 { "mips32r2", PROCESSOR_M4K, 33 }, 715 { "mips64", PROCESSOR_5KC, 64 }, | 1/* Subroutines used for MIPS code generation. 2 Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. 4 Contributed by A. Lichnewsky, lich@inria.inria.fr. 5 Changes by Michael Meissner, meissner@osf.org. 6 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and 7 Brendan Eich, brendan@microunity.com. 8 --- 699 unchanged lines hidden (view full) --- 708 /* Entries for generic ISAs */ 709 { "mips1", PROCESSOR_R3000, 1 }, 710 { "mips2", PROCESSOR_R6000, 2 }, 711 { "mips3", PROCESSOR_R4000, 3 }, 712 { "mips4", PROCESSOR_R8000, 4 }, 713 { "mips32", PROCESSOR_4KC, 32 }, 714 { "mips32r2", PROCESSOR_M4K, 33 }, 715 { "mips64", PROCESSOR_5KC, 64 }, |
| 716 { "mips64r2", PROCESSOR_5KC, 65 }, |
|
| 716 717 /* MIPS I */ 718 { "r3000", PROCESSOR_R3000, 1 }, 719 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */ 720 { "r3900", PROCESSOR_R3900, 1 }, 721 722 /* MIPS II */ 723 { "r6000", PROCESSOR_R6000, 2 }, --- 33 unchanged lines hidden (view full) --- 757 /* MIPS64 */ 758 { "5kc", PROCESSOR_5KC, 64 }, 759 { "5kf", PROCESSOR_5KF, 64 }, 760 { "20kc", PROCESSOR_20KC, 64 }, 761 { "sb1", PROCESSOR_SB1, 64 }, 762 { "sb1a", PROCESSOR_SB1A, 64 }, 763 { "sr71000", PROCESSOR_SR71000, 64 }, 764 | 717 718 /* MIPS I */ 719 { "r3000", PROCESSOR_R3000, 1 }, 720 { "r2000", PROCESSOR_R3000, 1 }, /* = r3000 */ 721 { "r3900", PROCESSOR_R3900, 1 }, 722 723 /* MIPS II */ 724 { "r6000", PROCESSOR_R6000, 2 }, --- 33 unchanged lines hidden (view full) --- 758 /* MIPS64 */ 759 { "5kc", PROCESSOR_5KC, 64 }, 760 { "5kf", PROCESSOR_5KF, 64 }, 761 { "20kc", PROCESSOR_20KC, 64 }, 762 { "sb1", PROCESSOR_SB1, 64 }, 763 { "sb1a", PROCESSOR_SB1A, 64 }, 764 { "sr71000", PROCESSOR_SR71000, 64 }, 765 |
| 766 /* MIPS64R2 */ 767 { "octeon", PROCESSOR_OCTEON, 65 }, 768 |
|
| 765 /* End marker */ 766 { 0, 0, 0 } 767}; 768 769/* Default costs. If these are used for a processor we should look 770 up the actual costs. */ 771#define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ 772 COSTS_N_INSNS (7), /* fp_mult_sf */ \ --- 4051 unchanged lines hidden (view full) --- 4824 4825 The MIPS32 and MIPS64 architecture specifications say "Software 4826 is strongly encouraged to avoid use of Branch Likely 4827 instructions, as they will be removed from a future revision 4828 of the [MIPS32 and MIPS64] architecture." Therefore, we do not 4829 issue those instructions unless instructed to do so by 4830 -mbranch-likely. */ 4831 if (ISA_HAS_BRANCHLIKELY | 769 /* End marker */ 770 { 0, 0, 0 } 771}; 772 773/* Default costs. If these are used for a processor we should look 774 up the actual costs. */ 775#define DEFAULT_COSTS COSTS_N_INSNS (6), /* fp_add */ \ 776 COSTS_N_INSNS (7), /* fp_mult_sf */ \ --- 4051 unchanged lines hidden (view full) --- 4828 4829 The MIPS32 and MIPS64 architecture specifications say "Software 4830 is strongly encouraged to avoid use of Branch Likely 4831 instructions, as they will be removed from a future revision 4832 of the [MIPS32 and MIPS64] architecture." Therefore, we do not 4833 issue those instructions unless instructed to do so by 4834 -mbranch-likely. */ 4835 if (ISA_HAS_BRANCHLIKELY |
| 4832 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64) | 4836 && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2) |
| 4833 && !(TUNE_MIPS5500 || TUNE_SB1)) 4834 target_flags |= MASK_BRANCHLIKELY; 4835 else 4836 target_flags &= ~MASK_BRANCHLIKELY; 4837 } 4838 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) 4839 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture"); 4840 --- 5097 unchanged lines hidden (view full) --- 9938{ 9939 switch (mips_tune) 9940 { 9941 case PROCESSOR_R4130: 9942 case PROCESSOR_R5400: 9943 case PROCESSOR_R5500: 9944 case PROCESSOR_R7000: 9945 case PROCESSOR_R9000: | 4837 && !(TUNE_MIPS5500 || TUNE_SB1)) 4838 target_flags |= MASK_BRANCHLIKELY; 4839 else 4840 target_flags &= ~MASK_BRANCHLIKELY; 4841 } 4842 if (TARGET_BRANCHLIKELY && !ISA_HAS_BRANCHLIKELY) 4843 warning (0, "generation of Branch Likely instructions enabled, but not supported by architecture"); 4844 --- 5097 unchanged lines hidden (view full) --- 9942{ 9943 switch (mips_tune) 9944 { 9945 case PROCESSOR_R4130: 9946 case PROCESSOR_R5400: 9947 case PROCESSOR_R5500: 9948 case PROCESSOR_R7000: 9949 case PROCESSOR_R9000: |
| 9950 case PROCESSOR_OCTEON: |
|
| 9946 return 2; 9947 9948 case PROCESSOR_SB1: 9949 case PROCESSOR_SB1A: 9950 /* This is actually 4, but we get better performance if we claim 3. 9951 This is partly because of unwanted speculative code motion with the 9952 larger number, and partly because in most common cases we can't 9953 reach the theoretical max of 4. */ --- 887 unchanged lines hidden --- | 9951 return 2; 9952 9953 case PROCESSOR_SB1: 9954 case PROCESSOR_SB1A: 9955 /* This is actually 4, but we get better performance if we claim 3. 9956 This is partly because of unwanted speculative code motion with the 9957 larger number, and partly because in most common cases we can't 9958 reach the theoretical max of 4. */ --- 887 unchanged lines hidden --- |