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tc-mips.c (208737) tc-mips.c (218822)
1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004, 2005 Free Software Foundation, Inc.
3 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify

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23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26#include "as.h"
27#include "config.h"
28#include "subsegs.h"
29#include "safe-ctype.h"
30
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify

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23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26#include "as.h"
27#include "config.h"
28#include "subsegs.h"
29#include "safe-ctype.h"
30
31#include <stdarg.h>
32
33#include "opcode/mips.h"
34#include "itbl-ops.h"
35#include "dwarf2dbg.h"
36#include "dw2gencfi.h"
37
38#ifdef DEBUG
39#define DBG(x) printf x
40#else

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164 long where;
165
166 /* The relocs associated with the instruction, if any. */
167 fixS *fixp[3];
168
169 /* True if this entry cannot be moved from its current position. */
170 unsigned int fixed_p : 1;
171
31#include "opcode/mips.h"
32#include "itbl-ops.h"
33#include "dwarf2dbg.h"
34#include "dw2gencfi.h"
35
36#ifdef DEBUG
37#define DBG(x) printf x
38#else

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162 long where;
163
164 /* The relocs associated with the instruction, if any. */
165 fixS *fixp[3];
166
167 /* True if this entry cannot be moved from its current position. */
168 unsigned int fixed_p : 1;
169
172 /* True if this instruction occured in a .set noreorder block. */
170 /* True if this instruction occurred in a .set noreorder block. */
173 unsigned int noreorder_p : 1;
174
175 /* True for mips16 instructions that jump to an absolute address. */
176 unsigned int mips16_absolute_jump_p : 1;
177};
178
179/* The ABI to use. */
180enum mips_abi_level

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207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
209 int isa;
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
213 int ase_mips3d;
214 int ase_mdmx;
171 unsigned int noreorder_p : 1;
172
173 /* True for mips16 instructions that jump to an absolute address. */
174 unsigned int mips16_absolute_jump_p : 1;
175};
176
177/* The ABI to use. */
178enum mips_abi_level

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205 if it has not been initialized. Changed by `.set mipsN', and the
206 -mipsN command line option, and the default CPU. */
207 int isa;
208 /* Enabled Application Specific Extensions (ASEs). These are set to -1
209 if they have not been initialized. Changed by `.set <asename>', by
210 command line options, and based on the default architecture. */
211 int ase_mips3d;
212 int ase_mdmx;
213 int ase_smartmips;
215 int ase_dsp;
214 int ase_dsp;
215 int ase_dspr2;
216 int ase_mt;
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
221 int mips16;
222 /* Non-zero if we should not reorder instructions. Changed by `.set
223 reorder' and `.set noreorder'. */

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259static int file_mips_fp32 = -1;
260
261/* This is the struct we use to hold the current set of options. Note
262 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
263 -1 to indicate that they have not been initialized. */
264
265static struct mips_set_options mips_opts =
266{
216 int ase_mt;
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
221 int mips16;
222 /* Non-zero if we should not reorder instructions. Changed by `.set
223 reorder' and `.set noreorder'. */

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259static int file_mips_fp32 = -1;
260
261/* This is the struct we use to hold the current set of options. Note
262 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
263 -1 to indicate that they have not been initialized. */
264
265static struct mips_set_options mips_opts =
266{
267 ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
267 ISA_UNKNOWN, -1, -1, 0, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
268};
269
270/* These variables are filled in with the masks of registers used.
271 The object format code reads them and puts them in the appropriate
272 place. */
273unsigned long mips_gprmask;
274unsigned long mips_cprmask[4];
275
276/* MIPS ISA we are using for this output file. */
277static int file_mips_isa = ISA_UNKNOWN;
278
279/* True if -mips16 was passed or implied by arguments passed on the
280 command line (e.g., by -march). */
281static int file_ase_mips16;
282
268};
269
270/* These variables are filled in with the masks of registers used.
271 The object format code reads them and puts them in the appropriate
272 place. */
273unsigned long mips_gprmask;
274unsigned long mips_cprmask[4];
275
276/* MIPS ISA we are using for this output file. */
277static int file_mips_isa = ISA_UNKNOWN;
278
279/* True if -mips16 was passed or implied by arguments passed on the
280 command line (e.g., by -march). */
281static int file_ase_mips16;
282
283#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \
284 || mips_opts.isa == ISA_MIPS32R2 \
285 || mips_opts.isa == ISA_MIPS64 \
286 || mips_opts.isa == ISA_MIPS64R2)
287
283/* True if -mips3d was passed or implied by arguments passed on the
284 command line (e.g., by -march). */
285static int file_ase_mips3d;
286
287/* True if -mdmx was passed or implied by arguments passed on the
288 command line (e.g., by -march). */
289static int file_ase_mdmx;
290
288/* True if -mips3d was passed or implied by arguments passed on the
289 command line (e.g., by -march). */
290static int file_ase_mips3d;
291
292/* True if -mdmx was passed or implied by arguments passed on the
293 command line (e.g., by -march). */
294static int file_ase_mdmx;
295
296/* True if -msmartmips was passed or implied by arguments passed on the
297 command line (e.g., by -march). */
298static int file_ase_smartmips;
299
300#define ISA_SUPPORTS_SMARTMIPS (mips_opts.isa == ISA_MIPS32 \
301 || mips_opts.isa == ISA_MIPS32R2)
302
291/* True if -mdsp was passed or implied by arguments passed on the
292 command line (e.g., by -march). */
293static int file_ase_dsp;
294
303/* True if -mdsp was passed or implied by arguments passed on the
304 command line (e.g., by -march). */
305static int file_ase_dsp;
306
307#define ISA_SUPPORTS_DSP_ASE (mips_opts.isa == ISA_MIPS32R2 \
308 || mips_opts.isa == ISA_MIPS64R2)
309
310#define ISA_SUPPORTS_DSP64_ASE (mips_opts.isa == ISA_MIPS64R2)
311
312/* True if -mdspr2 was passed or implied by arguments passed on the
313 command line (e.g., by -march). */
314static int file_ase_dspr2;
315
316#define ISA_SUPPORTS_DSPR2_ASE (mips_opts.isa == ISA_MIPS32R2 \
317 || mips_opts.isa == ISA_MIPS64R2)
318
295/* True if -mmt was passed or implied by arguments passed on the
296 command line (e.g., by -march). */
297static int file_ase_mt;
298
319/* True if -mmt was passed or implied by arguments passed on the
320 command line (e.g., by -march). */
321static int file_ase_mt;
322
323#define ISA_SUPPORTS_MT_ASE (mips_opts.isa == ISA_MIPS32R2 \
324 || mips_opts.isa == ISA_MIPS64R2)
325
299/* The argument of the -march= flag. The architecture we are assembling. */
300static int file_mips_arch = CPU_UNKNOWN;
301static const char *mips_arch_string;
302
303/* The argument of the -mtune= flag. The architecture for which we
304 are optimizing. */
305static int mips_tune = CPU_UNKNOWN;
306static const char *mips_tune_string;
307
308/* True when generating 32-bit code for a 64-bit processor. */
309static int mips_32bitmode = 0;
310
311/* True if the given ABI requires 32-bit registers. */
312#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
313
314/* Likewise 64-bit registers. */
326/* The argument of the -march= flag. The architecture we are assembling. */
327static int file_mips_arch = CPU_UNKNOWN;
328static const char *mips_arch_string;
329
330/* The argument of the -mtune= flag. The architecture for which we
331 are optimizing. */
332static int mips_tune = CPU_UNKNOWN;
333static const char *mips_tune_string;
334
335/* True when generating 32-bit code for a 64-bit processor. */
336static int mips_32bitmode = 0;
337
338/* True if the given ABI requires 32-bit registers. */
339#define ABI_NEEDS_32BIT_REGS(ABI) ((ABI) == O32_ABI)
340
341/* Likewise 64-bit registers. */
315#define ABI_NEEDS_64BIT_REGS(ABI) \
316 ((ABI) == N32_ABI \
317 || (ABI) == N64_ABI \
342#define ABI_NEEDS_64BIT_REGS(ABI) \
343 ((ABI) == N32_ABI \
344 || (ABI) == N64_ABI \
318 || (ABI) == O64_ABI)
319
345 || (ABI) == O64_ABI)
346
320/* Return true if ISA supports 64 bit gp register instructions. */
321#define ISA_HAS_64BIT_REGS(ISA) ( \
322 (ISA) == ISA_MIPS3 \
323 || (ISA) == ISA_MIPS4 \
324 || (ISA) == ISA_MIPS5 \
325 || (ISA) == ISA_MIPS64 \
326 || (ISA) == ISA_MIPS64R2 \
327 )
347/* Return true if ISA supports 64 bit wide gp registers. */
348#define ISA_HAS_64BIT_REGS(ISA) \
349 ((ISA) == ISA_MIPS3 \
350 || (ISA) == ISA_MIPS4 \
351 || (ISA) == ISA_MIPS5 \
352 || (ISA) == ISA_MIPS64 \
353 || (ISA) == ISA_MIPS64R2)
328
354
355/* Return true if ISA supports 64 bit wide float registers. */
356#define ISA_HAS_64BIT_FPRS(ISA) \
357 ((ISA) == ISA_MIPS3 \
358 || (ISA) == ISA_MIPS4 \
359 || (ISA) == ISA_MIPS5 \
360 || (ISA) == ISA_MIPS32R2 \
361 || (ISA) == ISA_MIPS64 \
362 || (ISA) == ISA_MIPS64R2)
363
329/* Return true if ISA supports 64-bit right rotate (dror et al.)
330 instructions. */
364/* Return true if ISA supports 64-bit right rotate (dror et al.)
365 instructions. */
331#define ISA_HAS_DROR(ISA) ( \
332 (ISA) == ISA_MIPS64R2 \
333 )
366#define ISA_HAS_DROR(ISA) \
367 ((ISA) == ISA_MIPS64R2)
334
335/* Return true if ISA supports 32-bit right rotate (ror et al.)
336 instructions. */
368
369/* Return true if ISA supports 32-bit right rotate (ror et al.)
370 instructions. */
337#define ISA_HAS_ROR(ISA) ( \
338 (ISA) == ISA_MIPS32R2 \
339 || (ISA) == ISA_MIPS64R2 \
340 )
371#define ISA_HAS_ROR(ISA) \
372 ((ISA) == ISA_MIPS32R2 \
373 || (ISA) == ISA_MIPS64R2 \
374 || mips_opts.ase_smartmips)
341
342/* Return true if ISA supports ins instructions. */
375
376/* Return true if ISA supports ins instructions. */
343#define ISA_HAS_INS(ISA) ( \
344 (ISA) == ISA_MIPS32R2 \
345 || (ISA) == ISA_MIPS64R2 \
346 )
377#define ISA_HAS_INS(ISA) \
378 ((ISA) == ISA_MIPS32R2 \
379 || (ISA) == ISA_MIPS64R2)
347
380
381/* Return true if ISA supports single-precision floats in odd registers. */
382#define ISA_HAS_ODD_SINGLE_FPR(ISA) \
383 ((ISA) == ISA_MIPS32 \
384 || (ISA) == ISA_MIPS32R2 \
385 || (ISA) == ISA_MIPS64 \
386 || (ISA) == ISA_MIPS64R2)
387
388/* Return true if ISA supports move to/from high part of a 64-bit
389 floating-point register. */
390#define ISA_HAS_MXHC1(ISA) \
391 ((ISA) == ISA_MIPS32R2 \
392 || (ISA) == ISA_MIPS64R2)
393
348#define HAVE_32BIT_GPRS \
394#define HAVE_32BIT_GPRS \
349 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
395 (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa))
350
351#define HAVE_32BIT_FPRS \
396
397#define HAVE_32BIT_FPRS \
352 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
398 (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa))
353
399
354#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
355#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
400#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS)
401#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS)
356
357#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
358
359#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
360
361/* True if relocations are stored in-place. */
362#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
363

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387#define ADDRESS_STORE_INSN \
388 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
389
390/* Return true if the given CPU supports the MIPS16 ASE. */
391#define CPU_HAS_MIPS16(cpu) \
392 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
393 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
394
402
403#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
404
405#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
406
407/* True if relocations are stored in-place. */
408#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
409

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433#define ADDRESS_STORE_INSN \
434 (HAVE_32BIT_ADDRESSES ? "sw" : "sd")
435
436/* Return true if the given CPU supports the MIPS16 ASE. */
437#define CPU_HAS_MIPS16(cpu) \
438 (strncmp (TARGET_CPU, "mips16", sizeof ("mips16") - 1) == 0 \
439 || strncmp (TARGET_CANONICAL, "mips-lsi-elf", sizeof ("mips-lsi-elf") - 1) == 0)
440
395/* Return true if the given CPU supports the MIPS3D ASE. */
396#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
397 )
398
399/* Return true if the given CPU supports the MDMX ASE. */
400#define CPU_HAS_MDMX(cpu) (FALSE \
401 )
402
403/* Return true if the given CPU supports the DSP ASE. */
404#define CPU_HAS_DSP(cpu) (FALSE \
405 )
406
407/* Return true if the given CPU supports the MT ASE. */
408#define CPU_HAS_MT(cpu) (FALSE \
409 )
410
411/* True if CPU has a dror instruction. */
412#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
413
414/* True if CPU has a ror instruction. */
415#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
416
417/* True if mflo and mfhi can be immediately followed by instructions
418 which write to the HI and LO registers.

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496/* Non-zero if any .set noreorder directives were used. */
497
498static int mips_any_noreorder;
499
500/* Non-zero if nops should be inserted when the register referenced in
501 an mfhi/mflo instruction is read in the next two instructions. */
502static int mips_7000_hilo_fix;
503
441/* True if CPU has a dror instruction. */
442#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
443
444/* True if CPU has a ror instruction. */
445#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
446
447/* True if mflo and mfhi can be immediately followed by instructions
448 which write to the HI and LO registers.

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526/* Non-zero if any .set noreorder directives were used. */
527
528static int mips_any_noreorder;
529
530/* Non-zero if nops should be inserted when the register referenced in
531 an mfhi/mflo instruction is read in the next two instructions. */
532static int mips_7000_hilo_fix;
533
504/* The size of the small data section. */
534/* The size of objects in the small data section. */
505static unsigned int g_switch_value = 8;
506/* Whether the -G option was used. */
507static int g_switch_seen = 0;
508
509#define N_RMASK 0xc4
510#define N_VFP 0xd4
511
512/* If we can determine in advance that GP optimization won't be

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1013static void s_option (int);
1014static void s_mipsset (int);
1015static void s_abicalls (int);
1016static void s_cpload (int);
1017static void s_cpsetup (int);
1018static void s_cplocal (int);
1019static void s_cprestore (int);
1020static void s_cpreturn (int);
535static unsigned int g_switch_value = 8;
536/* Whether the -G option was used. */
537static int g_switch_seen = 0;
538
539#define N_RMASK 0xc4
540#define N_VFP 0xd4
541
542/* If we can determine in advance that GP optimization won't be

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1043static void s_option (int);
1044static void s_mipsset (int);
1045static void s_abicalls (int);
1046static void s_cpload (int);
1047static void s_cpsetup (int);
1048static void s_cplocal (int);
1049static void s_cprestore (int);
1050static void s_cpreturn (int);
1051static void s_dtprelword (int);
1052static void s_dtpreldword (int);
1021static void s_gpvalue (int);
1022static void s_gpword (int);
1023static void s_gpdword (int);
1024static void s_cpadd (int);
1025static void s_insn (int);
1026static void md_obj_begin (void);
1027static void md_obj_end (void);
1028static void s_mips_ent (int);

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1038static int validate_mips_insn (const struct mips_opcode *);
1039
1040/* Table and functions used to map between CPU/ISA names, and
1041 ISA levels, and CPU numbers. */
1042
1043struct mips_cpu_info
1044{
1045 const char *name; /* CPU or ISA name. */
1053static void s_gpvalue (int);
1054static void s_gpword (int);
1055static void s_gpdword (int);
1056static void s_cpadd (int);
1057static void s_insn (int);
1058static void md_obj_begin (void);
1059static void md_obj_end (void);
1060static void s_mips_ent (int);

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1070static int validate_mips_insn (const struct mips_opcode *);
1071
1072/* Table and functions used to map between CPU/ISA names, and
1073 ISA levels, and CPU numbers. */
1074
1075struct mips_cpu_info
1076{
1077 const char *name; /* CPU or ISA name. */
1046 int is_isa; /* Is this an ISA? (If 0, a CPU.) */
1078 int flags; /* ASEs available, or ISA flag. */
1047 int isa; /* ISA level. */
1048 int cpu; /* CPU number (default CPU if ISA). */
1049};
1050
1079 int isa; /* ISA level. */
1080 int cpu; /* CPU number (default CPU if ISA). */
1081};
1082
1083#define MIPS_CPU_IS_ISA 0x0001 /* Is this an ISA? (If 0, a CPU.) */
1084#define MIPS_CPU_ASE_SMARTMIPS 0x0002 /* CPU implements SmartMIPS ASE */
1085#define MIPS_CPU_ASE_DSP 0x0004 /* CPU implements DSP ASE */
1086#define MIPS_CPU_ASE_MT 0x0008 /* CPU implements MT ASE */
1087#define MIPS_CPU_ASE_MIPS3D 0x0010 /* CPU implements MIPS-3D ASE */
1088#define MIPS_CPU_ASE_MDMX 0x0020 /* CPU implements MDMX ASE */
1089#define MIPS_CPU_ASE_DSPR2 0x0040 /* CPU implements DSP R2 ASE */
1090
1051static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1052static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1053static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1054
1055/* Pseudo-op table.
1056
1057 The following pseudo-ops from the Kane and Heinrich MIPS book
1058 should be defined here, but are currently unsupported: .alias,
1059 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1060
1061 The following pseudo-ops from the Kane and Heinrich MIPS book are
1062 specific to the type of debugging information being generated, and
1063 should be defined by the object format: .aent, .begin, .bend,
1064 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1065 .vreg.
1066
1067 The following pseudo-ops from the Kane and Heinrich MIPS book are
1068 not MIPS CPU specific, but are also not specific to the object file
1069 format. This file is probably the best place to define them, but
1091static const struct mips_cpu_info *mips_parse_cpu (const char *, const char *);
1092static const struct mips_cpu_info *mips_cpu_info_from_isa (int);
1093static const struct mips_cpu_info *mips_cpu_info_from_arch (int);
1094
1095/* Pseudo-op table.
1096
1097 The following pseudo-ops from the Kane and Heinrich MIPS book
1098 should be defined here, but are currently unsupported: .alias,
1099 .galive, .gjaldef, .gjrlive, .livereg, .noalias.
1100
1101 The following pseudo-ops from the Kane and Heinrich MIPS book are
1102 specific to the type of debugging information being generated, and
1103 should be defined by the object format: .aent, .begin, .bend,
1104 .bgnb, .end, .endb, .ent, .fmask, .frame, .loc, .mask, .verstamp,
1105 .vreg.
1106
1107 The following pseudo-ops from the Kane and Heinrich MIPS book are
1108 not MIPS CPU specific, but are also not specific to the object file
1109 format. This file is probably the best place to define them, but
1070 they are not currently supported: .asm0, .endr, .lab, .repeat,
1071 .struct. */
1110 they are not currently supported: .asm0, .endr, .lab, .struct. */
1072
1073static const pseudo_typeS mips_pseudo_table[] =
1074{
1075 /* MIPS specific pseudo-ops. */
1076 {"option", s_option, 0},
1077 {"set", s_mipsset, 0},
1078 {"rdata", s_change_sec, 'r'},
1079 {"sdata", s_change_sec, 's'},
1080 {"livereg", s_ignore, 0},
1081 {"abicalls", s_abicalls, 0},
1082 {"cpload", s_cpload, 0},
1083 {"cpsetup", s_cpsetup, 0},
1084 {"cplocal", s_cplocal, 0},
1085 {"cprestore", s_cprestore, 0},
1086 {"cpreturn", s_cpreturn, 0},
1111
1112static const pseudo_typeS mips_pseudo_table[] =
1113{
1114 /* MIPS specific pseudo-ops. */
1115 {"option", s_option, 0},
1116 {"set", s_mipsset, 0},
1117 {"rdata", s_change_sec, 'r'},
1118 {"sdata", s_change_sec, 's'},
1119 {"livereg", s_ignore, 0},
1120 {"abicalls", s_abicalls, 0},
1121 {"cpload", s_cpload, 0},
1122 {"cpsetup", s_cpsetup, 0},
1123 {"cplocal", s_cplocal, 0},
1124 {"cprestore", s_cprestore, 0},
1125 {"cpreturn", s_cpreturn, 0},
1126 {"dtprelword", s_dtprelword, 0},
1127 {"dtpreldword", s_dtpreldword, 0},
1087 {"gpvalue", s_gpvalue, 0},
1088 {"gpword", s_gpword, 0},
1089 {"gpdword", s_gpdword, 0},
1090 {"cpadd", s_cpadd, 0},
1091 {"insn", s_insn, 0},
1092
1093 /* Relatively generic pseudo-ops that happen to be used on MIPS
1094 chips. */
1095 {"asciiz", stringer, 1},
1096 {"bss", s_change_sec, 'b'},
1097 {"err", s_err, 0},
1098 {"half", s_cons, 1},
1099 {"dword", s_cons, 3},
1100 {"weakext", s_mips_weakext, 0},
1128 {"gpvalue", s_gpvalue, 0},
1129 {"gpword", s_gpword, 0},
1130 {"gpdword", s_gpdword, 0},
1131 {"cpadd", s_cpadd, 0},
1132 {"insn", s_insn, 0},
1133
1134 /* Relatively generic pseudo-ops that happen to be used on MIPS
1135 chips. */
1136 {"asciiz", stringer, 1},
1137 {"bss", s_change_sec, 'b'},
1138 {"err", s_err, 0},
1139 {"half", s_cons, 1},
1140 {"dword", s_cons, 3},
1141 {"weakext", s_mips_weakext, 0},
1142 {"origin", s_org, 0},
1143 {"repeat", s_rept, 0},
1101
1102 /* These pseudo-ops are defined in read.c, but must be overridden
1103 here for one reason or another. */
1104 {"align", s_align, 0},
1105 {"byte", s_cons, 0},
1106 {"data", s_change_sec, 'd'},
1107 {"double", s_float_cons, 'd'},
1108 {"float", s_float_cons, 'f'},

--- 47 unchanged lines hidden (view full) ---

1156/* Symbols labelling the current insn. */
1157
1158struct insn_label_list
1159{
1160 struct insn_label_list *next;
1161 symbolS *label;
1162};
1163
1144
1145 /* These pseudo-ops are defined in read.c, but must be overridden
1146 here for one reason or another. */
1147 {"align", s_align, 0},
1148 {"byte", s_cons, 0},
1149 {"data", s_change_sec, 'd'},
1150 {"double", s_float_cons, 'd'},
1151 {"float", s_float_cons, 'f'},

--- 47 unchanged lines hidden (view full) ---

1199/* Symbols labelling the current insn. */
1200
1201struct insn_label_list
1202{
1203 struct insn_label_list *next;
1204 symbolS *label;
1205};
1206
1164static struct insn_label_list *insn_labels;
1165static struct insn_label_list *free_insn_labels;
1207static struct insn_label_list *free_insn_labels;
1208#define label_list tc_segment_info_data
1166
1167static void mips_clear_insn_labels (void);
1168
1169static inline void
1170mips_clear_insn_labels (void)
1171{
1172 register struct insn_label_list **pl;
1209
1210static void mips_clear_insn_labels (void);
1211
1212static inline void
1213mips_clear_insn_labels (void)
1214{
1215 register struct insn_label_list **pl;
1216 segment_info_type *si;
1173
1217
1174 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1175 ;
1176 *pl = insn_labels;
1177 insn_labels = NULL;
1218 if (now_seg)
1219 {
1220 for (pl = &free_insn_labels; *pl != NULL; pl = &(*pl)->next)
1221 ;
1222
1223 si = seg_info (now_seg);
1224 *pl = si->label_list;
1225 si->label_list = NULL;
1226 }
1178}
1227}
1228
1179
1180static char *expr_end;
1181
1182/* Expressions which appear in instructions. These are set by
1183 mips_ip. */
1184
1185static expressionS imm_expr;
1186static expressionS imm2_expr;

--- 24 unchanged lines hidden (view full) ---

1211{
1212 switch (OUTPUT_FLAVOR)
1213 {
1214 case bfd_target_ecoff_flavour:
1215 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1216 case bfd_target_coff_flavour:
1217 return "pe-mips";
1218 case bfd_target_elf_flavour:
1229
1230static char *expr_end;
1231
1232/* Expressions which appear in instructions. These are set by
1233 mips_ip. */
1234
1235static expressionS imm_expr;
1236static expressionS imm2_expr;

--- 24 unchanged lines hidden (view full) ---

1261{
1262 switch (OUTPUT_FLAVOR)
1263 {
1264 case bfd_target_ecoff_flavour:
1265 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1266 case bfd_target_coff_flavour:
1267 return "pe-mips";
1268 case bfd_target_elf_flavour:
1269#ifdef TE_VXWORKS
1270 if (!HAVE_64BIT_OBJECTS && !HAVE_NEWABI)
1271 return (target_big_endian
1272 ? "elf32-bigmips-vxworks"
1273 : "elf32-littlemips-vxworks");
1274#endif
1219#ifdef TE_TMIPS
1220 /* This is traditional mips. */
1221 return (target_big_endian
1222 ? (HAVE_64BIT_OBJECTS
1223 ? "elf64-tradbigmips"
1224 : (HAVE_NEWABI
1225 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1226 : (HAVE_64BIT_OBJECTS

--- 180 unchanged lines hidden (view full) ---

1407 CONFLICT (DMULT, MACC);
1408 CONFLICT (DMULT, DMACC);
1409 CONFLICT (DIV, MACC);
1410 CONFLICT (DIV, DMACC);
1411
1412#undef CONFLICT
1413}
1414
1275#ifdef TE_TMIPS
1276 /* This is traditional mips. */
1277 return (target_big_endian
1278 ? (HAVE_64BIT_OBJECTS
1279 ? "elf64-tradbigmips"
1280 : (HAVE_NEWABI
1281 ? "elf32-ntradbigmips" : "elf32-tradbigmips"))
1282 : (HAVE_64BIT_OBJECTS

--- 180 unchanged lines hidden (view full) ---

1463 CONFLICT (DMULT, MACC);
1464 CONFLICT (DMULT, DMACC);
1465 CONFLICT (DIV, MACC);
1466 CONFLICT (DIV, DMACC);
1467
1468#undef CONFLICT
1469}
1470
1415/* This function is called once, at assembler startup time. It should
1416 set up all the tables, etc. that the MD part of the assembler will need. */
1471struct regname {
1472 const char *name;
1473 unsigned int num;
1474};
1417
1475
1476#define RTYPE_MASK 0x1ff00
1477#define RTYPE_NUM 0x00100
1478#define RTYPE_FPU 0x00200
1479#define RTYPE_FCC 0x00400
1480#define RTYPE_VEC 0x00800
1481#define RTYPE_GP 0x01000
1482#define RTYPE_CP0 0x02000
1483#define RTYPE_PC 0x04000
1484#define RTYPE_ACC 0x08000
1485#define RTYPE_CCC 0x10000
1486#define RNUM_MASK 0x000ff
1487#define RWARN 0x80000
1488
1489#define GENERIC_REGISTER_NUMBERS \
1490 {"$0", RTYPE_NUM | 0}, \
1491 {"$1", RTYPE_NUM | 1}, \
1492 {"$2", RTYPE_NUM | 2}, \
1493 {"$3", RTYPE_NUM | 3}, \
1494 {"$4", RTYPE_NUM | 4}, \
1495 {"$5", RTYPE_NUM | 5}, \
1496 {"$6", RTYPE_NUM | 6}, \
1497 {"$7", RTYPE_NUM | 7}, \
1498 {"$8", RTYPE_NUM | 8}, \
1499 {"$9", RTYPE_NUM | 9}, \
1500 {"$10", RTYPE_NUM | 10}, \
1501 {"$11", RTYPE_NUM | 11}, \
1502 {"$12", RTYPE_NUM | 12}, \
1503 {"$13", RTYPE_NUM | 13}, \
1504 {"$14", RTYPE_NUM | 14}, \
1505 {"$15", RTYPE_NUM | 15}, \
1506 {"$16", RTYPE_NUM | 16}, \
1507 {"$17", RTYPE_NUM | 17}, \
1508 {"$18", RTYPE_NUM | 18}, \
1509 {"$19", RTYPE_NUM | 19}, \
1510 {"$20", RTYPE_NUM | 20}, \
1511 {"$21", RTYPE_NUM | 21}, \
1512 {"$22", RTYPE_NUM | 22}, \
1513 {"$23", RTYPE_NUM | 23}, \
1514 {"$24", RTYPE_NUM | 24}, \
1515 {"$25", RTYPE_NUM | 25}, \
1516 {"$26", RTYPE_NUM | 26}, \
1517 {"$27", RTYPE_NUM | 27}, \
1518 {"$28", RTYPE_NUM | 28}, \
1519 {"$29", RTYPE_NUM | 29}, \
1520 {"$30", RTYPE_NUM | 30}, \
1521 {"$31", RTYPE_NUM | 31}
1522
1523#define FPU_REGISTER_NAMES \
1524 {"$f0", RTYPE_FPU | 0}, \
1525 {"$f1", RTYPE_FPU | 1}, \
1526 {"$f2", RTYPE_FPU | 2}, \
1527 {"$f3", RTYPE_FPU | 3}, \
1528 {"$f4", RTYPE_FPU | 4}, \
1529 {"$f5", RTYPE_FPU | 5}, \
1530 {"$f6", RTYPE_FPU | 6}, \
1531 {"$f7", RTYPE_FPU | 7}, \
1532 {"$f8", RTYPE_FPU | 8}, \
1533 {"$f9", RTYPE_FPU | 9}, \
1534 {"$f10", RTYPE_FPU | 10}, \
1535 {"$f11", RTYPE_FPU | 11}, \
1536 {"$f12", RTYPE_FPU | 12}, \
1537 {"$f13", RTYPE_FPU | 13}, \
1538 {"$f14", RTYPE_FPU | 14}, \
1539 {"$f15", RTYPE_FPU | 15}, \
1540 {"$f16", RTYPE_FPU | 16}, \
1541 {"$f17", RTYPE_FPU | 17}, \
1542 {"$f18", RTYPE_FPU | 18}, \
1543 {"$f19", RTYPE_FPU | 19}, \
1544 {"$f20", RTYPE_FPU | 20}, \
1545 {"$f21", RTYPE_FPU | 21}, \
1546 {"$f22", RTYPE_FPU | 22}, \
1547 {"$f23", RTYPE_FPU | 23}, \
1548 {"$f24", RTYPE_FPU | 24}, \
1549 {"$f25", RTYPE_FPU | 25}, \
1550 {"$f26", RTYPE_FPU | 26}, \
1551 {"$f27", RTYPE_FPU | 27}, \
1552 {"$f28", RTYPE_FPU | 28}, \
1553 {"$f29", RTYPE_FPU | 29}, \
1554 {"$f30", RTYPE_FPU | 30}, \
1555 {"$f31", RTYPE_FPU | 31}
1556
1557#define FPU_CONDITION_CODE_NAMES \
1558 {"$fcc0", RTYPE_FCC | 0}, \
1559 {"$fcc1", RTYPE_FCC | 1}, \
1560 {"$fcc2", RTYPE_FCC | 2}, \
1561 {"$fcc3", RTYPE_FCC | 3}, \
1562 {"$fcc4", RTYPE_FCC | 4}, \
1563 {"$fcc5", RTYPE_FCC | 5}, \
1564 {"$fcc6", RTYPE_FCC | 6}, \
1565 {"$fcc7", RTYPE_FCC | 7}
1566
1567#define COPROC_CONDITION_CODE_NAMES \
1568 {"$cc0", RTYPE_FCC | RTYPE_CCC | 0}, \
1569 {"$cc1", RTYPE_FCC | RTYPE_CCC | 1}, \
1570 {"$cc2", RTYPE_FCC | RTYPE_CCC | 2}, \
1571 {"$cc3", RTYPE_FCC | RTYPE_CCC | 3}, \
1572 {"$cc4", RTYPE_FCC | RTYPE_CCC | 4}, \
1573 {"$cc5", RTYPE_FCC | RTYPE_CCC | 5}, \
1574 {"$cc6", RTYPE_FCC | RTYPE_CCC | 6}, \
1575 {"$cc7", RTYPE_FCC | RTYPE_CCC | 7}
1576
1577#define N32N64_SYMBOLIC_REGISTER_NAMES \
1578 {"$a4", RTYPE_GP | 8}, \
1579 {"$a5", RTYPE_GP | 9}, \
1580 {"$a6", RTYPE_GP | 10}, \
1581 {"$a7", RTYPE_GP | 11}, \
1582 {"$ta0", RTYPE_GP | 8}, /* alias for $a4 */ \
1583 {"$ta1", RTYPE_GP | 9}, /* alias for $a5 */ \
1584 {"$ta2", RTYPE_GP | 10}, /* alias for $a6 */ \
1585 {"$ta3", RTYPE_GP | 11}, /* alias for $a7 */ \
1586 {"$t0", RTYPE_GP | 12}, \
1587 {"$t1", RTYPE_GP | 13}, \
1588 {"$t2", RTYPE_GP | 14}, \
1589 {"$t3", RTYPE_GP | 15}
1590
1591#define O32_SYMBOLIC_REGISTER_NAMES \
1592 {"$t0", RTYPE_GP | 8}, \
1593 {"$t1", RTYPE_GP | 9}, \
1594 {"$t2", RTYPE_GP | 10}, \
1595 {"$t3", RTYPE_GP | 11}, \
1596 {"$t4", RTYPE_GP | 12}, \
1597 {"$t5", RTYPE_GP | 13}, \
1598 {"$t6", RTYPE_GP | 14}, \
1599 {"$t7", RTYPE_GP | 15}, \
1600 {"$ta0", RTYPE_GP | 12}, /* alias for $t4 */ \
1601 {"$ta1", RTYPE_GP | 13}, /* alias for $t5 */ \
1602 {"$ta2", RTYPE_GP | 14}, /* alias for $t6 */ \
1603 {"$ta3", RTYPE_GP | 15} /* alias for $t7 */
1604
1605/* Remaining symbolic register names */
1606#define SYMBOLIC_REGISTER_NAMES \
1607 {"$zero", RTYPE_GP | 0}, \
1608 {"$at", RTYPE_GP | 1}, \
1609 {"$AT", RTYPE_GP | 1}, \
1610 {"$v0", RTYPE_GP | 2}, \
1611 {"$v1", RTYPE_GP | 3}, \
1612 {"$a0", RTYPE_GP | 4}, \
1613 {"$a1", RTYPE_GP | 5}, \
1614 {"$a2", RTYPE_GP | 6}, \
1615 {"$a3", RTYPE_GP | 7}, \
1616 {"$s0", RTYPE_GP | 16}, \
1617 {"$s1", RTYPE_GP | 17}, \
1618 {"$s2", RTYPE_GP | 18}, \
1619 {"$s3", RTYPE_GP | 19}, \
1620 {"$s4", RTYPE_GP | 20}, \
1621 {"$s5", RTYPE_GP | 21}, \
1622 {"$s6", RTYPE_GP | 22}, \
1623 {"$s7", RTYPE_GP | 23}, \
1624 {"$t8", RTYPE_GP | 24}, \
1625 {"$t9", RTYPE_GP | 25}, \
1626 {"$k0", RTYPE_GP | 26}, \
1627 {"$kt0", RTYPE_GP | 26}, \
1628 {"$k1", RTYPE_GP | 27}, \
1629 {"$kt1", RTYPE_GP | 27}, \
1630 {"$gp", RTYPE_GP | 28}, \
1631 {"$sp", RTYPE_GP | 29}, \
1632 {"$s8", RTYPE_GP | 30}, \
1633 {"$fp", RTYPE_GP | 30}, \
1634 {"$ra", RTYPE_GP | 31}
1635
1636#define MIPS16_SPECIAL_REGISTER_NAMES \
1637 {"$pc", RTYPE_PC | 0}
1638
1639#define MDMX_VECTOR_REGISTER_NAMES \
1640 /* {"$v0", RTYPE_VEC | 0}, clash with REG 2 above */ \
1641 /* {"$v1", RTYPE_VEC | 1}, clash with REG 3 above */ \
1642 {"$v2", RTYPE_VEC | 2}, \
1643 {"$v3", RTYPE_VEC | 3}, \
1644 {"$v4", RTYPE_VEC | 4}, \
1645 {"$v5", RTYPE_VEC | 5}, \
1646 {"$v6", RTYPE_VEC | 6}, \
1647 {"$v7", RTYPE_VEC | 7}, \
1648 {"$v8", RTYPE_VEC | 8}, \
1649 {"$v9", RTYPE_VEC | 9}, \
1650 {"$v10", RTYPE_VEC | 10}, \
1651 {"$v11", RTYPE_VEC | 11}, \
1652 {"$v12", RTYPE_VEC | 12}, \
1653 {"$v13", RTYPE_VEC | 13}, \
1654 {"$v14", RTYPE_VEC | 14}, \
1655 {"$v15", RTYPE_VEC | 15}, \
1656 {"$v16", RTYPE_VEC | 16}, \
1657 {"$v17", RTYPE_VEC | 17}, \
1658 {"$v18", RTYPE_VEC | 18}, \
1659 {"$v19", RTYPE_VEC | 19}, \
1660 {"$v20", RTYPE_VEC | 20}, \
1661 {"$v21", RTYPE_VEC | 21}, \
1662 {"$v22", RTYPE_VEC | 22}, \
1663 {"$v23", RTYPE_VEC | 23}, \
1664 {"$v24", RTYPE_VEC | 24}, \
1665 {"$v25", RTYPE_VEC | 25}, \
1666 {"$v26", RTYPE_VEC | 26}, \
1667 {"$v27", RTYPE_VEC | 27}, \
1668 {"$v28", RTYPE_VEC | 28}, \
1669 {"$v29", RTYPE_VEC | 29}, \
1670 {"$v30", RTYPE_VEC | 30}, \
1671 {"$v31", RTYPE_VEC | 31}
1672
1673#define MIPS_DSP_ACCUMULATOR_NAMES \
1674 {"$ac0", RTYPE_ACC | 0}, \
1675 {"$ac1", RTYPE_ACC | 1}, \
1676 {"$ac2", RTYPE_ACC | 2}, \
1677 {"$ac3", RTYPE_ACC | 3}
1678
1679static const struct regname reg_names[] = {
1680 GENERIC_REGISTER_NUMBERS,
1681 FPU_REGISTER_NAMES,
1682 FPU_CONDITION_CODE_NAMES,
1683 COPROC_CONDITION_CODE_NAMES,
1684
1685 /* The $txx registers depends on the abi,
1686 these will be added later into the symbol table from
1687 one of the tables below once mips_abi is set after
1688 parsing of arguments from the command line. */
1689 SYMBOLIC_REGISTER_NAMES,
1690
1691 MIPS16_SPECIAL_REGISTER_NAMES,
1692 MDMX_VECTOR_REGISTER_NAMES,
1693 MIPS_DSP_ACCUMULATOR_NAMES,
1694 {0, 0}
1695};
1696
1697static const struct regname reg_names_o32[] = {
1698 O32_SYMBOLIC_REGISTER_NAMES,
1699 {0, 0}
1700};
1701
1702static const struct regname reg_names_n32n64[] = {
1703 N32N64_SYMBOLIC_REGISTER_NAMES,
1704 {0, 0}
1705};
1706
1707static int
1708reg_lookup (char **s, unsigned int types, unsigned int *regnop)
1709{
1710 symbolS *symbolP;
1711 char *e;
1712 char save_c;
1713 int reg = -1;
1714
1715 /* Find end of name. */
1716 e = *s;
1717 if (is_name_beginner (*e))
1718 ++e;
1719 while (is_part_of_name (*e))
1720 ++e;
1721
1722 /* Terminate name. */
1723 save_c = *e;
1724 *e = '\0';
1725
1726 /* Look for a register symbol. */
1727 if ((symbolP = symbol_find (*s)) && S_GET_SEGMENT (symbolP) == reg_section)
1728 {
1729 int r = S_GET_VALUE (symbolP);
1730 if (r & types)
1731 reg = r & RNUM_MASK;
1732 else if ((types & RTYPE_VEC) && (r & ~1) == (RTYPE_GP | 2))
1733 /* Convert GP reg $v0/1 to MDMX reg $v0/1! */
1734 reg = (r & RNUM_MASK) - 2;
1735 }
1736 /* Else see if this is a register defined in an itbl entry. */
1737 else if ((types & RTYPE_GP) && itbl_have_entries)
1738 {
1739 char *n = *s;
1740 unsigned long r;
1741
1742 if (*n == '$')
1743 ++n;
1744 if (itbl_get_reg_val (n, &r))
1745 reg = r & RNUM_MASK;
1746 }
1747
1748 /* Advance to next token if a register was recognised. */
1749 if (reg >= 0)
1750 *s = e;
1751 else if (types & RWARN)
1752 as_warn ("Unrecognized register name `%s'", *s);
1753
1754 *e = save_c;
1755 if (regnop)
1756 *regnop = reg;
1757 return reg >= 0;
1758}
1759
1760/* This function is called once, at assembler startup time. It should set up
1761 all the tables, etc. that the MD part of the assembler will need. */
1762
1418void
1419md_begin (void)
1420{
1763void
1764md_begin (void)
1765{
1421 register const char *retval = NULL;
1766 const char *retval = NULL;
1422 int i = 0;
1423 int broken = 0;
1424
1425 if (mips_pic != NO_PIC)
1426 {
1427 if (g_switch_seen && g_switch_value != 0)
1428 as_bad (_("-G may not be used in position-independent code"));
1429 g_switch_value = 0;

--- 65 unchanged lines hidden (view full) ---

1495 && strcmp (mips16_opcodes[i].name, name) == 0);
1496 }
1497
1498 if (broken)
1499 as_fatal (_("Broken assembler. No assembly attempted."));
1500
1501 /* We add all the general register names to the symbol table. This
1502 helps us detect invalid uses of them. */
1767 int i = 0;
1768 int broken = 0;
1769
1770 if (mips_pic != NO_PIC)
1771 {
1772 if (g_switch_seen && g_switch_value != 0)
1773 as_bad (_("-G may not be used in position-independent code"));
1774 g_switch_value = 0;

--- 65 unchanged lines hidden (view full) ---

1840 && strcmp (mips16_opcodes[i].name, name) == 0);
1841 }
1842
1843 if (broken)
1844 as_fatal (_("Broken assembler. No assembly attempted."));
1845
1846 /* We add all the general register names to the symbol table. This
1847 helps us detect invalid uses of them. */
1503 for (i = 0; i < 32; i++)
1504 {
1505 char buf[5];
1506
1507 sprintf (buf, "$%d", i);
1508 symbol_table_insert (symbol_new (buf, reg_section, i,
1848 for (i = 0; reg_names[i].name; i++)
1849 symbol_table_insert (symbol_new (reg_names[i].name, reg_section,
1850 reg_names[i].num, // & RNUM_MASK,
1851 &zero_address_frag));
1852 if (HAVE_NEWABI)
1853 for (i = 0; reg_names_n32n64[i].name; i++)
1854 symbol_table_insert (symbol_new (reg_names_n32n64[i].name, reg_section,
1855 reg_names_n32n64[i].num, // & RNUM_MASK,
1509 &zero_address_frag));
1856 &zero_address_frag));
1510 }
1511 symbol_table_insert (symbol_new ("$ra", reg_section, RA,
1512 &zero_address_frag));
1513 symbol_table_insert (symbol_new ("$fp", reg_section, FP,
1514 &zero_address_frag));
1515 symbol_table_insert (symbol_new ("$sp", reg_section, SP,
1516 &zero_address_frag));
1517 symbol_table_insert (symbol_new ("$gp", reg_section, GP,
1518 &zero_address_frag));
1519 symbol_table_insert (symbol_new ("$at", reg_section, AT,
1520 &zero_address_frag));
1521 symbol_table_insert (symbol_new ("$kt0", reg_section, KT0,
1522 &zero_address_frag));
1523 symbol_table_insert (symbol_new ("$kt1", reg_section, KT1,
1524 &zero_address_frag));
1525 symbol_table_insert (symbol_new ("$zero", reg_section, ZERO,
1526 &zero_address_frag));
1527 symbol_table_insert (symbol_new ("$pc", reg_section, -1,
1528 &zero_address_frag));
1529
1530 /* If we don't add these register names to the symbol table, they
1531 may end up being added as regular symbols by operand(), and then
1532 make it to the object file as undefined in case they're not
1533 regarded as local symbols. They're local in o32, since `$' is a
1534 local symbol prefix, but not in n32 or n64. */
1535 for (i = 0; i < 8; i++)
1536 {
1537 char buf[6];
1538
1539 sprintf (buf, "$fcc%i", i);
1540 symbol_table_insert (symbol_new (buf, reg_section, -1,
1857 else
1858 for (i = 0; reg_names_o32[i].name; i++)
1859 symbol_table_insert (symbol_new (reg_names_o32[i].name, reg_section,
1860 reg_names_o32[i].num, // & RNUM_MASK,
1541 &zero_address_frag));
1861 &zero_address_frag));
1542 }
1543
1544 mips_no_prev_insn ();
1545
1546 mips_gprmask = 0;
1547 mips_cprmask[0] = 0;
1548 mips_cprmask[1] = 0;
1549 mips_cprmask[2] = 0;
1550 mips_cprmask[3] = 0;
1551
1552 /* set the default alignment for the text section (2**2) */
1553 record_alignment (text_section, 2);
1554
1555 bfd_set_gp_size (stdoutput, g_switch_value);
1556
1862
1863 mips_no_prev_insn ();
1864
1865 mips_gprmask = 0;
1866 mips_cprmask[0] = 0;
1867 mips_cprmask[1] = 0;
1868 mips_cprmask[2] = 0;
1869 mips_cprmask[3] = 0;
1870
1871 /* set the default alignment for the text section (2**2) */
1872 record_alignment (text_section, 2);
1873
1874 bfd_set_gp_size (stdoutput, g_switch_value);
1875
1557 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1876#ifdef OBJ_ELF
1877 if (IS_ELF)
1558 {
1878 {
1559 /* On a native system, sections must be aligned to 16 byte
1560 boundaries. When configured for an embedded ELF target, we
1561 don't bother. */
1879 /* On a native system other than VxWorks, sections must be aligned
1880 to 16 byte boundaries. When configured for an embedded ELF
1881 target, we don't bother. */
1562 if (strcmp (TARGET_OS, "elf") != 0
1563 && strcmp (TARGET_OS, "vxworks") != 0)
1564 {
1565 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1566 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1567 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1568 }
1569

--- 17 unchanged lines hidden (view full) ---

1587
1588 if (mips_abi != N64_ABI)
1589 {
1590 sec = subseg_new (".reginfo", (subsegT) 0);
1591
1592 bfd_set_section_flags (stdoutput, sec, flags);
1593 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1594
1882 if (strcmp (TARGET_OS, "elf") != 0
1883 && strcmp (TARGET_OS, "vxworks") != 0)
1884 {
1885 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1886 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1887 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1888 }
1889

--- 17 unchanged lines hidden (view full) ---

1907
1908 if (mips_abi != N64_ABI)
1909 {
1910 sec = subseg_new (".reginfo", (subsegT) 0);
1911
1912 bfd_set_section_flags (stdoutput, sec, flags);
1913 bfd_set_section_alignment (stdoutput, sec, HAVE_NEWABI ? 3 : 2);
1914
1595#ifdef OBJ_ELF
1596 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1915 mips_regmask_frag = frag_more (sizeof (Elf32_External_RegInfo));
1597#endif
1598 }
1599 else
1600 {
1601 /* The 64-bit ABI uses a .MIPS.options section rather than
1602 .reginfo section. */
1603 sec = subseg_new (".MIPS.options", (subsegT) 0);
1604 bfd_set_section_flags (stdoutput, sec, flags);
1605 bfd_set_section_alignment (stdoutput, sec, 3);
1606
1916 }
1917 else
1918 {
1919 /* The 64-bit ABI uses a .MIPS.options section rather than
1920 .reginfo section. */
1921 sec = subseg_new (".MIPS.options", (subsegT) 0);
1922 bfd_set_section_flags (stdoutput, sec, flags);
1923 bfd_set_section_alignment (stdoutput, sec, 3);
1924
1607#ifdef OBJ_ELF
1608 /* Set up the option header. */
1609 {
1610 Elf_Internal_Options opthdr;
1611 char *f;
1612
1613 opthdr.kind = ODK_REGINFO;
1614 opthdr.size = (sizeof (Elf_External_Options)
1615 + sizeof (Elf64_External_RegInfo));
1616 opthdr.section = 0;
1617 opthdr.info = 0;
1618 f = frag_more (sizeof (Elf_External_Options));
1619 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1620 (Elf_External_Options *) f);
1621
1622 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1623 }
1925 /* Set up the option header. */
1926 {
1927 Elf_Internal_Options opthdr;
1928 char *f;
1929
1930 opthdr.kind = ODK_REGINFO;
1931 opthdr.size = (sizeof (Elf_External_Options)
1932 + sizeof (Elf64_External_RegInfo));
1933 opthdr.section = 0;
1934 opthdr.info = 0;
1935 f = frag_more (sizeof (Elf_External_Options));
1936 bfd_mips_elf_swap_options_out (stdoutput, &opthdr,
1937 (Elf_External_Options *) f);
1938
1939 mips_regmask_frag = frag_more (sizeof (Elf64_External_RegInfo));
1940 }
1624#endif
1625 }
1626
1627 if (ECOFF_DEBUGGING)
1628 {
1629 sec = subseg_new (".mdebug", (subsegT) 0);
1630 (void) bfd_set_section_flags (stdoutput, sec,
1631 SEC_HAS_CONTENTS | SEC_READONLY);
1632 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1633 }
1941 }
1942
1943 if (ECOFF_DEBUGGING)
1944 {
1945 sec = subseg_new (".mdebug", (subsegT) 0);
1946 (void) bfd_set_section_flags (stdoutput, sec,
1947 SEC_HAS_CONTENTS | SEC_READONLY);
1948 (void) bfd_set_section_alignment (stdoutput, sec, 2);
1949 }
1634#ifdef OBJ_ELF
1635 else if (OUTPUT_FLAVOR == bfd_target_elf_flavour && mips_flag_pdr)
1950 else if (mips_flag_pdr)
1636 {
1637 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1638 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1639 SEC_READONLY | SEC_RELOC
1640 | SEC_DEBUGGING);
1641 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1642 }
1951 {
1952 pdr_seg = subseg_new (".pdr", (subsegT) 0);
1953 (void) bfd_set_section_flags (stdoutput, pdr_seg,
1954 SEC_READONLY | SEC_RELOC
1955 | SEC_DEBUGGING);
1956 (void) bfd_set_section_alignment (stdoutput, pdr_seg, 2);
1957 }
1643#endif
1644
1645 subseg_set (seg, subseg);
1646 }
1647 }
1958
1959 subseg_set (seg, subseg);
1960 }
1961 }
1962#endif /* OBJ_ELF */
1648
1649 if (! ECOFF_DEBUGGING)
1650 md_obj_begin ();
1651
1652 if (mips_fix_vr4120)
1653 init_vr4120_conflicts ();
1654}
1655

--- 58 unchanged lines hidden (view full) ---

1714
1715/* Return true if the given relocation might need a matching %lo().
1716 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1717 need a matching %lo() when applied to local symbols. */
1718
1719static inline bfd_boolean
1720reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1721{
1963
1964 if (! ECOFF_DEBUGGING)
1965 md_obj_begin ();
1966
1967 if (mips_fix_vr4120)
1968 init_vr4120_conflicts ();
1969}
1970

--- 58 unchanged lines hidden (view full) ---

2029
2030/* Return true if the given relocation might need a matching %lo().
2031 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
2032 need a matching %lo() when applied to local symbols. */
2033
2034static inline bfd_boolean
2035reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
2036{
1722 return (reloc == BFD_RELOC_HI16_S
1723 || reloc == BFD_RELOC_MIPS_GOT16);
2037 return (HAVE_IN_PLACE_ADDENDS
2038 && (reloc == BFD_RELOC_HI16_S
2039 || reloc == BFD_RELOC_MIPS16_HI16_S
2040 /* VxWorks R_MIPS_GOT16 relocs never need a matching %lo();
2041 all GOT16 relocations evaluate to "G". */
2042 || (reloc == BFD_RELOC_MIPS_GOT16 && mips_pic != VXWORKS_PIC)));
1724}
1725
1726/* Return true if the given fixup is followed by a matching R_MIPS_LO16
1727 relocation. */
1728
1729static inline bfd_boolean
1730fixup_has_matching_lo_p (fixS *fixp)
1731{
1732 return (fixp->fx_next != NULL
2043}
2044
2045/* Return true if the given fixup is followed by a matching R_MIPS_LO16
2046 relocation. */
2047
2048static inline bfd_boolean
2049fixup_has_matching_lo_p (fixS *fixp)
2050{
2051 return (fixp->fx_next != NULL
1733 && fixp->fx_next->fx_r_type == BFD_RELOC_LO16
2052 && (fixp->fx_next->fx_r_type == BFD_RELOC_LO16
2053 || fixp->fx_next->fx_r_type == BFD_RELOC_MIPS16_LO16)
1734 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1735 && fixp->fx_offset == fixp->fx_next->fx_offset);
1736}
1737
1738/* See whether instruction IP reads register REG. CLASS is the type
1739 of register. */
1740
1741static int

--- 91 unchanged lines hidden (view full) ---

1833 return 0;
1834}
1835
1836/* Move all labels in insn_labels to the current insertion point. */
1837
1838static void
1839mips_move_labels (void)
1840{
2054 && fixp->fx_addsy == fixp->fx_next->fx_addsy
2055 && fixp->fx_offset == fixp->fx_next->fx_offset);
2056}
2057
2058/* See whether instruction IP reads register REG. CLASS is the type
2059 of register. */
2060
2061static int

--- 91 unchanged lines hidden (view full) ---

2153 return 0;
2154}
2155
2156/* Move all labels in insn_labels to the current insertion point. */
2157
2158static void
2159mips_move_labels (void)
2160{
2161 segment_info_type *si = seg_info (now_seg);
1841 struct insn_label_list *l;
1842 valueT val;
1843
2162 struct insn_label_list *l;
2163 valueT val;
2164
1844 for (l = insn_labels; l != NULL; l = l->next)
2165 for (l = si->label_list; l != NULL; l = l->next)
1845 {
1846 assert (S_GET_SEGMENT (l->label) == now_seg);
1847 symbol_set_frag (l->label, frag_now);
1848 val = (valueT) frag_now_fix ();
1849 /* mips16 text labels are stored as odd. */
1850 if (mips_opts.mips16)
1851 ++val;
1852 S_SET_VALUE (l->label, val);
1853 }
1854}
1855
2166 {
2167 assert (S_GET_SEGMENT (l->label) == now_seg);
2168 symbol_set_frag (l->label, frag_now);
2169 val = (valueT) frag_now_fix ();
2170 /* mips16 text labels are stored as odd. */
2171 if (mips_opts.mips16)
2172 ++val;
2173 S_SET_VALUE (l->label, val);
2174 }
2175}
2176
2177static bfd_boolean
2178s_is_linkonce (symbolS *sym, segT from_seg)
2179{
2180 bfd_boolean linkonce = FALSE;
2181 segT symseg = S_GET_SEGMENT (sym);
2182
2183 if (symseg != from_seg && !S_IS_LOCAL (sym))
2184 {
2185 if ((bfd_get_section_flags (stdoutput, symseg) & SEC_LINK_ONCE))
2186 linkonce = TRUE;
2187#ifdef OBJ_ELF
2188 /* The GNU toolchain uses an extension for ELF: a section
2189 beginning with the magic string .gnu.linkonce is a
2190 linkonce section. */
2191 if (strncmp (segment_name (symseg), ".gnu.linkonce",
2192 sizeof ".gnu.linkonce" - 1) == 0)
2193 linkonce = TRUE;
2194#endif
2195 }
2196 return linkonce;
2197}
2198
1856/* Mark instruction labels in mips16 mode. This permits the linker to
1857 handle them specially, such as generating jalx instructions when
1858 needed. We also make them odd for the duration of the assembly, in
1859 order to generate the right sort of code. We will make them even
1860 in the adjust_symtab routine, while leaving them marked. This is
1861 convenient for the debugger and the disassembler. The linker knows
1862 to make them odd again. */
1863
1864static void
1865mips16_mark_labels (void)
1866{
2199/* Mark instruction labels in mips16 mode. This permits the linker to
2200 handle them specially, such as generating jalx instructions when
2201 needed. We also make them odd for the duration of the assembly, in
2202 order to generate the right sort of code. We will make them even
2203 in the adjust_symtab routine, while leaving them marked. This is
2204 convenient for the debugger and the disassembler. The linker knows
2205 to make them odd again. */
2206
2207static void
2208mips16_mark_labels (void)
2209{
1867 if (mips_opts.mips16)
1868 {
1869 struct insn_label_list *l;
1870 valueT val;
2210 segment_info_type *si = seg_info (now_seg);
2211 struct insn_label_list *l;
1871
2212
1872 for (l = insn_labels; l != NULL; l = l->next)
1873 {
1874#ifdef OBJ_ELF
1875 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1876 S_SET_OTHER (l->label, STO_MIPS16);
2213 if (!mips_opts.mips16)
2214 return;
2215
2216 for (l = si->label_list; l != NULL; l = l->next)
2217 {
2218 symbolS *label = l->label;
2219
2220#if defined(OBJ_ELF) || defined(OBJ_MAYBE_ELF)
2221 if (IS_ELF)
2222 S_SET_OTHER (label, STO_MIPS16);
1877#endif
2223#endif
1878 val = S_GET_VALUE (l->label);
1879 if ((val & 1) == 0)
1880 S_SET_VALUE (l->label, val + 1);
1881 }
2224 if ((S_GET_VALUE (label) & 1) == 0
2225 /* Don't adjust the address if the label is global or weak, or
2226 in a link-once section, since we'll be emitting symbol reloc
2227 references to it which will be patched up by the linker, and
2228 the final value of the symbol may or may not be MIPS16. */
2229 && ! S_IS_WEAK (label)
2230 && ! S_IS_EXTERNAL (label)
2231 && ! s_is_linkonce (label, now_seg))
2232 S_SET_VALUE (label, S_GET_VALUE (label) | 1);
1882 }
1883}
1884
1885/* End the current frag. Make it a variant frag and record the
1886 relaxation info. */
1887
1888static void
1889relax_close_frag (void)

--- 308 unchanged lines hidden (view full) ---

2198/* Output an instruction. IP is the instruction information.
2199 ADDRESS_EXPR is an operand of the instruction to be used with
2200 RELOC_TYPE. */
2201
2202static void
2203append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2204 bfd_reloc_code_real_type *reloc_type)
2205{
2233 }
2234}
2235
2236/* End the current frag. Make it a variant frag and record the
2237 relaxation info. */
2238
2239static void
2240relax_close_frag (void)

--- 308 unchanged lines hidden (view full) ---

2549/* Output an instruction. IP is the instruction information.
2550 ADDRESS_EXPR is an operand of the instruction to be used with
2551 RELOC_TYPE. */
2552
2553static void
2554append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2555 bfd_reloc_code_real_type *reloc_type)
2556{
2206 register unsigned long prev_pinfo, pinfo;
2557 unsigned long prev_pinfo, pinfo;
2207 relax_stateT prev_insn_frag_type = 0;
2208 bfd_boolean relaxed_branch = FALSE;
2558 relax_stateT prev_insn_frag_type = 0;
2559 bfd_boolean relaxed_branch = FALSE;
2560 segment_info_type *si = seg_info (now_seg);
2209
2210 /* Mark instruction labels in mips16 mode. */
2211 mips16_mark_labels ();
2212
2213 prev_pinfo = history[0].insn_mo->pinfo;
2214 pinfo = ip->insn_mo->pinfo;
2215
2216 if (mips_relax.sequence != 2 && !mips_opts.noreorder)

--- 246 unchanged lines hidden (view full) ---

2463
2464 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2465 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
2466 bfd_get_reloc_size (howto),
2467 address_expr,
2468 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2469 reloc_type[0]);
2470
2561
2562 /* Mark instruction labels in mips16 mode. */
2563 mips16_mark_labels ();
2564
2565 prev_pinfo = history[0].insn_mo->pinfo;
2566 pinfo = ip->insn_mo->pinfo;
2567
2568 if (mips_relax.sequence != 2 && !mips_opts.noreorder)

--- 246 unchanged lines hidden (view full) ---

2815
2816 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2817 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
2818 bfd_get_reloc_size (howto),
2819 address_expr,
2820 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2821 reloc_type[0]);
2822
2823 /* Tag symbols that have a R_MIPS16_26 relocation against them. */
2824 if (reloc_type[0] == BFD_RELOC_MIPS16_JMP
2825 && ip->fixp[0]->fx_addsy)
2826 *symbol_get_tc (ip->fixp[0]->fx_addsy) = 1;
2827
2471 /* These relocations can have an addend that won't fit in
2472 4 octets for 64bit assembly. */
2473 if (HAVE_64BIT_GPRS
2474 && ! howto->partial_inplace
2475 && (reloc_type[0] == BFD_RELOC_16
2476 || reloc_type[0] == BFD_RELOC_32
2477 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2478 || reloc_type[0] == BFD_RELOC_HI16_S
2479 || reloc_type[0] == BFD_RELOC_LO16
2480 || reloc_type[0] == BFD_RELOC_GPREL16
2481 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2482 || reloc_type[0] == BFD_RELOC_GPREL32
2483 || reloc_type[0] == BFD_RELOC_64
2484 || reloc_type[0] == BFD_RELOC_CTOR
2485 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2486 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2487 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2488 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2489 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2828 /* These relocations can have an addend that won't fit in
2829 4 octets for 64bit assembly. */
2830 if (HAVE_64BIT_GPRS
2831 && ! howto->partial_inplace
2832 && (reloc_type[0] == BFD_RELOC_16
2833 || reloc_type[0] == BFD_RELOC_32
2834 || reloc_type[0] == BFD_RELOC_MIPS_JMP
2835 || reloc_type[0] == BFD_RELOC_HI16_S
2836 || reloc_type[0] == BFD_RELOC_LO16
2837 || reloc_type[0] == BFD_RELOC_GPREL16
2838 || reloc_type[0] == BFD_RELOC_MIPS_LITERAL
2839 || reloc_type[0] == BFD_RELOC_GPREL32
2840 || reloc_type[0] == BFD_RELOC_64
2841 || reloc_type[0] == BFD_RELOC_CTOR
2842 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2843 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2844 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2845 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2846 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2490 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2847 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT
2848 || reloc_type[0] == BFD_RELOC_MIPS16_GPREL
2849 || reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
2850 || reloc_type[0] == BFD_RELOC_MIPS16_LO16))
2491 ip->fixp[0]->fx_no_overflow = 1;
2492
2493 if (mips_relax.sequence)
2494 {
2495 if (mips_relax.first_fixup == 0)
2496 mips_relax.first_fixup = ip->fixp[0];
2497 }
2498 else if (reloc_needs_lo_p (*reloc_type))

--- 115 unchanged lines hidden (view full) ---

2614 not configured -with-gnu-as, it does not output the
2615 .set pseudo-ops. */
2616 || history[1].noreorder_p
2617 /* If the branch is itself the target of a branch, we
2618 can not swap. We cheat on this; all we check for is
2619 whether there is a label on this instruction. If
2620 there are any branches to anything other than a
2621 label, users must use .set noreorder. */
2851 ip->fixp[0]->fx_no_overflow = 1;
2852
2853 if (mips_relax.sequence)
2854 {
2855 if (mips_relax.first_fixup == 0)
2856 mips_relax.first_fixup = ip->fixp[0];
2857 }
2858 else if (reloc_needs_lo_p (*reloc_type))

--- 115 unchanged lines hidden (view full) ---

2974 not configured -with-gnu-as, it does not output the
2975 .set pseudo-ops. */
2976 || history[1].noreorder_p
2977 /* If the branch is itself the target of a branch, we
2978 can not swap. We cheat on this; all we check for is
2979 whether there is a label on this instruction. If
2980 there are any branches to anything other than a
2981 label, users must use .set noreorder. */
2622 || insn_labels != NULL
2982 || si->label_list != NULL
2623 /* If the previous instruction is in a variant frag
2624 other than this branch's one, we cannot do the swap.
2625 This does not apply to the mips16, which uses variant
2626 frags for different purposes. */
2627 || (! mips_opts.mips16
2628 && prev_insn_frag_type == rs_machine_dependent)
2629 /* Check for conflicts between the branch and the instructions
2630 before the candidate delay slot. */

--- 90 unchanged lines hidden (view full) ---

2721 || (mips_opts.mips16 && history[0].fixp[0])
2722 /* If the previous instruction is a sync, sync.l, or
2723 sync.p, we can not swap. */
2724 || (prev_pinfo & INSN_SYNC))
2725 {
2726 if (mips_opts.mips16
2727 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
2728 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
2983 /* If the previous instruction is in a variant frag
2984 other than this branch's one, we cannot do the swap.
2985 This does not apply to the mips16, which uses variant
2986 frags for different purposes. */
2987 || (! mips_opts.mips16
2988 && prev_insn_frag_type == rs_machine_dependent)
2989 /* Check for conflicts between the branch and the instructions
2990 before the candidate delay slot. */

--- 90 unchanged lines hidden (view full) ---

3081 || (mips_opts.mips16 && history[0].fixp[0])
3082 /* If the previous instruction is a sync, sync.l, or
3083 sync.p, we can not swap. */
3084 || (prev_pinfo & INSN_SYNC))
3085 {
3086 if (mips_opts.mips16
3087 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
3088 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
2729 && (mips_opts.isa == ISA_MIPS32
2730 || mips_opts.isa == ISA_MIPS32R2
2731 || mips_opts.isa == ISA_MIPS64
2732 || mips_opts.isa == ISA_MIPS64R2))
3089 && ISA_SUPPORTS_MIPS16E)
2733 {
2734 /* Convert MIPS16 jr/jalr into a "compact" jump. */
2735 ip->insn_opcode |= 0x0080;
2736 install_insn (ip);
2737 insert_into_history (0, 1, ip);
2738 }
2739 else
2740 {

--- 265 unchanged lines hidden (view full) ---

3006
3007 r[0] = BFD_RELOC_UNUSED;
3008 r[1] = BFD_RELOC_UNUSED;
3009 r[2] = BFD_RELOC_UNUSED;
3010 mo = (struct mips_opcode *) hash_find (op_hash, name);
3011 assert (mo);
3012 assert (strcmp (name, mo->name) == 0);
3013
3090 {
3091 /* Convert MIPS16 jr/jalr into a "compact" jump. */
3092 ip->insn_opcode |= 0x0080;
3093 install_insn (ip);
3094 insert_into_history (0, 1, ip);
3095 }
3096 else
3097 {

--- 265 unchanged lines hidden (view full) ---

3363
3364 r[0] = BFD_RELOC_UNUSED;
3365 r[1] = BFD_RELOC_UNUSED;
3366 r[2] = BFD_RELOC_UNUSED;
3367 mo = (struct mips_opcode *) hash_find (op_hash, name);
3368 assert (mo);
3369 assert (strcmp (name, mo->name) == 0);
3370
3014 /* Search until we get a match for NAME. It is assumed here that
3015 macros will never generate MDMX or MIPS-3D instructions. */
3016 while (strcmp (fmt, mo->args) != 0
3017 || mo->pinfo == INSN_MACRO
3018 || !OPCODE_IS_MEMBER (mo,
3371 while (1)
3372 {
3373 /* Search until we get a match for NAME. It is assumed here that
3374 macros will never generate MDMX, MIPS-3D, or MT instructions. */
3375 if (strcmp (fmt, mo->args) == 0
3376 && mo->pinfo != INSN_MACRO
3377 && OPCODE_IS_MEMBER (mo,
3019 (mips_opts.isa
3378 (mips_opts.isa
3020 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3379 | (mips_opts.mips16 ? INSN_MIPS16 : 0)
3380 | (mips_opts.ase_dsp ? INSN_DSP : 0)
3381 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
3382 ? INSN_DSP64 : 0)
3383 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
3384 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
3021 mips_opts.arch)
3385 mips_opts.arch)
3022 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
3023 {
3386 && (mips_opts.arch != CPU_R4650 || (mo->pinfo & FP_D) == 0))
3387 break;
3388
3024 ++mo;
3025 assert (mo->name);
3026 assert (strcmp (name, mo->name) == 0);
3027 }
3028
3029 create_insn (&insn, mo);
3030 for (;;)
3031 {

--- 34 unchanged lines hidden (view full) ---

3066 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3067 continue;
3068
3069 default:
3070 internalError ();
3071 }
3072 continue;
3073
3389 ++mo;
3390 assert (mo->name);
3391 assert (strcmp (name, mo->name) == 0);
3392 }
3393
3394 create_insn (&insn, mo);
3395 for (;;)
3396 {

--- 34 unchanged lines hidden (view full) ---

3431 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3432 continue;
3433
3434 default:
3435 internalError ();
3436 }
3437 continue;
3438
3439 case '2':
3440 INSERT_OPERAND (BP, insn, va_arg (args, int));
3441 continue;
3442
3074 case 't':
3075 case 'w':
3076 case 'E':
3077 INSERT_OPERAND (RT, insn, va_arg (args, int));
3078 continue;
3079
3080 case 'c':
3081 INSERT_OPERAND (CODE, insn, va_arg (args, int));

--- 111 unchanged lines hidden (view full) ---

3193 continue;
3194
3195 case 'a':
3196 assert (ep != NULL);
3197 *r = BFD_RELOC_MIPS_JMP;
3198 continue;
3199
3200 case 'C':
3443 case 't':
3444 case 'w':
3445 case 'E':
3446 INSERT_OPERAND (RT, insn, va_arg (args, int));
3447 continue;
3448
3449 case 'c':
3450 INSERT_OPERAND (CODE, insn, va_arg (args, int));

--- 111 unchanged lines hidden (view full) ---

3562 continue;
3563
3564 case 'a':
3565 assert (ep != NULL);
3566 *r = BFD_RELOC_MIPS_JMP;
3567 continue;
3568
3569 case 'C':
3201 insn.insn_opcode |= va_arg (args, unsigned long);
3570 INSERT_OPERAND (COPZ, insn, va_arg (args, unsigned long));
3202 continue;
3203
3571 continue;
3572
3573 case 'k':
3574 INSERT_OPERAND (CACHE, insn, va_arg (args, unsigned long));
3575 continue;
3576
3204 default:
3205 internalError ();
3206 }
3207 break;
3208 }
3209 va_end (args);
3210 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3211

--- 65 unchanged lines hidden (view full) ---

3277 continue;
3278
3279 case 'Y':
3280 {
3281 int regno;
3282
3283 regno = va_arg (args, int);
3284 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3577 default:
3578 internalError ();
3579 }
3580 break;
3581 }
3582 va_end (args);
3583 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3584

--- 65 unchanged lines hidden (view full) ---

3650 continue;
3651
3652 case 'Y':
3653 {
3654 int regno;
3655
3656 regno = va_arg (args, int);
3657 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
3285 insn.insn_opcode |= regno << MIPS16OP_SH_REG32R;
3658 MIPS16_INSERT_OPERAND (REG32R, insn, regno);
3286 }
3287 continue;
3288
3289 case '<':
3290 case '>':
3291 case '4':
3292 case '5':
3293 case 'H':

--- 99 unchanged lines hidden (view full) ---

3393 const char *fmt = "t,u";
3394
3395 assert (! mips_opts.mips16);
3396
3397 high_expr = *ep;
3398
3399 if (high_expr.X_op == O_constant)
3400 {
3659 }
3660 continue;
3661
3662 case '<':
3663 case '>':
3664 case '4':
3665 case '5':
3666 case 'H':

--- 99 unchanged lines hidden (view full) ---

3766 const char *fmt = "t,u";
3767
3768 assert (! mips_opts.mips16);
3769
3770 high_expr = *ep;
3771
3772 if (high_expr.X_op == O_constant)
3773 {
3401 /* we can compute the instruction now without a relocation entry */
3774 /* We can compute the instruction now without a relocation entry. */
3402 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3403 >> 16) & 0xffff;
3404 *r = BFD_RELOC_UNUSED;
3405 }
3406 else
3407 {
3408 assert (ep->X_op == O_symbol);
3409 /* _gp_disp is a special case, used from s_cpload.

--- 760 unchanged lines hidden (view full) ---

4170 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4171 * first load register 'at' with zero and use it as the base register. The
4172 * mips assembler simply uses register $zero. Just one tiny optimization
4173 * we're missing.
4174 */
4175static void
4176macro (struct mips_cl_insn *ip)
4177{
3775 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3776 >> 16) & 0xffff;
3777 *r = BFD_RELOC_UNUSED;
3778 }
3779 else
3780 {
3781 assert (ep->X_op == O_symbol);
3782 /* _gp_disp is a special case, used from s_cpload.

--- 760 unchanged lines hidden (view full) ---

4543 * constant expression in the first 64k of memory (ie ld $2,0x4000c) we
4544 * first load register 'at' with zero and use it as the base register. The
4545 * mips assembler simply uses register $zero. Just one tiny optimization
4546 * we're missing.
4547 */
4548static void
4549macro (struct mips_cl_insn *ip)
4550{
4178 register int treg, sreg, dreg, breg;
4551 int treg, sreg, dreg, breg;
4179 int tempreg;
4180 int mask;
4181 int used_at = 0;
4182 expressionS expr1;
4183 const char *s;
4184 const char *s2;
4185 const char *fmt;
4186 int likely = 0;

--- 103 unchanged lines hidden (view full) ---

4290 break;
4291 }
4292
4293 used_at = 1;
4294 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4295 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4296 break;
4297
4552 int tempreg;
4553 int mask;
4554 int used_at = 0;
4555 expressionS expr1;
4556 const char *s;
4557 const char *s2;
4558 const char *fmt;
4559 int likely = 0;

--- 103 unchanged lines hidden (view full) ---

4663 break;
4664 }
4665
4666 used_at = 1;
4667 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4668 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4669 break;
4670
4671 case M_BALIGN:
4672 switch (imm_expr.X_add_number)
4673 {
4674 case 0:
4675 macro_build (NULL, "nop", "");
4676 break;
4677 case 2:
4678 macro_build (NULL, "packrl.ph", "d,s,t", treg, treg, sreg);
4679 break;
4680 default:
4681 macro_build (NULL, "balign", "t,s,2", treg, sreg,
4682 (int)imm_expr.X_add_number);
4683 break;
4684 }
4685 break;
4686
4298 case M_BEQ_I:
4299 s = "beq";
4300 goto beq_i;
4301 case M_BEQL_I:
4302 s = "beql";
4303 likely = 1;
4304 goto beq_i;
4305 case M_BNE_I:

--- 1376 unchanged lines hidden (view full) ---

5682 expr1.X_add_number = mips_cprestore_offset;
5683 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5684 mips_gp_register,
5685 mips_frame_reg,
5686 HAVE_64BIT_ADDRESSES);
5687 }
5688 }
5689 }
4687 case M_BEQ_I:
4688 s = "beq";
4689 goto beq_i;
4690 case M_BEQL_I:
4691 s = "beql";
4692 likely = 1;
4693 goto beq_i;
4694 case M_BNE_I:

--- 1376 unchanged lines hidden (view full) ---

6071 expr1.X_add_number = mips_cprestore_offset;
6072 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
6073 mips_gp_register,
6074 mips_frame_reg,
6075 HAVE_64BIT_ADDRESSES);
6076 }
6077 }
6078 }
6079 else if (mips_pic == VXWORKS_PIC)
6080 as_bad (_("Non-PIC jump used in PIC library"));
5690 else
5691 abort ();
5692
5693 break;
5694
5695 case M_LB_AB:
5696 s = "lb";
5697 goto ld;

--- 130 unchanged lines hidden (view full) ---

5828 s = "swr";
5829 goto st;
5830 case M_SC_AB:
5831 s = "sc";
5832 goto st;
5833 case M_SCD_AB:
5834 s = "scd";
5835 goto st;
6081 else
6082 abort ();
6083
6084 break;
6085
6086 case M_LB_AB:
6087 s = "lb";
6088 goto ld;

--- 130 unchanged lines hidden (view full) ---

6219 s = "swr";
6220 goto st;
6221 case M_SC_AB:
6222 s = "sc";
6223 goto st;
6224 case M_SCD_AB:
6225 s = "scd";
6226 goto st;
6227 case M_CACHE_AB:
6228 s = "cache";
6229 goto st;
5836 case M_SDC1_AB:
5837 if (mips_opts.arch == CPU_R4650)
5838 {
5839 as_bad (_("opcode not supported on this processor"));
5840 break;
5841 }
5842 s = "sdc1";
5843 coproc = 1;

--- 30 unchanged lines hidden (view full) ---

5874 /* Itbl support may require additional care here. */
5875 if (mask == M_LWC1_AB
5876 || mask == M_SWC1_AB
5877 || mask == M_LDC1_AB
5878 || mask == M_SDC1_AB
5879 || mask == M_L_DAB
5880 || mask == M_S_DAB)
5881 fmt = "T,o(b)";
6230 case M_SDC1_AB:
6231 if (mips_opts.arch == CPU_R4650)
6232 {
6233 as_bad (_("opcode not supported on this processor"));
6234 break;
6235 }
6236 s = "sdc1";
6237 coproc = 1;

--- 30 unchanged lines hidden (view full) ---

6268 /* Itbl support may require additional care here. */
6269 if (mask == M_LWC1_AB
6270 || mask == M_SWC1_AB
6271 || mask == M_LDC1_AB
6272 || mask == M_SDC1_AB
6273 || mask == M_L_DAB
6274 || mask == M_S_DAB)
6275 fmt = "T,o(b)";
6276 else if (mask == M_CACHE_AB)
6277 fmt = "k,o(b)";
5882 else if (coproc)
5883 fmt = "E,o(b)";
5884 else
5885 fmt = "t,o(b)";
5886
5887 if (offset_expr.X_op != O_constant
5888 && offset_expr.X_op != O_symbol)
5889 {

--- 943 unchanged lines hidden (view full) ---

6833 }
6834 if (mips_opts.noat && used_at)
6835 as_bad (_("Macro used $at after \".set noat\""));
6836}
6837
6838static void
6839macro2 (struct mips_cl_insn *ip)
6840{
6278 else if (coproc)
6279 fmt = "E,o(b)";
6280 else
6281 fmt = "t,o(b)";
6282
6283 if (offset_expr.X_op != O_constant
6284 && offset_expr.X_op != O_symbol)
6285 {

--- 943 unchanged lines hidden (view full) ---

7229 }
7230 if (mips_opts.noat && used_at)
7231 as_bad (_("Macro used $at after \".set noat\""));
7232}
7233
7234static void
7235macro2 (struct mips_cl_insn *ip)
7236{
6841 register int treg, sreg, dreg, breg;
7237 int treg, sreg, dreg, breg;
6842 int tempreg;
6843 int mask;
6844 int used_at;
6845 expressionS expr1;
6846 const char *s;
6847 const char *s2;
6848 const char *fmt;
6849 int likely = 0;

--- 1119 unchanged lines hidden (view full) ---

7969 case ',': break;
7970 case '(': break;
7971 case ')': break;
7972 case '^': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
7973 case '~': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
7974 case '+':
7975 switch (c = *p++)
7976 {
7238 int tempreg;
7239 int mask;
7240 int used_at;
7241 expressionS expr1;
7242 const char *s;
7243 const char *s2;
7244 const char *fmt;
7245 int likely = 0;

--- 1119 unchanged lines hidden (view full) ---

8365 case ',': break;
8366 case '(': break;
8367 case ')': break;
8368 case '^': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
8369 case '~': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
8370 case '+':
8371 switch (c = *p++)
8372 {
8373 case '1': USE_BITS (OP_MASK_UDI1, OP_SH_UDI1); break;
8374 case '2': USE_BITS (OP_MASK_UDI2, OP_SH_UDI2); break;
8375 case '3': USE_BITS (OP_MASK_UDI3, OP_SH_UDI3); break;
8376 case '4': USE_BITS (OP_MASK_UDI4, OP_SH_UDI4); break;
7977 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7978 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7979 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7980 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7981 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7982 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7983 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7984 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;

--- 59 unchanged lines hidden (view full) ---

8044 case 'z': break;
8045 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8046 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8047 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8048 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8049 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8050 case '[': break;
8051 case ']': break;
8377 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8378 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8379 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
8380 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
8381 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
8382 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
8383 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
8384 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;

--- 59 unchanged lines hidden (view full) ---

8444 case 'z': break;
8445 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8446 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8447 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8448 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8449 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8450 case '[': break;
8451 case ']': break;
8452 case '2': USE_BITS (OP_MASK_BP, OP_SH_BP); break;
8052 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8053 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8054 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8055 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8056 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8057 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8058 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8059 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;

--- 15 unchanged lines hidden (view full) ---

8075 {
8076 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8077 ~used_bits & 0xffffffff, opc->name, opc->args);
8078 return 0;
8079 }
8080 return 1;
8081}
8082
8453 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8454 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8455 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8456 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8457 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8458 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8459 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8460 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;

--- 15 unchanged lines hidden (view full) ---

8476 {
8477 as_bad (_("internal: bad mips opcode (bits 0x%lx undefined): %s %s"),
8478 ~used_bits & 0xffffffff, opc->name, opc->args);
8479 return 0;
8480 }
8481 return 1;
8482}
8483
8484/* UDI immediates. */
8485struct mips_immed {
8486 char type;
8487 unsigned int shift;
8488 unsigned long mask;
8489 const char * desc;
8490};
8491
8492static const struct mips_immed mips_immed[] = {
8493 { '1', OP_SH_UDI1, OP_MASK_UDI1, 0},
8494 { '2', OP_SH_UDI2, OP_MASK_UDI2, 0},
8495 { '3', OP_SH_UDI3, OP_MASK_UDI3, 0},
8496 { '4', OP_SH_UDI4, OP_MASK_UDI4, 0},
8497 { 0,0,0,0 }
8498};
8499
8500/* Check whether an odd floating-point register is allowed. */
8501static int
8502mips_oddfpreg_ok (const struct mips_opcode *insn, int argnum)
8503{
8504 const char *s = insn->name;
8505
8506 if (insn->pinfo == INSN_MACRO)
8507 /* Let a macro pass, we'll catch it later when it is expanded. */
8508 return 1;
8509
8510 if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa))
8511 {
8512 /* Allow odd registers for single-precision ops. */
8513 switch (insn->pinfo & (FP_S | FP_D))
8514 {
8515 case FP_S:
8516 case 0:
8517 return 1; /* both single precision - ok */
8518 case FP_D:
8519 return 0; /* both double precision - fail */
8520 default:
8521 break;
8522 }
8523
8524 /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */
8525 s = strchr (insn->name, '.');
8526 if (argnum == 2)
8527 s = s != NULL ? strchr (s + 1, '.') : NULL;
8528 return (s != NULL && (s[1] == 'w' || s[1] == 's'));
8529 }
8530
8531 /* Single-precision coprocessor loads and moves are OK too. */
8532 if ((insn->pinfo & FP_S)
8533 && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY
8534 | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY)))
8535 return 1;
8536
8537 return 0;
8538}
8539
8083/* This routine assembles an instruction into its binary format. As a
8084 side effect, it sets one of the global variables imm_reloc or
8085 offset_reloc to the type of relocation to do if one of the operands
8086 is an address expression. */
8087
8088static void
8089mips_ip (char *str, struct mips_cl_insn *ip)
8090{

--- 4 unchanged lines hidden (view full) ---

8095 char *argsStart;
8096 unsigned int regno;
8097 unsigned int lastregno = 0;
8098 unsigned int lastpos = 0;
8099 unsigned int limlo, limhi;
8100 char *s_reset;
8101 char save_c = 0;
8102 offsetT min_range, max_range;
8540/* This routine assembles an instruction into its binary format. As a
8541 side effect, it sets one of the global variables imm_reloc or
8542 offset_reloc to the type of relocation to do if one of the operands
8543 is an address expression. */
8544
8545static void
8546mips_ip (char *str, struct mips_cl_insn *ip)
8547{

--- 4 unchanged lines hidden (view full) ---

8552 char *argsStart;
8553 unsigned int regno;
8554 unsigned int lastregno = 0;
8555 unsigned int lastpos = 0;
8556 unsigned int limlo, limhi;
8557 char *s_reset;
8558 char save_c = 0;
8559 offsetT min_range, max_range;
8560 int argnum;
8561 unsigned int rtype;
8103
8104 insn_error = NULL;
8105
8106 /* If the instruction contains a '.', we first try to match an instruction
8107 including the '.'. Then we try again without the '.'. */
8108 insn = NULL;
8109 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8110 continue;

--- 44 unchanged lines hidden (view full) ---

8155 for (;;)
8156 {
8157 bfd_boolean ok;
8158
8159 assert (strcmp (insn->name, str) == 0);
8160
8161 if (OPCODE_IS_MEMBER (insn,
8162 (mips_opts.isa
8562
8563 insn_error = NULL;
8564
8565 /* If the instruction contains a '.', we first try to match an instruction
8566 including the '.'. Then we try again without the '.'. */
8567 insn = NULL;
8568 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8569 continue;

--- 44 unchanged lines hidden (view full) ---

8614 for (;;)
8615 {
8616 bfd_boolean ok;
8617
8618 assert (strcmp (insn->name, str) == 0);
8619
8620 if (OPCODE_IS_MEMBER (insn,
8621 (mips_opts.isa
8622 /* We don't check for mips_opts.mips16 here since
8623 we want to allow jalx if -mips16 was specified
8624 on the command line. */
8163 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8164 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8165 | (mips_opts.ase_dsp ? INSN_DSP : 0)
8625 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8626 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8627 | (mips_opts.ase_dsp ? INSN_DSP : 0)
8628 | ((mips_opts.ase_dsp && ISA_SUPPORTS_DSP64_ASE)
8629 ? INSN_DSP64 : 0)
8630 | (mips_opts.ase_dspr2 ? INSN_DSPR2 : 0)
8166 | (mips_opts.ase_mt ? INSN_MT : 0)
8631 | (mips_opts.ase_mt ? INSN_MT : 0)
8167 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8632 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)
8633 | (mips_opts.ase_smartmips ? INSN_SMARTMIPS : 0)),
8168 mips_opts.arch))
8169 ok = TRUE;
8170 else
8171 ok = FALSE;
8172
8173 if (insn->pinfo != INSN_MACRO)
8174 {
8175 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)

--- 98 unchanged lines hidden (view full) ---

8274 if (save_c)
8275 *(--s) = save_c;
8276 return;
8277 }
8278 }
8279
8280 create_insn (ip, insn);
8281 insn_error = NULL;
8634 mips_opts.arch))
8635 ok = TRUE;
8636 else
8637 ok = FALSE;
8638
8639 if (insn->pinfo != INSN_MACRO)
8640 {
8641 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)

--- 98 unchanged lines hidden (view full) ---

8740 if (save_c)
8741 *(--s) = save_c;
8742 return;
8743 }
8744 }
8745
8746 create_insn (ip, insn);
8747 insn_error = NULL;
8748 argnum = 1;
8282 for (args = insn->args;; ++args)
8283 {
8284 int is_mdmx;
8285
8286 s += strspn (s, " \t");
8287 is_mdmx = 0;
8288 switch (*args)
8289 {
8290 case '\0': /* end of args */
8291 if (*s == '\0')
8292 return;
8293 break;
8294
8749 for (args = insn->args;; ++args)
8750 {
8751 int is_mdmx;
8752
8753 s += strspn (s, " \t");
8754 is_mdmx = 0;
8755 switch (*args)
8756 {
8757 case '\0': /* end of args */
8758 if (*s == '\0')
8759 return;
8760 break;
8761
8762 case '2': /* dsp 2-bit unsigned immediate in bit 11 */
8763 my_getExpression (&imm_expr, s);
8764 check_absolute_expr (ip, &imm_expr);
8765 if ((unsigned long) imm_expr.X_add_number != 1
8766 && (unsigned long) imm_expr.X_add_number != 3)
8767 {
8768 as_bad (_("BALIGN immediate not 1 or 3 (%lu)"),
8769 (unsigned long) imm_expr.X_add_number);
8770 }
8771 INSERT_OPERAND (BP, *ip, imm_expr.X_add_number);
8772 imm_expr.X_op = O_absent;
8773 s = expr_end;
8774 continue;
8775
8295 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8296 my_getExpression (&imm_expr, s);
8297 check_absolute_expr (ip, &imm_expr);
8298 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8299 {
8776 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8777 my_getExpression (&imm_expr, s);
8778 check_absolute_expr (ip, &imm_expr);
8779 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8780 {
8300 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8301 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8302 imm_expr.X_add_number &= OP_MASK_SA3;
8781 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8782 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8303 }
8783 }
8304 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
8784 INSERT_OPERAND (SA3, *ip, imm_expr.X_add_number);
8305 imm_expr.X_op = O_absent;
8306 s = expr_end;
8307 continue;
8308
8309 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8310 my_getExpression (&imm_expr, s);
8311 check_absolute_expr (ip, &imm_expr);
8312 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8313 {
8785 imm_expr.X_op = O_absent;
8786 s = expr_end;
8787 continue;
8788
8789 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8790 my_getExpression (&imm_expr, s);
8791 check_absolute_expr (ip, &imm_expr);
8792 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8793 {
8314 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8315 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8316 imm_expr.X_add_number &= OP_MASK_SA4;
8794 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8795 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8317 }
8796 }
8318 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
8797 INSERT_OPERAND (SA4, *ip, imm_expr.X_add_number);
8319 imm_expr.X_op = O_absent;
8320 s = expr_end;
8321 continue;
8322
8323 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8324 my_getExpression (&imm_expr, s);
8325 check_absolute_expr (ip, &imm_expr);
8326 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8327 {
8798 imm_expr.X_op = O_absent;
8799 s = expr_end;
8800 continue;
8801
8802 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8803 my_getExpression (&imm_expr, s);
8804 check_absolute_expr (ip, &imm_expr);
8805 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8806 {
8328 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8329 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8330 imm_expr.X_add_number &= OP_MASK_IMM8;
8807 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8808 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8331 }
8809 }
8332 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
8810 INSERT_OPERAND (IMM8, *ip, imm_expr.X_add_number);
8333 imm_expr.X_op = O_absent;
8334 s = expr_end;
8335 continue;
8336
8337 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8338 my_getExpression (&imm_expr, s);
8339 check_absolute_expr (ip, &imm_expr);
8340 if (imm_expr.X_add_number & ~OP_MASK_RS)
8341 {
8811 imm_expr.X_op = O_absent;
8812 s = expr_end;
8813 continue;
8814
8815 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8816 my_getExpression (&imm_expr, s);
8817 check_absolute_expr (ip, &imm_expr);
8818 if (imm_expr.X_add_number & ~OP_MASK_RS)
8819 {
8342 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8343 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8344 imm_expr.X_add_number &= OP_MASK_RS;
8820 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8821 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8345 }
8822 }
8346 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
8823 INSERT_OPERAND (RS, *ip, imm_expr.X_add_number);
8347 imm_expr.X_op = O_absent;
8348 s = expr_end;
8349 continue;
8350
8351 case '7': /* four dsp accumulators in bits 11,12 */
8352 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8353 s[3] >= '0' && s[3] <= '3')
8354 {
8355 regno = s[3] - '0';
8356 s += 4;
8824 imm_expr.X_op = O_absent;
8825 s = expr_end;
8826 continue;
8827
8828 case '7': /* four dsp accumulators in bits 11,12 */
8829 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8830 s[3] >= '0' && s[3] <= '3')
8831 {
8832 regno = s[3] - '0';
8833 s += 4;
8357 ip->insn_opcode |= regno << OP_SH_DSPACC;
8834 INSERT_OPERAND (DSPACC, *ip, regno);
8358 continue;
8359 }
8360 else
8361 as_bad (_("Invalid dsp acc register"));
8362 break;
8363
8364 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8365 my_getExpression (&imm_expr, s);
8366 check_absolute_expr (ip, &imm_expr);
8367 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8368 {
8835 continue;
8836 }
8837 else
8838 as_bad (_("Invalid dsp acc register"));
8839 break;
8840
8841 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8842 my_getExpression (&imm_expr, s);
8843 check_absolute_expr (ip, &imm_expr);
8844 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8845 {
8369 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8370 OP_MASK_WRDSP,
8371 (unsigned long) imm_expr.X_add_number);
8372 imm_expr.X_add_number &= OP_MASK_WRDSP;
8846 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8847 OP_MASK_WRDSP,
8848 (unsigned long) imm_expr.X_add_number);
8373 }
8849 }
8374 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
8850 INSERT_OPERAND (WRDSP, *ip, imm_expr.X_add_number);
8375 imm_expr.X_op = O_absent;
8376 s = expr_end;
8377 continue;
8378
8379 case '9': /* four dsp accumulators in bits 21,22 */
8380 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8381 s[3] >= '0' && s[3] <= '3')
8382 {
8383 regno = s[3] - '0';
8384 s += 4;
8851 imm_expr.X_op = O_absent;
8852 s = expr_end;
8853 continue;
8854
8855 case '9': /* four dsp accumulators in bits 21,22 */
8856 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8857 s[3] >= '0' && s[3] <= '3')
8858 {
8859 regno = s[3] - '0';
8860 s += 4;
8385 ip->insn_opcode |= regno << OP_SH_DSPACC_S;
8861 INSERT_OPERAND (DSPACC_S, *ip, regno);
8386 continue;
8387 }
8388 else
8389 as_bad (_("Invalid dsp acc register"));
8390 break;
8391
8392 case '0': /* dsp 6-bit signed immediate in bit 20 */
8393 my_getExpression (&imm_expr, s);
8394 check_absolute_expr (ip, &imm_expr);
8395 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8396 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8397 if (imm_expr.X_add_number < min_range ||
8398 imm_expr.X_add_number > max_range)
8399 {
8862 continue;
8863 }
8864 else
8865 as_bad (_("Invalid dsp acc register"));
8866 break;
8867
8868 case '0': /* dsp 6-bit signed immediate in bit 20 */
8869 my_getExpression (&imm_expr, s);
8870 check_absolute_expr (ip, &imm_expr);
8871 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8872 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8873 if (imm_expr.X_add_number < min_range ||
8874 imm_expr.X_add_number > max_range)
8875 {
8400 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8401 (long) min_range, (long) max_range,
8402 (long) imm_expr.X_add_number);
8876 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8877 (long) min_range, (long) max_range,
8878 (long) imm_expr.X_add_number);
8403 }
8879 }
8404 imm_expr.X_add_number &= OP_MASK_DSPSFT;
8405 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8406 << OP_SH_DSPSFT);
8880 INSERT_OPERAND (DSPSFT, *ip, imm_expr.X_add_number);
8407 imm_expr.X_op = O_absent;
8408 s = expr_end;
8409 continue;
8410
8411 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8412 my_getExpression (&imm_expr, s);
8413 check_absolute_expr (ip, &imm_expr);
8414 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8415 {
8881 imm_expr.X_op = O_absent;
8882 s = expr_end;
8883 continue;
8884
8885 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8886 my_getExpression (&imm_expr, s);
8887 check_absolute_expr (ip, &imm_expr);
8888 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8889 {
8416 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8417 OP_MASK_RDDSP,
8418 (unsigned long) imm_expr.X_add_number);
8419 imm_expr.X_add_number &= OP_MASK_RDDSP;
8890 as_bad (_("DSP immediate not in range 0..%d (%lu)"),
8891 OP_MASK_RDDSP,
8892 (unsigned long) imm_expr.X_add_number);
8420 }
8893 }
8421 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
8894 INSERT_OPERAND (RDDSP, *ip, imm_expr.X_add_number);
8422 imm_expr.X_op = O_absent;
8423 s = expr_end;
8424 continue;
8425
8426 case ':': /* dsp 7-bit signed immediate in bit 19 */
8427 my_getExpression (&imm_expr, s);
8428 check_absolute_expr (ip, &imm_expr);
8429 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8430 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8431 if (imm_expr.X_add_number < min_range ||
8432 imm_expr.X_add_number > max_range)
8433 {
8895 imm_expr.X_op = O_absent;
8896 s = expr_end;
8897 continue;
8898
8899 case ':': /* dsp 7-bit signed immediate in bit 19 */
8900 my_getExpression (&imm_expr, s);
8901 check_absolute_expr (ip, &imm_expr);
8902 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8903 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8904 if (imm_expr.X_add_number < min_range ||
8905 imm_expr.X_add_number > max_range)
8906 {
8434 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8435 (long) min_range, (long) max_range,
8436 (long) imm_expr.X_add_number);
8907 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8908 (long) min_range, (long) max_range,
8909 (long) imm_expr.X_add_number);
8437 }
8910 }
8438 imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
8439 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8440 << OP_SH_DSPSFT_7);
8911 INSERT_OPERAND (DSPSFT_7, *ip, imm_expr.X_add_number);
8441 imm_expr.X_op = O_absent;
8442 s = expr_end;
8443 continue;
8444
8445 case '@': /* dsp 10-bit signed immediate in bit 16 */
8446 my_getExpression (&imm_expr, s);
8447 check_absolute_expr (ip, &imm_expr);
8448 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8449 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8450 if (imm_expr.X_add_number < min_range ||
8451 imm_expr.X_add_number > max_range)
8452 {
8912 imm_expr.X_op = O_absent;
8913 s = expr_end;
8914 continue;
8915
8916 case '@': /* dsp 10-bit signed immediate in bit 16 */
8917 my_getExpression (&imm_expr, s);
8918 check_absolute_expr (ip, &imm_expr);
8919 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8920 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8921 if (imm_expr.X_add_number < min_range ||
8922 imm_expr.X_add_number > max_range)
8923 {
8453 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8454 (long) min_range, (long) max_range,
8455 (long) imm_expr.X_add_number);
8924 as_bad (_("DSP immediate not in range %ld..%ld (%ld)"),
8925 (long) min_range, (long) max_range,
8926 (long) imm_expr.X_add_number);
8456 }
8927 }
8457 imm_expr.X_add_number &= OP_MASK_IMM10;
8458 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8459 << OP_SH_IMM10);
8928 INSERT_OPERAND (IMM10, *ip, imm_expr.X_add_number);
8460 imm_expr.X_op = O_absent;
8461 s = expr_end;
8462 continue;
8463
8929 imm_expr.X_op = O_absent;
8930 s = expr_end;
8931 continue;
8932
8464 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8933 case '!': /* MT usermode flag bit. */
8465 my_getExpression (&imm_expr, s);
8466 check_absolute_expr (ip, &imm_expr);
8467 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8934 my_getExpression (&imm_expr, s);
8935 check_absolute_expr (ip, &imm_expr);
8936 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8468 {
8469 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8470 OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
8471 imm_expr.X_add_number &= OP_MASK_MT_U;
8472 }
8473 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
8937 as_bad (_("MT usermode bit not 0 or 1 (%lu)"),
8938 (unsigned long) imm_expr.X_add_number);
8939 INSERT_OPERAND (MT_U, *ip, imm_expr.X_add_number);
8474 imm_expr.X_op = O_absent;
8475 s = expr_end;
8476 continue;
8477
8940 imm_expr.X_op = O_absent;
8941 s = expr_end;
8942 continue;
8943
8478 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8944 case '$': /* MT load high flag bit. */
8479 my_getExpression (&imm_expr, s);
8480 check_absolute_expr (ip, &imm_expr);
8481 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8945 my_getExpression (&imm_expr, s);
8946 check_absolute_expr (ip, &imm_expr);
8947 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8482 {
8483 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8484 OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
8485 imm_expr.X_add_number &= OP_MASK_MT_H;
8486 }
8487 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
8948 as_bad (_("MT load high bit not 0 or 1 (%lu)"),
8949 (unsigned long) imm_expr.X_add_number);
8950 INSERT_OPERAND (MT_H, *ip, imm_expr.X_add_number);
8488 imm_expr.X_op = O_absent;
8489 s = expr_end;
8490 continue;
8491
8492 case '*': /* four dsp accumulators in bits 18,19 */
8493 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8494 s[3] >= '0' && s[3] <= '3')
8495 {
8496 regno = s[3] - '0';
8497 s += 4;
8951 imm_expr.X_op = O_absent;
8952 s = expr_end;
8953 continue;
8954
8955 case '*': /* four dsp accumulators in bits 18,19 */
8956 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8957 s[3] >= '0' && s[3] <= '3')
8958 {
8959 regno = s[3] - '0';
8960 s += 4;
8498 ip->insn_opcode |= regno << OP_SH_MTACC_T;
8961 INSERT_OPERAND (MTACC_T, *ip, regno);
8499 continue;
8500 }
8501 else
8502 as_bad (_("Invalid dsp/smartmips acc register"));
8503 break;
8504
8505 case '&': /* four dsp accumulators in bits 13,14 */
8506 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8507 s[3] >= '0' && s[3] <= '3')
8508 {
8509 regno = s[3] - '0';
8510 s += 4;
8962 continue;
8963 }
8964 else
8965 as_bad (_("Invalid dsp/smartmips acc register"));
8966 break;
8967
8968 case '&': /* four dsp accumulators in bits 13,14 */
8969 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8970 s[3] >= '0' && s[3] <= '3')
8971 {
8972 regno = s[3] - '0';
8973 s += 4;
8511 ip->insn_opcode |= regno << OP_SH_MTACC_D;
8974 INSERT_OPERAND (MTACC_D, *ip, regno);
8512 continue;
8513 }
8514 else
8515 as_bad (_("Invalid dsp/smartmips acc register"));
8516 break;
8517
8518 case ',':
8975 continue;
8976 }
8977 else
8978 as_bad (_("Invalid dsp/smartmips acc register"));
8979 break;
8980
8981 case ',':
8982 ++argnum;
8519 if (*s++ == *args)
8520 continue;
8521 s--;
8522 switch (*++args)
8523 {
8524 case 'r':
8525 case 'v':
8526 INSERT_OPERAND (RS, *ip, lastregno);

--- 29 unchanged lines hidden (view full) ---

8556 case ']':
8557 if (*s++ == *args)
8558 continue;
8559 break;
8560
8561 case '+': /* Opcode extension character. */
8562 switch (*++args)
8563 {
8983 if (*s++ == *args)
8984 continue;
8985 s--;
8986 switch (*++args)
8987 {
8988 case 'r':
8989 case 'v':
8990 INSERT_OPERAND (RS, *ip, lastregno);

--- 29 unchanged lines hidden (view full) ---

9020 case ']':
9021 if (*s++ == *args)
9022 continue;
9023 break;
9024
9025 case '+': /* Opcode extension character. */
9026 switch (*++args)
9027 {
9028 case '1': /* UDI immediates. */
9029 case '2':
9030 case '3':
9031 case '4':
9032 {
9033 const struct mips_immed *imm = mips_immed;
9034
9035 while (imm->type && imm->type != *args)
9036 ++imm;
9037 if (! imm->type)
9038 internalError ();
9039 my_getExpression (&imm_expr, s);
9040 check_absolute_expr (ip, &imm_expr);
9041 if ((unsigned long) imm_expr.X_add_number & ~imm->mask)
9042 {
9043 as_warn (_("Illegal %s number (%lu, 0x%lx)"),
9044 imm->desc ? imm->desc : ip->insn_mo->name,
9045 (unsigned long) imm_expr.X_add_number,
9046 (unsigned long) imm_expr.X_add_number);
9047 imm_expr.X_add_number &= imm->mask;
9048 }
9049 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
9050 << imm->shift);
9051 imm_expr.X_op = O_absent;
9052 s = expr_end;
9053 }
9054 continue;
9055
8564 case 'A': /* ins/ext position, becomes LSB. */
8565 limlo = 0;
8566 limhi = 31;
8567 goto do_lsb;
8568 case 'E':
8569 limlo = 32;
8570 limhi = 63;
8571 goto do_lsb;

--- 90 unchanged lines hidden (view full) ---

8662 if (imm2_expr.X_op != O_big
8663 && imm2_expr.X_op != O_constant)
8664 insn_error = _("absolute expression required");
8665 if (HAVE_32BIT_GPRS)
8666 normalize_constant_expr (&imm2_expr);
8667 s = expr_end;
8668 continue;
8669
9056 case 'A': /* ins/ext position, becomes LSB. */
9057 limlo = 0;
9058 limhi = 31;
9059 goto do_lsb;
9060 case 'E':
9061 limlo = 32;
9062 limhi = 63;
9063 goto do_lsb;

--- 90 unchanged lines hidden (view full) ---

9154 if (imm2_expr.X_op != O_big
9155 && imm2_expr.X_op != O_constant)
9156 insn_error = _("absolute expression required");
9157 if (HAVE_32BIT_GPRS)
9158 normalize_constant_expr (&imm2_expr);
9159 s = expr_end;
9160 continue;
9161
8670 case 'T': /* Coprocessor register */
9162 case 'T': /* Coprocessor register. */
8671 /* +T is for disassembly only; never match. */
8672 break;
8673
9163 /* +T is for disassembly only; never match. */
9164 break;
9165
8674 case 't': /* Coprocessor register number */
9166 case 't': /* Coprocessor register number. */
8675 if (s[0] == '$' && ISDIGIT (s[1]))
8676 {
8677 ++s;
8678 regno = 0;
8679 do
8680 {
8681 regno *= 10;
8682 regno += *s - '0';
8683 ++s;
8684 }
8685 while (ISDIGIT (*s));
8686 if (regno > 31)
8687 as_bad (_("Invalid register number (%d)"), regno);
8688 else
8689 {
9167 if (s[0] == '$' && ISDIGIT (s[1]))
9168 {
9169 ++s;
9170 regno = 0;
9171 do
9172 {
9173 regno *= 10;
9174 regno += *s - '0';
9175 ++s;
9176 }
9177 while (ISDIGIT (*s));
9178 if (regno > 31)
9179 as_bad (_("Invalid register number (%d)"), regno);
9180 else
9181 {
8690 ip->insn_opcode |= regno << OP_SH_RT;
9182 INSERT_OPERAND (RT, *ip, regno);
8691 continue;
8692 }
8693 }
8694 else
8695 as_bad (_("Invalid coprocessor 0 register number"));
8696 break;
8697
8698 default:

--- 74 unchanged lines hidden (view full) ---

8773 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
8774 imm_expr.X_op = O_absent;
8775 s = expr_end;
8776 continue;
8777
8778 case 'c': /* break code */
8779 my_getExpression (&imm_expr, s);
8780 check_absolute_expr (ip, &imm_expr);
9183 continue;
9184 }
9185 }
9186 else
9187 as_bad (_("Invalid coprocessor 0 register number"));
9188 break;
9189
9190 default:

--- 74 unchanged lines hidden (view full) ---

9265 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
9266 imm_expr.X_op = O_absent;
9267 s = expr_end;
9268 continue;
9269
9270 case 'c': /* break code */
9271 my_getExpression (&imm_expr, s);
9272 check_absolute_expr (ip, &imm_expr);
8781 if ((unsigned long) imm_expr.X_add_number > 1023)
8782 as_warn (_("Illegal break code (%lu)"),
9273 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE)
9274 as_warn (_("Code for %s not in range 0..1023 (%lu)"),
9275 ip->insn_mo->name,
8783 (unsigned long) imm_expr.X_add_number);
8784 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
8785 imm_expr.X_op = O_absent;
8786 s = expr_end;
8787 continue;
8788
8789 case 'q': /* lower break code */
8790 my_getExpression (&imm_expr, s);
8791 check_absolute_expr (ip, &imm_expr);
9276 (unsigned long) imm_expr.X_add_number);
9277 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
9278 imm_expr.X_op = O_absent;
9279 s = expr_end;
9280 continue;
9281
9282 case 'q': /* lower break code */
9283 my_getExpression (&imm_expr, s);
9284 check_absolute_expr (ip, &imm_expr);
8792 if ((unsigned long) imm_expr.X_add_number > 1023)
8793 as_warn (_("Illegal lower break code (%lu)"),
9285 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE2)
9286 as_warn (_("Lower code for %s not in range 0..1023 (%lu)"),
9287 ip->insn_mo->name,
8794 (unsigned long) imm_expr.X_add_number);
8795 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
8796 imm_expr.X_op = O_absent;
8797 s = expr_end;
8798 continue;
8799
8800 case 'y':
8801 /* Decode 10-bits of seqi/snei's signed constant offset. Issue

--- 11 unchanged lines hidden (view full) ---

8813 imm_expr.X_op = O_absent;
8814 s = expr_end;
8815 continue;
8816
8817 case 'B': /* 20-bit syscall/break code. */
8818 my_getExpression (&imm_expr, s);
8819 check_absolute_expr (ip, &imm_expr);
8820 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
9288 (unsigned long) imm_expr.X_add_number);
9289 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
9290 imm_expr.X_op = O_absent;
9291 s = expr_end;
9292 continue;
9293
9294 case 'y':
9295 /* Decode 10-bits of seqi/snei's signed constant offset. Issue

--- 11 unchanged lines hidden (view full) ---

9307 imm_expr.X_op = O_absent;
9308 s = expr_end;
9309 continue;
9310
9311 case 'B': /* 20-bit syscall/break code. */
9312 my_getExpression (&imm_expr, s);
9313 check_absolute_expr (ip, &imm_expr);
9314 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8821 as_warn (_("Illegal 20-bit code (%lu)"),
9315 as_warn (_("Code for %s not in range 0..1048575 (%lu)"),
9316 ip->insn_mo->name,
8822 (unsigned long) imm_expr.X_add_number);
8823 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
8824 imm_expr.X_op = O_absent;
8825 s = expr_end;
8826 continue;
8827
8828 case 'C': /* Coprocessor code */
8829 my_getExpression (&imm_expr, s);
8830 check_absolute_expr (ip, &imm_expr);
9317 (unsigned long) imm_expr.X_add_number);
9318 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
9319 imm_expr.X_op = O_absent;
9320 s = expr_end;
9321 continue;
9322
9323 case 'C': /* Coprocessor code */
9324 my_getExpression (&imm_expr, s);
9325 check_absolute_expr (ip, &imm_expr);
8831 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))
9326 if ((unsigned long) imm_expr.X_add_number > OP_MASK_COPZ)
8832 {
8833 as_warn (_("Coproccesor code > 25 bits (%lu)"),
8834 (unsigned long) imm_expr.X_add_number);
9327 {
9328 as_warn (_("Coproccesor code > 25 bits (%lu)"),
9329 (unsigned long) imm_expr.X_add_number);
8835 imm_expr.X_add_number &= ((1 << 25) - 1);
9330 imm_expr.X_add_number &= OP_MASK_COPZ;
8836 }
9331 }
8837 ip->insn_opcode |= imm_expr.X_add_number;
9332 INSERT_OPERAND (COPZ, *ip, imm_expr.X_add_number);
8838 imm_expr.X_op = O_absent;
8839 s = expr_end;
8840 continue;
8841
8842 case 'J': /* 19-bit wait code. */
8843 my_getExpression (&imm_expr, s);
8844 check_absolute_expr (ip, &imm_expr);
8845 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
9333 imm_expr.X_op = O_absent;
9334 s = expr_end;
9335 continue;
9336
9337 case 'J': /* 19-bit wait code. */
9338 my_getExpression (&imm_expr, s);
9339 check_absolute_expr (ip, &imm_expr);
9340 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8846 as_warn (_("Illegal 19-bit code (%lu)"),
8847 (unsigned long) imm_expr.X_add_number);
9341 {
9342 as_warn (_("Illegal 19-bit code (%lu)"),
9343 (unsigned long) imm_expr.X_add_number);
9344 imm_expr.X_add_number &= OP_MASK_CODE19;
9345 }
8848 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
8849 imm_expr.X_op = O_absent;
8850 s = expr_end;
8851 continue;
8852
9346 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
9347 imm_expr.X_op = O_absent;
9348 s = expr_end;
9349 continue;
9350
8853 case 'P': /* Performance register */
9351 case 'P': /* Performance register. */
8854 my_getExpression (&imm_expr, s);
8855 check_absolute_expr (ip, &imm_expr);
8856 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8857 as_warn (_("Invalid performance register (%lu)"),
8858 (unsigned long) imm_expr.X_add_number);
8859 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
8860 imm_expr.X_op = O_absent;
8861 s = expr_end;
8862 continue;
8863
9352 my_getExpression (&imm_expr, s);
9353 check_absolute_expr (ip, &imm_expr);
9354 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
9355 as_warn (_("Invalid performance register (%lu)"),
9356 (unsigned long) imm_expr.X_add_number);
9357 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
9358 imm_expr.X_op = O_absent;
9359 s = expr_end;
9360 continue;
9361
9362 case 'G': /* Coprocessor destination register. */
9363 if (((ip->insn_opcode >> OP_SH_OP) & OP_MASK_OP) == OP_OP_COP0)
9364 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_CP0, &regno);
9365 else
9366 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9367 INSERT_OPERAND (RD, *ip, regno);
9368 if (ok)
9369 {
9370 lastregno = regno;
9371 continue;
9372 }
9373 else
9374 break;
9375
8864 case 'b': /* base register */
8865 case 'd': /* destination register */
8866 case 's': /* source register */
8867 case 't': /* target register */
8868 case 'r': /* both target and source */
8869 case 'v': /* both dest and source */
8870 case 'w': /* both dest and target */
8871 case 'E': /* coprocessor target register */
9376 case 'b': /* base register */
9377 case 'd': /* destination register */
9378 case 's': /* source register */
9379 case 't': /* target register */
9380 case 'r': /* both target and source */
9381 case 'v': /* both dest and source */
9382 case 'w': /* both dest and target */
9383 case 'E': /* coprocessor target register */
8872 case 'G': /* coprocessor destination register */
8873 case 'K': /* 'rdhwr' destination register */
8874 case 'x': /* ignore register name */
8875 case 'z': /* must be zero register */
8876 case 'U': /* destination register (clo/clz). */
8877 case 'g': /* coprocessor destination register */
9384 case 'K': /* 'rdhwr' destination register */
9385 case 'x': /* ignore register name */
9386 case 'z': /* must be zero register */
9387 case 'U': /* destination register (clo/clz). */
9388 case 'g': /* coprocessor destination register */
8878 s_reset = s;
8879 if (s[0] == '$')
9389 s_reset = s;
9390 if (*args == 'E' || *args == 'K')
9391 ok = reg_lookup (&s, RTYPE_NUM, &regno);
9392 else
8880 {
9393 {
8881 if (ISDIGIT (s[1]))
8882 {
8883 ++s;
8884 regno = 0;
8885 do
8886 {
8887 regno *= 10;
8888 regno += *s - '0';
8889 ++s;
8890 }
8891 while (ISDIGIT (*s));
8892 if (regno > 31)
8893 as_bad (_("Invalid register number (%d)"), regno);
8894 }
8895 else if (*args == 'E' || *args == 'G' || *args == 'K')
8896 goto notreg;
8897 else
8898 {
8899 if (s[1] == 'r' && s[2] == 'a')
8900 {
8901 s += 3;
8902 regno = RA;
8903 }
8904 else if (s[1] == 'f' && s[2] == 'p')
8905 {
8906 s += 3;
8907 regno = FP;
8908 }
8909 else if (s[1] == 's' && s[2] == 'p')
8910 {
8911 s += 3;
8912 regno = SP;
8913 }
8914 else if (s[1] == 'g' && s[2] == 'p')
8915 {
8916 s += 3;
8917 regno = GP;
8918 }
8919 else if (s[1] == 'a' && s[2] == 't')
8920 {
8921 s += 3;
8922 regno = AT;
8923 }
8924 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
8925 {
8926 s += 4;
8927 regno = KT0;
8928 }
8929 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
8930 {
8931 s += 4;
8932 regno = KT1;
8933 }
8934 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
8935 {
8936 s += 5;
8937 regno = ZERO;
8938 }
8939 else if (itbl_have_entries)
8940 {
8941 char *p, *n;
8942 unsigned long r;
8943
8944 p = s + 1; /* advance past '$' */
8945 n = itbl_get_field (&p); /* n is name */
8946
8947 /* See if this is a register defined in an
8948 itbl entry. */
8949 if (itbl_get_reg_val (n, &r))
8950 {
8951 /* Get_field advances to the start of
8952 the next field, so we need to back
8953 rack to the end of the last field. */
8954 if (p)
8955 s = p - 1;
8956 else
8957 s = strchr (s, '\0');
8958 regno = r;
8959 }
8960 else
8961 goto notreg;
8962 }
8963 else
8964 goto notreg;
8965 }
8966 if (regno == AT
8967 && ! mips_opts.noat
8968 && *args != 'E'
8969 && *args != 'G'
8970 && *args != 'K')
8971 as_warn (_("Used $at without \".set noat\""));
9394 ok = reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno);
9395 if (regno == AT && ! mips_opts.noat)
9396 as_warn ("Used $at without \".set noat\"");
9397 }
9398 if (ok)
9399 {
8972 c = *args;
8973 if (*s == ' ')
8974 ++s;
8975 if (args[1] != *s)
8976 {
8977 if (c == 'r' || c == 'v' || c == 'w')
8978 {
8979 regno = lastregno;

--- 49 unchanged lines hidden (view full) ---

9029 /* Itbl operand; not yet implemented. FIXME ?? */
9030 break;
9031 /* What about all other operands like 'i', which
9032 can be specified in the opcode table? */
9033 }
9034 lastregno = regno;
9035 continue;
9036 }
9400 c = *args;
9401 if (*s == ' ')
9402 ++s;
9403 if (args[1] != *s)
9404 {
9405 if (c == 'r' || c == 'v' || c == 'w')
9406 {
9407 regno = lastregno;

--- 49 unchanged lines hidden (view full) ---

9457 /* Itbl operand; not yet implemented. FIXME ?? */
9458 break;
9459 /* What about all other operands like 'i', which
9460 can be specified in the opcode table? */
9461 }
9462 lastregno = regno;
9463 continue;
9464 }
9037 notreg:
9038 switch (*args++)
9039 {
9040 case 'r':
9041 case 'v':
9042 INSERT_OPERAND (RS, *ip, lastregno);
9043 continue;
9044 case 'w':
9045 INSERT_OPERAND (RT, *ip, lastregno);

--- 36 unchanged lines hidden (view full) ---

9082 case 'Z': /* MDMX target register. */
9083 is_mdmx = 1;
9084 case 'D': /* floating point destination register */
9085 case 'S': /* floating point source register */
9086 case 'T': /* floating point target register */
9087 case 'R': /* floating point source register */
9088 case 'V':
9089 case 'W':
9465 switch (*args++)
9466 {
9467 case 'r':
9468 case 'v':
9469 INSERT_OPERAND (RS, *ip, lastregno);
9470 continue;
9471 case 'w':
9472 INSERT_OPERAND (RT, *ip, lastregno);

--- 36 unchanged lines hidden (view full) ---

9509 case 'Z': /* MDMX target register. */
9510 is_mdmx = 1;
9511 case 'D': /* floating point destination register */
9512 case 'S': /* floating point source register */
9513 case 'T': /* floating point target register */
9514 case 'R': /* floating point source register */
9515 case 'V':
9516 case 'W':
9517 rtype = RTYPE_FPU;
9518 if (is_mdmx
9519 || (mips_opts.ase_mdmx
9520 && (ip->insn_mo->pinfo & FP_D)
9521 && (ip->insn_mo->pinfo & (INSN_COPROC_MOVE_DELAY
9522 | INSN_COPROC_MEMORY_DELAY
9523 | INSN_LOAD_COPROC_DELAY
9524 | INSN_LOAD_MEMORY_DELAY
9525 | INSN_STORE_MEMORY))))
9526 rtype |= RTYPE_VEC;
9090 s_reset = s;
9527 s_reset = s;
9091 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
9092 {
9093 insn_error = "opcode not implemented in Octeon";
9094 return;
9095 }
9096 /* Accept $fN for FP and MDMX register numbers, and in
9097 addition accept $vN for MDMX register numbers. */
9098 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
9099 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
9100 && ISDIGIT (s[2])))
9528 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
9101 {
9529 {
9102 s += 2;
9103 regno = 0;
9104 do
9105 {
9106 regno *= 10;
9107 regno += *s - '0';
9108 ++s;
9109 }
9110 while (ISDIGIT (*s));
9111
9112 if (regno > 31)
9113 as_bad (_("Invalid float register number (%d)"), regno);
9114
9530 insn_error = "opcode not implemented in Octeon";
9531 return;
9532 }
9533 if (reg_lookup (&s, rtype, &regno))
9534 {
9115 if ((regno & 1) != 0
9116 && HAVE_32BIT_FPRS
9535 if ((regno & 1) != 0
9536 && HAVE_32BIT_FPRS
9117 && ! (strcmp (str, "mtc1") == 0
9118 || strcmp (str, "mfc1") == 0
9119 || strcmp (str, "lwc1") == 0
9120 || strcmp (str, "swc1") == 0
9121 || strcmp (str, "l.s") == 0
9122 || strcmp (str, "s.s") == 0
9123 || strcmp (str, "mftc1") == 0
9124 || strcmp (str, "mfthc1") == 0
9125 || strcmp (str, "cftc1") == 0
9126 || strcmp (str, "mttc1") == 0
9127 || strcmp (str, "mtthc1") == 0
9128 || strcmp (str, "cttc1") == 0))
9537 && ! mips_oddfpreg_ok (ip->insn_mo, argnum))
9129 as_warn (_("Float register should be even, was %d"),
9130 regno);
9131
9132 c = *args;
9133 if (*s == ' ')
9134 ++s;
9135 if (args[1] != *s)
9136 {

--- 245 unchanged lines hidden (view full) ---

9382 newname = RDATA_SECTION_NAME;
9383 break;
9384 case 'l':
9385 assert (g_switch_value >= 4);
9386 newname = ".lit4";
9387 break;
9388 }
9389 new_seg = subseg_new (newname, (subsegT) 0);
9538 as_warn (_("Float register should be even, was %d"),
9539 regno);
9540
9541 c = *args;
9542 if (*s == ' ')
9543 ++s;
9544 if (args[1] != *s)
9545 {

--- 245 unchanged lines hidden (view full) ---

9791 newname = RDATA_SECTION_NAME;
9792 break;
9793 case 'l':
9794 assert (g_switch_value >= 4);
9795 newname = ".lit4";
9796 break;
9797 }
9798 new_seg = subseg_new (newname, (subsegT) 0);
9390 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9799 if (IS_ELF)
9391 bfd_set_section_flags (stdoutput, new_seg,
9392 (SEC_ALLOC
9393 | SEC_LOAD
9394 | SEC_READONLY
9395 | SEC_DATA));
9396 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9800 bfd_set_section_flags (stdoutput, new_seg,
9801 (SEC_ALLOC
9802 | SEC_LOAD
9803 | SEC_READONLY
9804 | SEC_DATA));
9805 frag_align (*args == 'l' ? 2 : 3, 0, 0);
9397 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
9398 && strcmp (TARGET_OS, "elf") != 0)
9806 if (IS_ELF && strcmp (TARGET_OS, "elf") != 0)
9399 record_alignment (new_seg, 4);
9400 else
9401 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9402 if (seg == now_seg)
9403 as_bad (_("Can't use floating point insn in this section"));
9404
9405 /* Set the argument to the current address in the
9406 section. */

--- 101 unchanged lines hidden (view full) ---

9508 case 'a': /* 26 bit address */
9509 my_getExpression (&offset_expr, s);
9510 s = expr_end;
9511 *offset_reloc = BFD_RELOC_MIPS_JMP;
9512 continue;
9513
9514 case 'N': /* 3 bit branch condition code */
9515 case 'M': /* 3 bit compare condition code */
9807 record_alignment (new_seg, 4);
9808 else
9809 record_alignment (new_seg, *args == 'l' ? 2 : 3);
9810 if (seg == now_seg)
9811 as_bad (_("Can't use floating point insn in this section"));
9812
9813 /* Set the argument to the current address in the
9814 section. */

--- 101 unchanged lines hidden (view full) ---

9916 case 'a': /* 26 bit address */
9917 my_getExpression (&offset_expr, s);
9918 s = expr_end;
9919 *offset_reloc = BFD_RELOC_MIPS_JMP;
9920 continue;
9921
9922 case 'N': /* 3 bit branch condition code */
9923 case 'M': /* 3 bit compare condition code */
9516 if (strncmp (s, "$fcc", 4) != 0)
9924 rtype = RTYPE_CCC;
9925 if (ip->insn_mo->pinfo & (FP_D| FP_S))
9926 rtype |= RTYPE_FCC;
9927 if (!reg_lookup (&s, rtype, &regno))
9517 break;
9928 break;
9518 s += 4;
9519 regno = 0;
9520 do
9521 {
9522 regno *= 10;
9523 regno += *s - '0';
9524 ++s;
9525 }
9526 while (ISDIGIT (*s));
9527 if (regno > 7)
9528 as_bad (_("Invalid condition code register $fcc%d"), regno);
9529 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9530 || strcmp(str + strlen(str) - 5, "any2f") == 0
9531 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9532 && (regno & 1) != 0)
9533 as_warn(_("Condition code register should be even for %s, was %d"),
9534 str, regno);
9535 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9536 || strcmp(str + strlen(str) - 5, "any4t") == 0)

--- 150 unchanged lines hidden (view full) ---

9687 {
9688 insn_error = _("unrecognized opcode");
9689 return;
9690 }
9691
9692 argsstart = s;
9693 for (;;)
9694 {
9929 if ((strcmp(str + strlen(str) - 3, ".ps") == 0
9930 || strcmp(str + strlen(str) - 5, "any2f") == 0
9931 || strcmp(str + strlen(str) - 5, "any2t") == 0)
9932 && (regno & 1) != 0)
9933 as_warn(_("Condition code register should be even for %s, was %d"),
9934 str, regno);
9935 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9936 || strcmp(str + strlen(str) - 5, "any4t") == 0)

--- 150 unchanged lines hidden (view full) ---

10087 {
10088 insn_error = _("unrecognized opcode");
10089 return;
10090 }
10091
10092 argsstart = s;
10093 for (;;)
10094 {
10095 bfd_boolean ok;
10096
9695 assert (strcmp (insn->name, str) == 0);
9696
10097 assert (strcmp (insn->name, str) == 0);
10098
10099 if (OPCODE_IS_MEMBER (insn, mips_opts.isa, mips_opts.arch))
10100 ok = TRUE;
10101 else
10102 ok = FALSE;
10103
10104 if (! ok)
10105 {
10106 if (insn + 1 < &mips16_opcodes[bfd_mips16_num_opcodes]
10107 && strcmp (insn->name, insn[1].name) == 0)
10108 {
10109 ++insn;
10110 continue;
10111 }
10112 else
10113 {
10114 if (!insn_error)
10115 {
10116 static char buf[100];
10117 sprintf (buf,
10118 _("opcode not supported on this processor: %s (%s)"),
10119 mips_cpu_info_from_arch (mips_opts.arch)->name,
10120 mips_cpu_info_from_isa (mips_opts.isa)->name);
10121 insn_error = buf;
10122 }
10123 return;
10124 }
10125 }
10126
9697 create_insn (ip, insn);
9698 imm_expr.X_op = O_absent;
9699 imm_reloc[0] = BFD_RELOC_UNUSED;
9700 imm_reloc[1] = BFD_RELOC_UNUSED;
9701 imm_reloc[2] = BFD_RELOC_UNUSED;
9702 imm2_expr.X_op = O_absent;
9703 offset_expr.X_op = O_absent;
9704 offset_reloc[0] = BFD_RELOC_UNUSED;

--- 16 unchanged lines hidden (view full) ---

9721 case '\0':
9722 if (*s == '\0')
9723 {
9724 /* Stuff the immediate value in now, if we can. */
9725 if (imm_expr.X_op == O_constant
9726 && *imm_reloc > BFD_RELOC_UNUSED
9727 && insn->pinfo != INSN_MACRO)
9728 {
10127 create_insn (ip, insn);
10128 imm_expr.X_op = O_absent;
10129 imm_reloc[0] = BFD_RELOC_UNUSED;
10130 imm_reloc[1] = BFD_RELOC_UNUSED;
10131 imm_reloc[2] = BFD_RELOC_UNUSED;
10132 imm2_expr.X_op = O_absent;
10133 offset_expr.X_op = O_absent;
10134 offset_reloc[0] = BFD_RELOC_UNUSED;

--- 16 unchanged lines hidden (view full) ---

10151 case '\0':
10152 if (*s == '\0')
10153 {
10154 /* Stuff the immediate value in now, if we can. */
10155 if (imm_expr.X_op == O_constant
10156 && *imm_reloc > BFD_RELOC_UNUSED
10157 && insn->pinfo != INSN_MACRO)
10158 {
10159 valueT tmp;
10160
10161 switch (*offset_reloc)
10162 {
10163 case BFD_RELOC_MIPS16_HI16_S:
10164 tmp = (imm_expr.X_add_number + 0x8000) >> 16;
10165 break;
10166
10167 case BFD_RELOC_MIPS16_HI16:
10168 tmp = imm_expr.X_add_number >> 16;
10169 break;
10170
10171 case BFD_RELOC_MIPS16_LO16:
10172 tmp = ((imm_expr.X_add_number + 0x8000) & 0xffff)
10173 - 0x8000;
10174 break;
10175
10176 case BFD_RELOC_UNUSED:
10177 tmp = imm_expr.X_add_number;
10178 break;
10179
10180 default:
10181 internalError ();
10182 }
9729 *offset_reloc = BFD_RELOC_UNUSED;
9730
9731 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
10183 *offset_reloc = BFD_RELOC_UNUSED;
10184
10185 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9732 imm_expr.X_add_number, TRUE, mips16_small,
10186 tmp, TRUE, mips16_small,
9733 mips16_ext, &ip->insn_opcode,
9734 &ip->use_extend, &ip->extend);
9735 imm_expr.X_op = O_absent;
9736 *imm_reloc = BFD_RELOC_UNUSED;
9737 }
9738
9739 return;
9740 }

--- 36 unchanged lines hidden (view full) ---

9777 case 'y':
9778 case 'z':
9779 case 'Z':
9780 case '0':
9781 case 'S':
9782 case 'R':
9783 case 'X':
9784 case 'Y':
10187 mips16_ext, &ip->insn_opcode,
10188 &ip->use_extend, &ip->extend);
10189 imm_expr.X_op = O_absent;
10190 *imm_reloc = BFD_RELOC_UNUSED;
10191 }
10192
10193 return;
10194 }

--- 36 unchanged lines hidden (view full) ---

10231 case 'y':
10232 case 'z':
10233 case 'Z':
10234 case '0':
10235 case 'S':
10236 case 'R':
10237 case 'X':
10238 case 'Y':
9785 if (s[0] != '$')
9786 break;
9787 s_reset = s;
9788 if (ISDIGIT (s[1]))
10239 s_reset = s;
10240 if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &regno))
9789 {
10241 {
9790 ++s;
9791 regno = 0;
9792 do
10242 if (c == 'v' || c == 'w')
9793 {
10243 {
9794 regno *= 10;
9795 regno += *s - '0';
9796 ++s;
10244 if (c == 'v')
10245 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
10246 else
10247 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
10248 ++args;
10249 continue;
9797 }
10250 }
9798 while (ISDIGIT (*s));
9799 if (regno > 31)
9800 {
9801 as_bad (_("invalid register number (%d)"), regno);
9802 regno = 2;
9803 }
10251 break;
9804 }
10252 }
9805 else
9806 {
9807 if (s[1] == 'r' && s[2] == 'a')
9808 {
9809 s += 3;
9810 regno = RA;
9811 }
9812 else if (s[1] == 'f' && s[2] == 'p')
9813 {
9814 s += 3;
9815 regno = FP;
9816 }
9817 else if (s[1] == 's' && s[2] == 'p')
9818 {
9819 s += 3;
9820 regno = SP;
9821 }
9822 else if (s[1] == 'g' && s[2] == 'p')
9823 {
9824 s += 3;
9825 regno = GP;
9826 }
9827 else if (s[1] == 'a' && s[2] == 't')
9828 {
9829 s += 3;
9830 regno = AT;
9831 }
9832 else if (s[1] == 'k' && s[2] == 't' && s[3] == '0')
9833 {
9834 s += 4;
9835 regno = KT0;
9836 }
9837 else if (s[1] == 'k' && s[2] == 't' && s[3] == '1')
9838 {
9839 s += 4;
9840 regno = KT1;
9841 }
9842 else if (s[1] == 'z' && s[2] == 'e' && s[3] == 'r' && s[4] == 'o')
9843 {
9844 s += 5;
9845 regno = ZERO;
9846 }
9847 else
9848 break;
9849 }
9850
9851 if (*s == ' ')
9852 ++s;
9853 if (args[1] != *s)
9854 {
9855 if (c == 'v' || c == 'w')
9856 {
9857 regno = mips16_to_32_reg_map[lastregno];

--- 188 unchanged lines hidden (view full) ---

10046 int mask;
10047
10048 if (c == 'l')
10049 mask = 0;
10050 else
10051 mask = 7 << 3;
10052 while (*s != '\0')
10053 {
10253
10254 if (*s == ' ')
10255 ++s;
10256 if (args[1] != *s)
10257 {
10258 if (c == 'v' || c == 'w')
10259 {
10260 regno = mips16_to_32_reg_map[lastregno];

--- 188 unchanged lines hidden (view full) ---

10449 int mask;
10450
10451 if (c == 'l')
10452 mask = 0;
10453 else
10454 mask = 7 << 3;
10455 while (*s != '\0')
10456 {
10054 int freg, reg1, reg2;
10457 unsigned int freg, reg1, reg2;
10055
10056 while (*s == ' ' || *s == ',')
10057 ++s;
10458
10459 while (*s == ' ' || *s == ',')
10460 ++s;
10058 if (*s != '$')
10461 if (reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10462 freg = 0;
10463 else if (reg_lookup (&s, RTYPE_FPU, &reg1))
10464 freg = 1;
10465 else
10059 {
10060 as_bad (_("can't parse register list"));
10061 break;
10062 }
10466 {
10467 as_bad (_("can't parse register list"));
10468 break;
10469 }
10063 ++s;
10064 if (*s != 'f')
10065 freg = 0;
10066 else
10067 {
10068 freg = 1;
10069 ++s;
10070 }
10071 reg1 = 0;
10072 while (ISDIGIT (*s))
10073 {
10074 reg1 *= 10;
10075 reg1 += *s - '0';
10076 ++s;
10077 }
10078 if (*s == ' ')
10079 ++s;
10080 if (*s != '-')
10081 reg2 = reg1;
10082 else
10083 {
10084 ++s;
10470 if (*s == ' ')
10471 ++s;
10472 if (*s != '-')
10473 reg2 = reg1;
10474 else
10475 {
10476 ++s;
10085 if (*s != '$')
10086 break;
10087 ++s;
10088 if (freg)
10477 if (!reg_lookup (&s, freg ? RTYPE_FPU
10478 : (RTYPE_GP | RTYPE_NUM), &reg2))
10089 {
10479 {
10090 if (*s == 'f')
10091 ++s;
10092 else
10093 {
10094 as_bad (_("invalid register list"));
10095 break;
10096 }
10480 as_bad (_("invalid register list"));
10481 break;
10097 }
10482 }
10098 reg2 = 0;
10099 while (ISDIGIT (*s))
10100 {
10101 reg2 *= 10;
10102 reg2 += *s - '0';
10103 ++s;
10104 }
10105 }
10106 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10107 {
10108 mask &= ~ (7 << 3);
10109 mask |= 5 << 3;
10110 }
10111 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10112 {

--- 47 unchanged lines hidden (view full) ---

10160 }
10161 seen_framesz = 1;
10162 framesz = imm_expr.X_add_number;
10163 imm_expr.X_op = O_absent;
10164 s = expr_end;
10165 continue;
10166 }
10167
10483 }
10484 if (freg && reg1 == 0 && reg2 == 0 && c == 'L')
10485 {
10486 mask &= ~ (7 << 3);
10487 mask |= 5 << 3;
10488 }
10489 else if (freg && reg1 == 0 && reg2 == 1 && c == 'L')
10490 {

--- 47 unchanged lines hidden (view full) ---

10538 }
10539 seen_framesz = 1;
10540 framesz = imm_expr.X_add_number;
10541 imm_expr.X_op = O_absent;
10542 s = expr_end;
10543 continue;
10544 }
10545
10168 if (*s != '$')
10546 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg1))
10169 {
10170 as_bad (_("can't parse register list"));
10171 break;
10172 }
10547 {
10548 as_bad (_("can't parse register list"));
10549 break;
10550 }
10173 ++s;
10174
10551
10175 reg1 = 0;
10176 while (ISDIGIT (*s))
10177 {
10178 reg1 *= 10;
10179 reg1 += *s - '0';
10180 ++s;
10181 }
10182 SKIP_SPACE_TABS (s);
10552 while (*s == ' ')
10553 ++s;
10554
10183 if (*s != '-')
10184 reg2 = reg1;
10185 else
10186 {
10187 ++s;
10555 if (*s != '-')
10556 reg2 = reg1;
10557 else
10558 {
10559 ++s;
10188 if (*s != '$')
10560 if (! reg_lookup (&s, RTYPE_GP | RTYPE_NUM, &reg2)
10561 || reg2 < reg1)
10189 {
10190 as_bad (_("can't parse register list"));
10191 break;
10192 }
10562 {
10563 as_bad (_("can't parse register list"));
10564 break;
10565 }
10193 ++s;
10194 reg2 = 0;
10195 while (ISDIGIT (*s))
10196 {
10197 reg2 *= 10;
10198 reg2 += *s - '0';
10199 ++s;
10200 }
10201 }
10202
10203 while (reg1 <= reg2)
10204 {
10205 if (reg1 >= 4 && reg1 <= 7)
10206 {
10566 }
10567
10568 while (reg1 <= reg2)
10569 {
10570 if (reg1 >= 4 && reg1 <= 7)
10571 {
10207 if (c == 'm' && !seen_framesz)
10572 if (!seen_framesz)
10208 /* args $a0-$a3 */
10209 args |= 1 << (reg1 - 4);
10210 else
10211 /* statics $a0-$a3 */
10212 statics |= 1 << (reg1 - 4);
10213 }
10214 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10215 {

--- 195 unchanged lines hidden (view full) ---

10411 WARN is true, warn if EXT does not match reality. */
10412
10413static void
10414mips16_immed (char *file, unsigned int line, int type, offsetT val,
10415 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10416 unsigned long *insn, bfd_boolean *use_extend,
10417 unsigned short *extend)
10418{
10573 /* args $a0-$a3 */
10574 args |= 1 << (reg1 - 4);
10575 else
10576 /* statics $a0-$a3 */
10577 statics |= 1 << (reg1 - 4);
10578 }
10579 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10580 {

--- 195 unchanged lines hidden (view full) ---

10776 WARN is true, warn if EXT does not match reality. */
10777
10778static void
10779mips16_immed (char *file, unsigned int line, int type, offsetT val,
10780 bfd_boolean warn, bfd_boolean small, bfd_boolean ext,
10781 unsigned long *insn, bfd_boolean *use_extend,
10782 unsigned short *extend)
10783{
10419 register const struct mips16_immed_operand *op;
10784 const struct mips16_immed_operand *op;
10420 int mintiny, maxtiny;
10421 bfd_boolean needext;
10422
10423 op = mips16_immed_operands;
10424 while (op->type != type)
10425 {
10426 ++op;
10427 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);

--- 104 unchanged lines hidden (view full) ---

10532 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10533 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10534 {"%got", BFD_RELOC_MIPS_GOT16},
10535 {"%gp_rel", BFD_RELOC_GPREL16},
10536 {"%half", BFD_RELOC_16},
10537 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10538 {"%higher", BFD_RELOC_MIPS_HIGHER},
10539 {"%neg", BFD_RELOC_MIPS_SUB},
10785 int mintiny, maxtiny;
10786 bfd_boolean needext;
10787
10788 op = mips16_immed_operands;
10789 while (op->type != type)
10790 {
10791 ++op;
10792 assert (op < mips16_immed_operands + MIPS16_NUM_IMMED);

--- 104 unchanged lines hidden (view full) ---

10897 {"%got_hi", BFD_RELOC_MIPS_GOT_HI16},
10898 {"%got_lo", BFD_RELOC_MIPS_GOT_LO16},
10899 {"%got", BFD_RELOC_MIPS_GOT16},
10900 {"%gp_rel", BFD_RELOC_GPREL16},
10901 {"%half", BFD_RELOC_16},
10902 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10903 {"%higher", BFD_RELOC_MIPS_HIGHER},
10904 {"%neg", BFD_RELOC_MIPS_SUB},
10905 {"%tlsgd", BFD_RELOC_MIPS_TLS_GD},
10906 {"%tlsldm", BFD_RELOC_MIPS_TLS_LDM},
10907 {"%dtprel_hi", BFD_RELOC_MIPS_TLS_DTPREL_HI16},
10908 {"%dtprel_lo", BFD_RELOC_MIPS_TLS_DTPREL_LO16},
10909 {"%tprel_hi", BFD_RELOC_MIPS_TLS_TPREL_HI16},
10910 {"%tprel_lo", BFD_RELOC_MIPS_TLS_TPREL_LO16},
10911 {"%gottprel", BFD_RELOC_MIPS_TLS_GOTTPREL},
10540#endif
10541 {"%hi", BFD_RELOC_HI16_S}
10542};
10543
10912#endif
10913 {"%hi", BFD_RELOC_HI16_S}
10914};
10915
10916static const struct percent_op_match mips16_percent_op[] =
10917{
10918 {"%lo", BFD_RELOC_MIPS16_LO16},
10919 {"%gprel", BFD_RELOC_MIPS16_GPREL},
10920 {"%hi", BFD_RELOC_MIPS16_HI16_S}
10921};
10922
10923
10544/* Return true if *STR points to a relocation operator. When returning true,
10545 move *STR over the operator and store its relocation code in *RELOC.
10546 Leave both *STR and *RELOC alone when returning false. */
10547
10548static bfd_boolean
10549parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10550{
10551 const struct percent_op_match *percent_op;
10552 size_t limit, i;
10553
10924/* Return true if *STR points to a relocation operator. When returning true,
10925 move *STR over the operator and store its relocation code in *RELOC.
10926 Leave both *STR and *RELOC alone when returning false. */
10927
10928static bfd_boolean
10929parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10930{
10931 const struct percent_op_match *percent_op;
10932 size_t limit, i;
10933
10554 percent_op = mips_percent_op;
10555 limit = ARRAY_SIZE (mips_percent_op);
10934 if (mips_opts.mips16)
10935 {
10936 percent_op = mips16_percent_op;
10937 limit = ARRAY_SIZE (mips16_percent_op);
10938 }
10939 else
10940 {
10941 percent_op = mips_percent_op;
10942 limit = ARRAY_SIZE (mips_percent_op);
10943 }
10556
10557 for (i = 0; i < limit; i++)
10558 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10559 {
10560 int len = strlen (percent_op[i].str);
10561
10562 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
10563 continue;

--- 234 unchanged lines hidden (view full) ---

10798#define OPTION_DSP (OPTION_ASE_BASE + 6)
10799 {"mdsp", no_argument, NULL, OPTION_DSP},
10800#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10801 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
10802#define OPTION_MT (OPTION_ASE_BASE + 8)
10803 {"mmt", no_argument, NULL, OPTION_MT},
10804#define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10805 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
10944
10945 for (i = 0; i < limit; i++)
10946 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10947 {
10948 int len = strlen (percent_op[i].str);
10949
10950 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
10951 continue;

--- 234 unchanged lines hidden (view full) ---

11186#define OPTION_DSP (OPTION_ASE_BASE + 6)
11187 {"mdsp", no_argument, NULL, OPTION_DSP},
11188#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
11189 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
11190#define OPTION_MT (OPTION_ASE_BASE + 8)
11191 {"mmt", no_argument, NULL, OPTION_MT},
11192#define OPTION_NO_MT (OPTION_ASE_BASE + 9)
11193 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
11194#define OPTION_SMARTMIPS (OPTION_ASE_BASE + 10)
11195 {"msmartmips", no_argument, NULL, OPTION_SMARTMIPS},
11196#define OPTION_NO_SMARTMIPS (OPTION_ASE_BASE + 11)
11197 {"mno-smartmips", no_argument, NULL, OPTION_NO_SMARTMIPS},
11198#define OPTION_DSPR2 (OPTION_ASE_BASE + 12)
11199 {"mdspr2", no_argument, NULL, OPTION_DSPR2},
11200#define OPTION_NO_DSPR2 (OPTION_ASE_BASE + 13)
11201 {"mno-dspr2", no_argument, NULL, OPTION_NO_DSPR2},
10806
10807 /* Old-style architecture options. Don't add more of these. */
11202
11203 /* Old-style architecture options. Don't add more of these. */
10808#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
11204#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 14)
10809#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10810 {"m4650", no_argument, NULL, OPTION_M4650},
10811#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10812 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10813#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10814 {"m4010", no_argument, NULL, OPTION_M4010},
10815#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10816 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},

--- 80 unchanged lines hidden (view full) ---

10897#define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
10898 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
10899#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10900 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10901#define OPTION_PDR (OPTION_ELF_BASE + 9)
10902 {"mpdr", no_argument, NULL, OPTION_PDR},
10903#define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10904 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11205#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
11206 {"m4650", no_argument, NULL, OPTION_M4650},
11207#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
11208 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
11209#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
11210 {"m4010", no_argument, NULL, OPTION_M4010},
11211#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
11212 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},

--- 80 unchanged lines hidden (view full) ---

11293#define OPTION_MDEBUG (OPTION_ELF_BASE + 7)
11294 {"mdebug", no_argument, NULL, OPTION_MDEBUG},
11295#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
11296 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
11297#define OPTION_PDR (OPTION_ELF_BASE + 9)
11298 {"mpdr", no_argument, NULL, OPTION_PDR},
11299#define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
11300 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
11301#define OPTION_MVXWORKS_PIC (OPTION_ELF_BASE + 11)
11302 {"mvxworks-pic", no_argument, NULL, OPTION_MVXWORKS_PIC},
10905#endif /* OBJ_ELF */
10906
10907#define OPTION_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 28)
10908#define OPTION_NO_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 29)
10909 {"mocteon-unsupported", no_argument, NULL, OPTION_MOCTEON_UNSUPPORTED},
10910 {"mno-octeon-unsupported", no_argument, NULL, OPTION_NO_MOCTEON_UNSUPPORTED},
10911
10912#define OPTION_MOCTEON_USEUN (OPTION_MISC_BASE + 30)

--- 63 unchanged lines hidden (view full) ---

10976 octeon_use_unalign = 1;
10977 break;
10978
10979 case OPTION_NO_MOCTEON_USEUN:
10980 octeon_use_unalign = 0;
10981 break;
10982
10983 case 'O':
11303#endif /* OBJ_ELF */
11304
11305#define OPTION_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 28)
11306#define OPTION_NO_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 29)
11307 {"mocteon-unsupported", no_argument, NULL, OPTION_MOCTEON_UNSUPPORTED},
11308 {"mno-octeon-unsupported", no_argument, NULL, OPTION_NO_MOCTEON_UNSUPPORTED},
11309
11310#define OPTION_MOCTEON_USEUN (OPTION_MISC_BASE + 30)

--- 63 unchanged lines hidden (view full) ---

11374 octeon_use_unalign = 1;
11375 break;
11376
11377 case OPTION_NO_MOCTEON_USEUN:
11378 octeon_use_unalign = 0;
11379 break;
11380
11381 case 'O':
10984 if (arg && arg[1] == '0')
11382 if (arg && arg[0] == '0')
10985 mips_optimize = 1;
10986 else
10987 mips_optimize = 2;
10988 break;
10989
10990 case 'g':
10991 if (arg == NULL)
10992 mips_debug = 2;
10993 else
10994 mips_debug = atoi (arg);
11383 mips_optimize = 1;
11384 else
11385 mips_optimize = 2;
11386 break;
11387
11388 case 'g':
11389 if (arg == NULL)
11390 mips_debug = 2;
11391 else
11392 mips_debug = atoi (arg);
10995 /* When the MIPS assembler sees -g or -g2, it does not do
10996 optimizations which limit full symbolic debugging. We take
10997 that to be equivalent to -O0. */
10998 if (mips_debug == 2)
10999 mips_optimize = 1;
11000 break;
11001
11002 case OPTION_MIPS1:
11003 file_mips_isa = ISA_MIPS1;
11004 break;
11005
11006 case OPTION_MIPS2:
11007 file_mips_isa = ISA_MIPS2;

--- 72 unchanged lines hidden (view full) ---

11080 break;
11081
11082 case OPTION_NO_MDMX:
11083 mips_opts.ase_mdmx = 0;
11084 break;
11085
11086 case OPTION_DSP:
11087 mips_opts.ase_dsp = 1;
11393 break;
11394
11395 case OPTION_MIPS1:
11396 file_mips_isa = ISA_MIPS1;
11397 break;
11398
11399 case OPTION_MIPS2:
11400 file_mips_isa = ISA_MIPS2;

--- 72 unchanged lines hidden (view full) ---

11473 break;
11474
11475 case OPTION_NO_MDMX:
11476 mips_opts.ase_mdmx = 0;
11477 break;
11478
11479 case OPTION_DSP:
11480 mips_opts.ase_dsp = 1;
11481 mips_opts.ase_dspr2 = 0;
11088 break;
11089
11090 case OPTION_NO_DSP:
11091 mips_opts.ase_dsp = 0;
11482 break;
11483
11484 case OPTION_NO_DSP:
11485 mips_opts.ase_dsp = 0;
11486 mips_opts.ase_dspr2 = 0;
11092 break;
11093
11487 break;
11488
11489 case OPTION_DSPR2:
11490 mips_opts.ase_dspr2 = 1;
11491 mips_opts.ase_dsp = 1;
11492 break;
11493
11494 case OPTION_NO_DSPR2:
11495 mips_opts.ase_dspr2 = 0;
11496 mips_opts.ase_dsp = 0;
11497 break;
11498
11094 case OPTION_MT:
11095 mips_opts.ase_mt = 1;
11096 break;
11097
11098 case OPTION_NO_MT:
11099 mips_opts.ase_mt = 0;
11100 break;
11101

--- 10 unchanged lines hidden (view full) ---

11112 case OPTION_MIPS3D:
11113 mips_opts.ase_mips3d = 1;
11114 break;
11115
11116 case OPTION_NO_MIPS3D:
11117 mips_opts.ase_mips3d = 0;
11118 break;
11119
11499 case OPTION_MT:
11500 mips_opts.ase_mt = 1;
11501 break;
11502
11503 case OPTION_NO_MT:
11504 mips_opts.ase_mt = 0;
11505 break;
11506

--- 10 unchanged lines hidden (view full) ---

11517 case OPTION_MIPS3D:
11518 mips_opts.ase_mips3d = 1;
11519 break;
11520
11521 case OPTION_NO_MIPS3D:
11522 mips_opts.ase_mips3d = 0;
11523 break;
11524
11525 case OPTION_SMARTMIPS:
11526 mips_opts.ase_smartmips = 1;
11527 break;
11528
11529 case OPTION_NO_SMARTMIPS:
11530 mips_opts.ase_smartmips = 0;
11531 break;
11532
11120 case OPTION_FIX_VR4120:
11121 mips_fix_vr4120 = 1;
11122 break;
11123
11124 case OPTION_NO_FIX_VR4120:
11125 mips_fix_vr4120 = 0;
11126 break;
11127

--- 29 unchanged lines hidden (view full) ---

11157 mips_opts.sym32 = FALSE;
11158 break;
11159
11160#ifdef OBJ_ELF
11161 /* When generating ELF code, we permit -KPIC and -call_shared to
11162 select SVR4_PIC, and -non_shared to select no PIC. This is
11163 intended to be compatible with Irix 5. */
11164 case OPTION_CALL_SHARED:
11533 case OPTION_FIX_VR4120:
11534 mips_fix_vr4120 = 1;
11535 break;
11536
11537 case OPTION_NO_FIX_VR4120:
11538 mips_fix_vr4120 = 0;
11539 break;
11540

--- 29 unchanged lines hidden (view full) ---

11570 mips_opts.sym32 = FALSE;
11571 break;
11572
11573#ifdef OBJ_ELF
11574 /* When generating ELF code, we permit -KPIC and -call_shared to
11575 select SVR4_PIC, and -non_shared to select no PIC. This is
11576 intended to be compatible with Irix 5. */
11577 case OPTION_CALL_SHARED:
11165 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11578 if (!IS_ELF)
11166 {
11167 as_bad (_("-call_shared is supported only for ELF format"));
11168 return 0;
11169 }
11170 mips_pic = SVR4_PIC;
11171 mips_abicalls = TRUE;
11172 break;
11173
11174 case OPTION_NON_SHARED:
11579 {
11580 as_bad (_("-call_shared is supported only for ELF format"));
11581 return 0;
11582 }
11583 mips_pic = SVR4_PIC;
11584 mips_abicalls = TRUE;
11585 break;
11586
11587 case OPTION_NON_SHARED:
11175 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11588 if (!IS_ELF)
11176 {
11177 as_bad (_("-non_shared is supported only for ELF format"));
11178 return 0;
11179 }
11180 mips_pic = NO_PIC;
11181 mips_abicalls = FALSE;
11182 break;
11183

--- 9 unchanged lines hidden (view full) ---

11193 g_switch_value = atoi (arg);
11194 g_switch_seen = 1;
11195 break;
11196
11197#ifdef OBJ_ELF
11198 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11199 and -mabi=64. */
11200 case OPTION_32:
11589 {
11590 as_bad (_("-non_shared is supported only for ELF format"));
11591 return 0;
11592 }
11593 mips_pic = NO_PIC;
11594 mips_abicalls = FALSE;
11595 break;
11596

--- 9 unchanged lines hidden (view full) ---

11606 g_switch_value = atoi (arg);
11607 g_switch_seen = 1;
11608 break;
11609
11610#ifdef OBJ_ELF
11611 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11612 and -mabi=64. */
11613 case OPTION_32:
11201 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11614 if (!IS_ELF)
11202 {
11203 as_bad (_("-32 is supported for ELF format only"));
11204 return 0;
11205 }
11206 mips_abi = O32_ABI;
11207 break;
11208
11209 case OPTION_N32:
11615 {
11616 as_bad (_("-32 is supported for ELF format only"));
11617 return 0;
11618 }
11619 mips_abi = O32_ABI;
11620 break;
11621
11622 case OPTION_N32:
11210 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11623 if (!IS_ELF)
11211 {
11212 as_bad (_("-n32 is supported for ELF format only"));
11213 return 0;
11214 }
11215 mips_abi = N32_ABI;
11216 break;
11217
11218 case OPTION_64:
11624 {
11625 as_bad (_("-n32 is supported for ELF format only"));
11626 return 0;
11627 }
11628 mips_abi = N32_ABI;
11629 break;
11630
11631 case OPTION_64:
11219 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11632 if (!IS_ELF)
11220 {
11221 as_bad (_("-64 is supported for ELF format only"));
11222 return 0;
11223 }
11224 mips_abi = N64_ABI;
11633 {
11634 as_bad (_("-64 is supported for ELF format only"));
11635 return 0;
11636 }
11637 mips_abi = N64_ABI;
11225 if (! support_64bit_objects())
11638 if (!support_64bit_objects())
11226 as_fatal (_("No compiled in support for 64 bit object file format"));
11227 break;
11228#endif /* OBJ_ELF */
11229
11230 case OPTION_GP32:
11231 file_mips_gp32 = 1;
11232 break;
11233

--- 6 unchanged lines hidden (view full) ---

11240 break;
11241
11242 case OPTION_FP64:
11243 file_mips_fp32 = 0;
11244 break;
11245
11246#ifdef OBJ_ELF
11247 case OPTION_MABI:
11639 as_fatal (_("No compiled in support for 64 bit object file format"));
11640 break;
11641#endif /* OBJ_ELF */
11642
11643 case OPTION_GP32:
11644 file_mips_gp32 = 1;
11645 break;
11646

--- 6 unchanged lines hidden (view full) ---

11653 break;
11654
11655 case OPTION_FP64:
11656 file_mips_fp32 = 0;
11657 break;
11658
11659#ifdef OBJ_ELF
11660 case OPTION_MABI:
11248 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11661 if (!IS_ELF)
11249 {
11250 as_bad (_("-mabi is supported for ELF format only"));
11251 return 0;
11252 }
11253 if (strcmp (arg, "32") == 0)
11254 mips_abi = O32_ABI;
11255 else if (strcmp (arg, "o64") == 0)
11256 mips_abi = O64_ABI;

--- 35 unchanged lines hidden (view full) ---

11292
11293 case OPTION_PDR:
11294 mips_flag_pdr = TRUE;
11295 break;
11296
11297 case OPTION_NO_PDR:
11298 mips_flag_pdr = FALSE;
11299 break;
11662 {
11663 as_bad (_("-mabi is supported for ELF format only"));
11664 return 0;
11665 }
11666 if (strcmp (arg, "32") == 0)
11667 mips_abi = O32_ABI;
11668 else if (strcmp (arg, "o64") == 0)
11669 mips_abi = O64_ABI;

--- 35 unchanged lines hidden (view full) ---

11705
11706 case OPTION_PDR:
11707 mips_flag_pdr = TRUE;
11708 break;
11709
11710 case OPTION_NO_PDR:
11711 mips_flag_pdr = FALSE;
11712 break;
11713
11714 case OPTION_MVXWORKS_PIC:
11715 mips_pic = VXWORKS_PIC;
11716 break;
11300#endif /* OBJ_ELF */
11301
11302 default:
11303 return 0;
11304 }
11305
11306 return 1;
11307}

--- 100 unchanged lines hidden (view full) ---

11408 {
11409 /* Infer the integer register size from the ABI and processor.
11410 Restrict ourselves to 32-bit registers if that's all the
11411 processor has, or if the ABI cannot handle 64-bit registers. */
11412 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11413 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11414 }
11415
11717#endif /* OBJ_ELF */
11718
11719 default:
11720 return 0;
11721 }
11722
11723 return 1;
11724}

--- 100 unchanged lines hidden (view full) ---

11825 {
11826 /* Infer the integer register size from the ABI and processor.
11827 Restrict ourselves to 32-bit registers if that's all the
11828 processor has, or if the ABI cannot handle 64-bit registers. */
11829 file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi)
11830 || !ISA_HAS_64BIT_REGS (mips_opts.isa));
11831 }
11832
11416 /* ??? GAS treats single-float processors as though they had 64-bit
11417 float registers (although it complains when double-precision
11418 instructions are used). As things stand, saying they have 32-bit
11419 registers would lead to spurious "register must be even" messages.
11420 So here we assume float registers are always the same size as
11421 integer ones, unless the user says otherwise. */
11422 if (file_mips_fp32 < 0)
11423 file_mips_fp32 = file_mips_gp32;
11833 switch (file_mips_fp32)
11834 {
11835 default:
11836 case -1:
11837 /* No user specified float register size.
11838 ??? GAS treats single-float processors as though they had 64-bit
11839 float registers (although it complains when double-precision
11840 instructions are used). As things stand, saying they have 32-bit
11841 registers would lead to spurious "register must be even" messages.
11842 So here we assume float registers are never smaller than the
11843 integer ones. */
11844 if (file_mips_gp32 == 0)
11845 /* 64-bit integer registers implies 64-bit float registers. */
11846 file_mips_fp32 = 0;
11847 else if ((mips_opts.ase_mips3d > 0 || mips_opts.ase_mdmx > 0)
11848 && ISA_HAS_64BIT_FPRS (mips_opts.isa))
11849 /* -mips3d and -mdmx imply 64-bit float registers, if possible. */
11850 file_mips_fp32 = 0;
11851 else
11852 /* 32-bit float registers. */
11853 file_mips_fp32 = 1;
11854 break;
11424
11855
11856 /* The user specified the size of the float registers. Check if it
11857 agrees with the ABI and ISA. */
11858 case 0:
11859 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
11860 as_bad (_("-mfp64 used with a 32-bit fpu"));
11861 else if (ABI_NEEDS_32BIT_REGS (mips_abi)
11862 && !ISA_HAS_MXHC1 (mips_opts.isa))
11863 as_warn (_("-mfp64 used with a 32-bit ABI"));
11864 break;
11865 case 1:
11866 if (ABI_NEEDS_64BIT_REGS (mips_abi))
11867 as_warn (_("-mfp32 used with a 64-bit ABI"));
11868 break;
11869 }
11870
11425 /* End of GCC-shared inference code. */
11426
11427 /* This flag is set when we have a 64-bit capable CPU but use only
11428 32-bit wide registers. Note that EABI does not use it. */
11429 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11430 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11431 || mips_abi == O32_ABI))
11432 mips_32bitmode = 1;
11433
11434 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11435 as_bad (_("trap exception not supported at ISA 1"));
11436
11437 /* If the selected architecture includes support for ASEs, enable
11438 generation of code for them. */
11439 if (mips_opts.mips16 == -1)
11440 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11441 if (mips_opts.ase_mips3d == -1)
11871 /* End of GCC-shared inference code. */
11872
11873 /* This flag is set when we have a 64-bit capable CPU but use only
11874 32-bit wide registers. Note that EABI does not use it. */
11875 if (ISA_HAS_64BIT_REGS (mips_opts.isa)
11876 && ((mips_abi == NO_ABI && file_mips_gp32 == 1)
11877 || mips_abi == O32_ABI))
11878 mips_32bitmode = 1;
11879
11880 if (mips_opts.isa == ISA_MIPS1 && mips_trap)
11881 as_bad (_("trap exception not supported at ISA 1"));
11882
11883 /* If the selected architecture includes support for ASEs, enable
11884 generation of code for them. */
11885 if (mips_opts.mips16 == -1)
11886 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11887 if (mips_opts.ase_mips3d == -1)
11442 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11888 mips_opts.ase_mips3d = ((arch_info->flags & MIPS_CPU_ASE_MIPS3D)
11889 && file_mips_fp32 == 0) ? 1 : 0;
11890 if (mips_opts.ase_mips3d && file_mips_fp32 == 1)
11891 as_bad (_("-mfp32 used with -mips3d"));
11892
11443 if (mips_opts.ase_mdmx == -1)
11893 if (mips_opts.ase_mdmx == -1)
11444 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11894 mips_opts.ase_mdmx = ((arch_info->flags & MIPS_CPU_ASE_MDMX)
11895 && file_mips_fp32 == 0) ? 1 : 0;
11896 if (mips_opts.ase_mdmx && file_mips_fp32 == 1)
11897 as_bad (_("-mfp32 used with -mdmx"));
11898
11899 if (mips_opts.ase_smartmips == -1)
11900 mips_opts.ase_smartmips = (arch_info->flags & MIPS_CPU_ASE_SMARTMIPS) ? 1 : 0;
11901 if (mips_opts.ase_smartmips && !ISA_SUPPORTS_SMARTMIPS)
11902 as_warn ("%s ISA does not support SmartMIPS",
11903 mips_cpu_info_from_isa (mips_opts.isa)->name);
11904
11445 if (mips_opts.ase_dsp == -1)
11905 if (mips_opts.ase_dsp == -1)
11446 mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
11906 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11907 if (mips_opts.ase_dsp && !ISA_SUPPORTS_DSP_ASE)
11908 as_warn ("%s ISA does not support DSP ASE",
11909 mips_cpu_info_from_isa (mips_opts.isa)->name);
11910
11911 if (mips_opts.ase_dspr2 == -1)
11912 {
11913 mips_opts.ase_dspr2 = (arch_info->flags & MIPS_CPU_ASE_DSPR2) ? 1 : 0;
11914 mips_opts.ase_dsp = (arch_info->flags & MIPS_CPU_ASE_DSP) ? 1 : 0;
11915 }
11916 if (mips_opts.ase_dspr2 && !ISA_SUPPORTS_DSPR2_ASE)
11917 as_warn ("%s ISA does not support DSP R2 ASE",
11918 mips_cpu_info_from_isa (mips_opts.isa)->name);
11919
11447 if (mips_opts.ase_mt == -1)
11920 if (mips_opts.ase_mt == -1)
11448 mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
11921 mips_opts.ase_mt = (arch_info->flags & MIPS_CPU_ASE_MT) ? 1 : 0;
11922 if (mips_opts.ase_mt && !ISA_SUPPORTS_MT_ASE)
11923 as_warn ("%s ISA does not support MT ASE",
11924 mips_cpu_info_from_isa (mips_opts.isa)->name);
11449
11450 file_mips_isa = mips_opts.isa;
11451 file_ase_mips16 = mips_opts.mips16;
11452 file_ase_mips3d = mips_opts.ase_mips3d;
11453 file_ase_mdmx = mips_opts.ase_mdmx;
11925
11926 file_mips_isa = mips_opts.isa;
11927 file_ase_mips16 = mips_opts.mips16;
11928 file_ase_mips3d = mips_opts.ase_mips3d;
11929 file_ase_mdmx = mips_opts.ase_mdmx;
11930 file_ase_smartmips = mips_opts.ase_smartmips;
11454 file_ase_dsp = mips_opts.ase_dsp;
11931 file_ase_dsp = mips_opts.ase_dsp;
11932 file_ase_dspr2 = mips_opts.ase_dspr2;
11455 file_ase_mt = mips_opts.ase_mt;
11456 mips_opts.gp32 = file_mips_gp32;
11457 mips_opts.fp32 = file_mips_fp32;
11458
11459 if (mips_flag_mdebug < 0)
11460 {
11461#ifdef OBJ_MAYBE_ECOFF
11462 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)

--- 18 unchanged lines hidden (view full) ---

11481 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11482 switch (fixP->fx_r_type)
11483 {
11484 case BFD_RELOC_16_PCREL_S2:
11485 case BFD_RELOC_MIPS_JMP:
11486 /* Return the address of the delay slot. */
11487 return addr + 4;
11488 default:
11933 file_ase_mt = mips_opts.ase_mt;
11934 mips_opts.gp32 = file_mips_gp32;
11935 mips_opts.fp32 = file_mips_fp32;
11936
11937 if (mips_flag_mdebug < 0)
11938 {
11939#ifdef OBJ_MAYBE_ECOFF
11940 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)

--- 18 unchanged lines hidden (view full) ---

11959 valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
11960 switch (fixP->fx_r_type)
11961 {
11962 case BFD_RELOC_16_PCREL_S2:
11963 case BFD_RELOC_MIPS_JMP:
11964 /* Return the address of the delay slot. */
11965 return addr + 4;
11966 default:
11967 /* We have no relocation type for PC relative MIPS16 instructions. */
11968 if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
11969 as_bad_where (fixP->fx_file, fixP->fx_line,
11970 _("PC relative MIPS16 instruction references a different section"));
11489 return addr;
11490 }
11491}
11492
11493/* This is called before the symbol table is processed. In order to
11494 work with gcc when using mips-tfile, we must keep all local labels.
11495 However, in other cases, we want to discard them. If we were
11496 called with -g, but we didn't see any debugging information, it may

--- 7 unchanged lines hidden (view full) ---

11504 if (ECOFF_DEBUGGING
11505 && mips_debug != 0
11506 && ! ecoff_debugging_seen)
11507 flag_keep_locals = 1;
11508#endif
11509}
11510
11511/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11971 return addr;
11972 }
11973}
11974
11975/* This is called before the symbol table is processed. In order to
11976 work with gcc when using mips-tfile, we must keep all local labels.
11977 However, in other cases, we want to discard them. If we were
11978 called with -g, but we didn't see any debugging information, it may

--- 7 unchanged lines hidden (view full) ---

11986 if (ECOFF_DEBUGGING
11987 && mips_debug != 0
11988 && ! ecoff_debugging_seen)
11989 flag_keep_locals = 1;
11990#endif
11991}
11992
11993/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11512 the corresponding LO16 reloc. This is called before md_apply_fix3 and
11994 the corresponding LO16 reloc. This is called before md_apply_fix and
11513 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11514 relocation operators.
11515
11516 For our purposes, a %lo() expression matches a %got() or %hi()
11517 expression if:
11518
11519 (a) it refers to the same symbol; and
11520 (b) the offset applied in the %lo() expression is no lower than

--- 68 unchanged lines hidden (view full) ---

11589 hi_pos = NULL;
11590 lo_pos = NULL;
11591 matched_lo_p = FALSE;
11592 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
11593 {
11594 if (*pos == l->fixp)
11595 hi_pos = pos;
11596
11995 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11996 relocation operators.
11997
11998 For our purposes, a %lo() expression matches a %got() or %hi()
11999 expression if:
12000
12001 (a) it refers to the same symbol; and
12002 (b) the offset applied in the %lo() expression is no lower than

--- 68 unchanged lines hidden (view full) ---

12071 hi_pos = NULL;
12072 lo_pos = NULL;
12073 matched_lo_p = FALSE;
12074 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
12075 {
12076 if (*pos == l->fixp)
12077 hi_pos = pos;
12078
11597 if ((*pos)->fx_r_type == BFD_RELOC_LO16
12079 if (((*pos)->fx_r_type == BFD_RELOC_LO16
12080 || (*pos)->fx_r_type == BFD_RELOC_MIPS16_LO16)
11598 && (*pos)->fx_addsy == l->fixp->fx_addsy
11599 && (*pos)->fx_offset >= l->fixp->fx_offset
11600 && (lo_pos == NULL
11601 || (*pos)->fx_offset < (*lo_pos)->fx_offset
11602 || (!matched_lo_p
11603 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
11604 lo_pos = pos;
11605

--- 39 unchanged lines hidden (view full) ---

11645 return 1;
11646
11647 return 0;
11648}
11649
11650/* Apply a fixup to the object file. */
11651
11652void
12081 && (*pos)->fx_addsy == l->fixp->fx_addsy
12082 && (*pos)->fx_offset >= l->fixp->fx_offset
12083 && (lo_pos == NULL
12084 || (*pos)->fx_offset < (*lo_pos)->fx_offset
12085 || (!matched_lo_p
12086 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
12087 lo_pos = pos;
12088

--- 39 unchanged lines hidden (view full) ---

12128 return 1;
12129
12130 return 0;
12131}
12132
12133/* Apply a fixup to the object file. */
12134
12135void
11653md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
12136md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11654{
11655 bfd_byte *buf;
11656 long insn;
11657 reloc_howto_type *howto;
11658
11659 /* We ignore generic BFD relocations we don't know about. */
11660 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11661 if (! howto)
11662 return;
11663
11664 assert (fixP->fx_size == 4
11665 || fixP->fx_r_type == BFD_RELOC_16
11666 || fixP->fx_r_type == BFD_RELOC_64
11667 || fixP->fx_r_type == BFD_RELOC_CTOR
11668 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11669 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
12137{
12138 bfd_byte *buf;
12139 long insn;
12140 reloc_howto_type *howto;
12141
12142 /* We ignore generic BFD relocations we don't know about. */
12143 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
12144 if (! howto)
12145 return;
12146
12147 assert (fixP->fx_size == 4
12148 || fixP->fx_r_type == BFD_RELOC_16
12149 || fixP->fx_r_type == BFD_RELOC_64
12150 || fixP->fx_r_type == BFD_RELOC_CTOR
12151 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
12152 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11670 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
12153 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY
12154 || fixP->fx_r_type == BFD_RELOC_MIPS_TLS_DTPREL64);
11671
11672 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11673
12155
12156 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
12157
11674 assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
12158 assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
11675
11676 /* Don't treat parts of a composite relocation as done. There are two
11677 reasons for this:
11678
11679 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11680 should nevertheless be emitted if the first part is.
11681
11682 (2) In normal usage, composite relocations are never assembly-time
11683 constants. The easiest way of dealing with the pathological
11684 exceptions is to generate a relocation against STN_UNDEF and
11685 leave everything up to the linker. */
12159
12160 /* Don't treat parts of a composite relocation as done. There are two
12161 reasons for this:
12162
12163 (1) The second and third parts will be against 0 (RSS_UNDEF) but
12164 should nevertheless be emitted if the first part is.
12165
12166 (2) In normal usage, composite relocations are never assembly-time
12167 constants. The easiest way of dealing with the pathological
12168 exceptions is to generate a relocation against STN_UNDEF and
12169 leave everything up to the linker. */
11686 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
12170 if (fixP->fx_addsy == NULL && !fixP->fx_pcrel && fixP->fx_tcbit == 0)
11687 fixP->fx_done = 1;
11688
11689 switch (fixP->fx_r_type)
11690 {
12171 fixP->fx_done = 1;
12172
12173 switch (fixP->fx_r_type)
12174 {
12175 case BFD_RELOC_MIPS_TLS_GD:
12176 case BFD_RELOC_MIPS_TLS_LDM:
12177 case BFD_RELOC_MIPS_TLS_DTPREL32:
12178 case BFD_RELOC_MIPS_TLS_DTPREL64:
12179 case BFD_RELOC_MIPS_TLS_DTPREL_HI16:
12180 case BFD_RELOC_MIPS_TLS_DTPREL_LO16:
12181 case BFD_RELOC_MIPS_TLS_GOTTPREL:
12182 case BFD_RELOC_MIPS_TLS_TPREL_HI16:
12183 case BFD_RELOC_MIPS_TLS_TPREL_LO16:
12184 S_SET_THREAD_LOCAL (fixP->fx_addsy);
12185 /* fall through */
12186
11691 case BFD_RELOC_MIPS_JMP:
11692 case BFD_RELOC_MIPS_SHIFT5:
11693 case BFD_RELOC_MIPS_SHIFT6:
11694 case BFD_RELOC_MIPS_GOT_DISP:
11695 case BFD_RELOC_MIPS_GOT_PAGE:
11696 case BFD_RELOC_MIPS_GOT_OFST:
11697 case BFD_RELOC_MIPS_SUB:
11698 case BFD_RELOC_MIPS_INSERT_A:

--- 12 unchanged lines hidden (view full) ---

11711 case BFD_RELOC_MIPS_CALL16:
11712 case BFD_RELOC_MIPS_GOT16:
11713 case BFD_RELOC_GPREL32:
11714 case BFD_RELOC_MIPS_GOT_HI16:
11715 case BFD_RELOC_MIPS_GOT_LO16:
11716 case BFD_RELOC_MIPS_CALL_HI16:
11717 case BFD_RELOC_MIPS_CALL_LO16:
11718 case BFD_RELOC_MIPS16_GPREL:
12187 case BFD_RELOC_MIPS_JMP:
12188 case BFD_RELOC_MIPS_SHIFT5:
12189 case BFD_RELOC_MIPS_SHIFT6:
12190 case BFD_RELOC_MIPS_GOT_DISP:
12191 case BFD_RELOC_MIPS_GOT_PAGE:
12192 case BFD_RELOC_MIPS_GOT_OFST:
12193 case BFD_RELOC_MIPS_SUB:
12194 case BFD_RELOC_MIPS_INSERT_A:

--- 12 unchanged lines hidden (view full) ---

12207 case BFD_RELOC_MIPS_CALL16:
12208 case BFD_RELOC_MIPS_GOT16:
12209 case BFD_RELOC_GPREL32:
12210 case BFD_RELOC_MIPS_GOT_HI16:
12211 case BFD_RELOC_MIPS_GOT_LO16:
12212 case BFD_RELOC_MIPS_CALL_HI16:
12213 case BFD_RELOC_MIPS_CALL_LO16:
12214 case BFD_RELOC_MIPS16_GPREL:
11719 /* Nothing needed to do. The value comes from the reloc entry */
11720 break;
11721
12215 case BFD_RELOC_MIPS16_HI16:
12216 case BFD_RELOC_MIPS16_HI16_S:
11722 case BFD_RELOC_MIPS16_JMP:
12217 case BFD_RELOC_MIPS16_JMP:
11723 /* We currently always generate a reloc against a symbol, which
11724 means that we don't want an addend even if the symbol is
11725 defined. */
11726 *valP = 0;
12218 /* Nothing needed to do. The value comes from the reloc entry. */
11727 break;
11728
11729 case BFD_RELOC_64:
11730 /* This is handled like BFD_RELOC_32, but we output a sign
11731 extended value if we are only 32 bits. */
11732 if (fixP->fx_done)
11733 {
11734 if (8 <= sizeof (valueT))

--- 11 unchanged lines hidden (view full) ---

11746 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
11747 hiv, 4);
11748 }
11749 }
11750 break;
11751
11752 case BFD_RELOC_RVA:
11753 case BFD_RELOC_32:
12219 break;
12220
12221 case BFD_RELOC_64:
12222 /* This is handled like BFD_RELOC_32, but we output a sign
12223 extended value if we are only 32 bits. */
12224 if (fixP->fx_done)
12225 {
12226 if (8 <= sizeof (valueT))

--- 11 unchanged lines hidden (view full) ---

12238 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
12239 hiv, 4);
12240 }
12241 }
12242 break;
12243
12244 case BFD_RELOC_RVA:
12245 case BFD_RELOC_32:
12246 case BFD_RELOC_16:
11754 /* If we are deleting this reloc entry, we must fill in the
11755 value now. This can happen if we have a .word which is not
12247 /* If we are deleting this reloc entry, we must fill in the
12248 value now. This can happen if we have a .word which is not
11756 resolved when it appears but is later defined. */
12249 resolved when it appears but is later defined. */
11757 if (fixP->fx_done)
12250 if (fixP->fx_done)
11758 md_number_to_chars ((char *) buf, *valP, 4);
12251 md_number_to_chars ((char *) buf, *valP, fixP->fx_size);
11759 break;
11760
12252 break;
12253
11761 case BFD_RELOC_16:
11762 /* If we are deleting this reloc entry, we must fill in the
11763 value now. */
11764 if (fixP->fx_done)
11765 md_number_to_chars ((char *) buf, *valP, 2);
11766 break;
11767
11768 case BFD_RELOC_LO16:
12254 case BFD_RELOC_LO16:
12255 case BFD_RELOC_MIPS16_LO16:
11769 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11770 may be safe to remove, but if so it's not obvious. */
11771 /* When handling an embedded PIC switch statement, we can wind
11772 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11773 if (fixP->fx_done)
11774 {
11775 if (*valP + 0x8000 > 0xffff)
11776 as_bad_where (fixP->fx_file, fixP->fx_line,

--- 4 unchanged lines hidden (view full) ---

11781 }
11782 break;
11783
11784 case BFD_RELOC_16_PCREL_S2:
11785 if ((*valP & 0x3) != 0)
11786 as_bad_where (fixP->fx_file, fixP->fx_line,
11787 _("Branch to misaligned address (%lx)"), (long) *valP);
11788
12256 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
12257 may be safe to remove, but if so it's not obvious. */
12258 /* When handling an embedded PIC switch statement, we can wind
12259 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
12260 if (fixP->fx_done)
12261 {
12262 if (*valP + 0x8000 > 0xffff)
12263 as_bad_where (fixP->fx_file, fixP->fx_line,

--- 4 unchanged lines hidden (view full) ---

12268 }
12269 break;
12270
12271 case BFD_RELOC_16_PCREL_S2:
12272 if ((*valP & 0x3) != 0)
12273 as_bad_where (fixP->fx_file, fixP->fx_line,
12274 _("Branch to misaligned address (%lx)"), (long) *valP);
12275
11789 /*
11790 * We need to save the bits in the instruction since fixup_segment()
11791 * might be deleting the relocation entry (i.e., a branch within
11792 * the current segment).
11793 */
12276 /* We need to save the bits in the instruction since fixup_segment()
12277 might be deleting the relocation entry (i.e., a branch within
12278 the current segment). */
11794 if (! fixP->fx_done)
11795 break;
11796
12279 if (! fixP->fx_done)
12280 break;
12281
11797 /* update old instruction data */
12282 /* Update old instruction data. */
11798 if (target_big_endian)
11799 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11800 else
11801 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11802
11803 if (*valP + 0x20000 <= 0x3ffff)
11804 {
11805 insn |= (*valP >> 2) & 0xffff;
11806 md_number_to_chars ((char *) buf, insn, 4);
11807 }
11808 else if (mips_pic == NO_PIC
11809 && fixP->fx_done
11810 && fixP->fx_frag->fr_address >= text_section->vma
11811 && (fixP->fx_frag->fr_address
12283 if (target_big_endian)
12284 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
12285 else
12286 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
12287
12288 if (*valP + 0x20000 <= 0x3ffff)
12289 {
12290 insn |= (*valP >> 2) & 0xffff;
12291 md_number_to_chars ((char *) buf, insn, 4);
12292 }
12293 else if (mips_pic == NO_PIC
12294 && fixP->fx_done
12295 && fixP->fx_frag->fr_address >= text_section->vma
12296 && (fixP->fx_frag->fr_address
11812 < text_section->vma + text_section->_raw_size)
12297 < text_section->vma + bfd_get_section_size (text_section))
11813 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11814 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
11815 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
11816 {
11817 /* The branch offset is too large. If this is an
11818 unconditional branch, and we are not generating PIC code,
11819 we can convert it to an absolute jump instruction. */
11820 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */

--- 68 unchanged lines hidden (view full) ---

11889}
11890
11891/* Align to a given power of two. .align 0 turns off the automatic
11892 alignment used by the data creating pseudo-ops. */
11893
11894static void
11895s_align (int x ATTRIBUTE_UNUSED)
11896{
12298 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
12299 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */
12300 || (insn & 0xffff0000) == 0x04110000)) /* bgezal $0 */
12301 {
12302 /* The branch offset is too large. If this is an
12303 unconditional branch, and we are not generating PIC code,
12304 we can convert it to an absolute jump instruction. */
12305 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */

--- 68 unchanged lines hidden (view full) ---

12374}
12375
12376/* Align to a given power of two. .align 0 turns off the automatic
12377 alignment used by the data creating pseudo-ops. */
12378
12379static void
12380s_align (int x ATTRIBUTE_UNUSED)
12381{
11897 register int temp;
11898 register long temp_fill;
12382 int temp;
12383 long temp_fill;
11899 long max_alignment = 15;
11900
12384 long max_alignment = 15;
12385
11901 /*
11902
11903 o Note that the assembler pulls down any immediately preceding label
12386 /* o Note that the assembler pulls down any immediately preceding label
11904 to the aligned address.
12387 to the aligned address.
11905 o It's not documented but auto alignment is reinstated by
12388 o It's not documented but auto alignment is reinstated by
11906 a .align pseudo instruction.
12389 a .align pseudo instruction.
11907 o Note also that after auto alignment is turned off the mips assembler
12390 o Note also that after auto alignment is turned off the mips assembler
11908 issues an error on attempt to assemble an improperly aligned data item.
12391 issues an error on attempt to assemble an improperly aligned data item.
11909 We don't.
12392 We don't. */
11910
12393
11911 */
11912
11913 temp = get_absolute_expression ();
11914 if (temp > max_alignment)
11915 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
11916 else if (temp < 0)
11917 {
11918 as_warn (_("Alignment negative: 0 assumed."));
11919 temp = 0;
11920 }
11921 if (*input_line_pointer == ',')
11922 {
11923 ++input_line_pointer;
11924 temp_fill = get_absolute_expression ();
11925 }
11926 else
11927 temp_fill = 0;
11928 if (temp)
11929 {
12394 temp = get_absolute_expression ();
12395 if (temp > max_alignment)
12396 as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
12397 else if (temp < 0)
12398 {
12399 as_warn (_("Alignment negative: 0 assumed."));
12400 temp = 0;
12401 }
12402 if (*input_line_pointer == ',')
12403 {
12404 ++input_line_pointer;
12405 temp_fill = get_absolute_expression ();
12406 }
12407 else
12408 temp_fill = 0;
12409 if (temp)
12410 {
12411 segment_info_type *si = seg_info (now_seg);
12412 struct insn_label_list *l = si->label_list;
12413 /* Auto alignment should be switched on by next section change. */
11930 auto_align = 1;
12414 auto_align = 1;
11931 mips_align (temp, (int) temp_fill,
11932 insn_labels != NULL ? insn_labels->label : NULL);
12415 mips_align (temp, (int) temp_fill, l != NULL ? l->label : NULL);
11933 }
11934 else
11935 {
11936 auto_align = 0;
11937 }
11938
11939 demand_empty_rest_of_line ();
11940}

--- 5 unchanged lines hidden (view full) ---

11946
11947#ifdef OBJ_ELF
11948 /* The ELF backend needs to know that we are changing sections, so
11949 that .previous works correctly. We could do something like check
11950 for an obj_section_change_hook macro, but that might be confusing
11951 as it would not be appropriate to use it in the section changing
11952 functions in read.c, since obj-elf.c intercepts those. FIXME:
11953 This should be cleaner, somehow. */
12416 }
12417 else
12418 {
12419 auto_align = 0;
12420 }
12421
12422 demand_empty_rest_of_line ();
12423}

--- 5 unchanged lines hidden (view full) ---

12429
12430#ifdef OBJ_ELF
12431 /* The ELF backend needs to know that we are changing sections, so
12432 that .previous works correctly. We could do something like check
12433 for an obj_section_change_hook macro, but that might be confusing
12434 as it would not be appropriate to use it in the section changing
12435 functions in read.c, since obj-elf.c intercepts those. FIXME:
12436 This should be cleaner, somehow. */
11954 obj_elf_section_change_hook ();
12437 if (IS_ELF)
12438 obj_elf_section_change_hook ();
11955#endif
11956
11957 mips_emit_delays ();
11958 switch (sec)
11959 {
11960 case 't':
11961 s_text (0);
11962 break;
11963 case 'd':
11964 s_data (0);
11965 break;
11966 case 'b':
11967 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11968 demand_empty_rest_of_line ();
11969 break;
11970
11971 case 'r':
11972 seg = subseg_new (RDATA_SECTION_NAME,
11973 (subsegT) get_absolute_expression ());
12439#endif
12440
12441 mips_emit_delays ();
12442 switch (sec)
12443 {
12444 case 't':
12445 s_text (0);
12446 break;
12447 case 'd':
12448 s_data (0);
12449 break;
12450 case 'b':
12451 subseg_set (bss_section, (subsegT) get_absolute_expression ());
12452 demand_empty_rest_of_line ();
12453 break;
12454
12455 case 'r':
12456 seg = subseg_new (RDATA_SECTION_NAME,
12457 (subsegT) get_absolute_expression ());
11974 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12458 if (IS_ELF)
11975 {
11976 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11977 | SEC_READONLY | SEC_RELOC
11978 | SEC_DATA));
11979 if (strcmp (TARGET_OS, "elf") != 0)
11980 record_alignment (seg, 4);
11981 }
11982 demand_empty_rest_of_line ();
11983 break;
11984
11985 case 's':
11986 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
12459 {
12460 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
12461 | SEC_READONLY | SEC_RELOC
12462 | SEC_DATA));
12463 if (strcmp (TARGET_OS, "elf") != 0)
12464 record_alignment (seg, 4);
12465 }
12466 demand_empty_rest_of_line ();
12467 break;
12468
12469 case 's':
12470 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11987 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
12471 if (IS_ELF)
11988 {
11989 bfd_set_section_flags (stdoutput, seg,
11990 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11991 if (strcmp (TARGET_OS, "elf") != 0)
11992 record_alignment (seg, 4);
11993 }
11994 demand_empty_rest_of_line ();
11995 break;

--- 9 unchanged lines hidden (view full) ---

12005 char *section_name;
12006 char c;
12007 char next_c = 0;
12008 int section_type;
12009 int section_flag;
12010 int section_entry_size;
12011 int section_alignment;
12012
12472 {
12473 bfd_set_section_flags (stdoutput, seg,
12474 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
12475 if (strcmp (TARGET_OS, "elf") != 0)
12476 record_alignment (seg, 4);
12477 }
12478 demand_empty_rest_of_line ();
12479 break;

--- 9 unchanged lines hidden (view full) ---

12489 char *section_name;
12490 char c;
12491 char next_c = 0;
12492 int section_type;
12493 int section_flag;
12494 int section_entry_size;
12495 int section_alignment;
12496
12013 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
12497 if (!IS_ELF)
12014 return;
12015
12016 section_name = input_line_pointer;
12017 c = get_symbol_end ();
12018 if (c)
12019 next_c = *(input_line_pointer + 1);
12020
12021 /* Do we have .section Name<,"flags">? */

--- 28 unchanged lines hidden (view full) ---

12050 section_name = xstrdup (section_name);
12051
12052 /* When using the generic form of .section (as implemented by obj-elf.c),
12053 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12054 traditionally had to fall back on the more common @progbits instead.
12055
12056 There's nothing really harmful in this, since bfd will correct
12057 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12498 return;
12499
12500 section_name = input_line_pointer;
12501 c = get_symbol_end ();
12502 if (c)
12503 next_c = *(input_line_pointer + 1);
12504
12505 /* Do we have .section Name<,"flags">? */

--- 28 unchanged lines hidden (view full) ---

12534 section_name = xstrdup (section_name);
12535
12536 /* When using the generic form of .section (as implemented by obj-elf.c),
12537 there's no way to set the section type to SHT_MIPS_DWARF. Users have
12538 traditionally had to fall back on the more common @progbits instead.
12539
12540 There's nothing really harmful in this, since bfd will correct
12541 SHT_PROGBITS to SHT_MIPS_DWARF before writing out the file. But it
12058 means that, for backwards compatibiltiy, the special_section entries
12542 means that, for backwards compatibility, the special_section entries
12059 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12060
12061 Even so, we shouldn't force users of the MIPS .section syntax to
12062 incorrectly label the sections as SHT_PROGBITS. The best compromise
12063 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12064 generic type-checking code. */
12065 if (section_type == SHT_MIPS_DWARF)
12066 section_type = SHT_PROGBITS;

--- 10 unchanged lines hidden (view full) ---

12077mips_enable_auto_align (void)
12078{
12079 auto_align = 1;
12080}
12081
12082static void
12083s_cons (int log_size)
12084{
12543 for dwarf sections must use SHT_PROGBITS rather than SHT_MIPS_DWARF.
12544
12545 Even so, we shouldn't force users of the MIPS .section syntax to
12546 incorrectly label the sections as SHT_PROGBITS. The best compromise
12547 seems to be to map SHT_MIPS_DWARF to SHT_PROGBITS before calling the
12548 generic type-checking code. */
12549 if (section_type == SHT_MIPS_DWARF)
12550 section_type = SHT_PROGBITS;

--- 10 unchanged lines hidden (view full) ---

12561mips_enable_auto_align (void)
12562{
12563 auto_align = 1;
12564}
12565
12566static void
12567s_cons (int log_size)
12568{
12569 segment_info_type *si = seg_info (now_seg);
12570 struct insn_label_list *l = si->label_list;
12085 symbolS *label;
12086
12571 symbolS *label;
12572
12087 label = insn_labels != NULL ? insn_labels->label : NULL;
12573 label = l != NULL ? l->label : NULL;
12088 mips_emit_delays ();
12089 if (log_size > 0 && auto_align)
12090 mips_align (log_size, 0, label);
12091 mips_clear_insn_labels ();
12092 cons (1 << log_size);
12093}
12094
12095static void
12096s_float_cons (int type)
12097{
12574 mips_emit_delays ();
12575 if (log_size > 0 && auto_align)
12576 mips_align (log_size, 0, label);
12577 mips_clear_insn_labels ();
12578 cons (1 << log_size);
12579}
12580
12581static void
12582s_float_cons (int type)
12583{
12584 segment_info_type *si = seg_info (now_seg);
12585 struct insn_label_list *l = si->label_list;
12098 symbolS *label;
12099
12586 symbolS *label;
12587
12100 label = insn_labels != NULL ? insn_labels->label : NULL;
12588 label = l != NULL ? l->label : NULL;
12101
12102 mips_emit_delays ();
12103
12104 if (auto_align)
12105 {
12106 if (type == 'd')
12107 mips_align (3, 0, label);
12108 else

--- 170 unchanged lines hidden (view full) ---

12279 else if (strcmp (name, "bopt") == 0)
12280 {
12281 mips_opts.nobopt = 0;
12282 }
12283 else if (strcmp (name, "nobopt") == 0)
12284 {
12285 mips_opts.nobopt = 1;
12286 }
12589
12590 mips_emit_delays ();
12591
12592 if (auto_align)
12593 {
12594 if (type == 'd')
12595 mips_align (3, 0, label);
12596 else

--- 170 unchanged lines hidden (view full) ---

12767 else if (strcmp (name, "bopt") == 0)
12768 {
12769 mips_opts.nobopt = 0;
12770 }
12771 else if (strcmp (name, "nobopt") == 0)
12772 {
12773 mips_opts.nobopt = 1;
12774 }
12775 else if (strcmp (name, "gp=default") == 0)
12776 mips_opts.gp32 = file_mips_gp32;
12777 else if (strcmp (name, "gp=32") == 0)
12778 mips_opts.gp32 = 1;
12779 else if (strcmp (name, "gp=64") == 0)
12780 {
12781 if (!ISA_HAS_64BIT_REGS (mips_opts.isa))
12782 as_warn ("%s isa does not support 64-bit registers",
12783 mips_cpu_info_from_isa (mips_opts.isa)->name);
12784 mips_opts.gp32 = 0;
12785 }
12786 else if (strcmp (name, "fp=default") == 0)
12787 mips_opts.fp32 = file_mips_fp32;
12788 else if (strcmp (name, "fp=32") == 0)
12789 mips_opts.fp32 = 1;
12790 else if (strcmp (name, "fp=64") == 0)
12791 {
12792 if (!ISA_HAS_64BIT_FPRS (mips_opts.isa))
12793 as_warn ("%s isa does not support 64-bit floating point registers",
12794 mips_cpu_info_from_isa (mips_opts.isa)->name);
12795 mips_opts.fp32 = 0;
12796 }
12287 else if (strcmp (name, "mips16") == 0
12288 || strcmp (name, "MIPS-16") == 0)
12289 mips_opts.mips16 = 1;
12290 else if (strcmp (name, "nomips16") == 0
12291 || strcmp (name, "noMIPS-16") == 0)
12292 mips_opts.mips16 = 0;
12797 else if (strcmp (name, "mips16") == 0
12798 || strcmp (name, "MIPS-16") == 0)
12799 mips_opts.mips16 = 1;
12800 else if (strcmp (name, "nomips16") == 0
12801 || strcmp (name, "noMIPS-16") == 0)
12802 mips_opts.mips16 = 0;
12803 else if (strcmp (name, "smartmips") == 0)
12804 {
12805 if (!ISA_SUPPORTS_SMARTMIPS)
12806 as_warn ("%s ISA does not support SmartMIPS ASE",
12807 mips_cpu_info_from_isa (mips_opts.isa)->name);
12808 mips_opts.ase_smartmips = 1;
12809 }
12810 else if (strcmp (name, "nosmartmips") == 0)
12811 mips_opts.ase_smartmips = 0;
12293 else if (strcmp (name, "mips3d") == 0)
12294 mips_opts.ase_mips3d = 1;
12295 else if (strcmp (name, "nomips3d") == 0)
12296 mips_opts.ase_mips3d = 0;
12297 else if (strcmp (name, "mdmx") == 0)
12298 mips_opts.ase_mdmx = 1;
12299 else if (strcmp (name, "nomdmx") == 0)
12300 mips_opts.ase_mdmx = 0;
12301 else if (strcmp (name, "dsp") == 0)
12812 else if (strcmp (name, "mips3d") == 0)
12813 mips_opts.ase_mips3d = 1;
12814 else if (strcmp (name, "nomips3d") == 0)
12815 mips_opts.ase_mips3d = 0;
12816 else if (strcmp (name, "mdmx") == 0)
12817 mips_opts.ase_mdmx = 1;
12818 else if (strcmp (name, "nomdmx") == 0)
12819 mips_opts.ase_mdmx = 0;
12820 else if (strcmp (name, "dsp") == 0)
12302 mips_opts.ase_dsp = 1;
12821 {
12822 if (!ISA_SUPPORTS_DSP_ASE)
12823 as_warn ("%s ISA does not support DSP ASE",
12824 mips_cpu_info_from_isa (mips_opts.isa)->name);
12825 mips_opts.ase_dsp = 1;
12826 mips_opts.ase_dspr2 = 0;
12827 }
12303 else if (strcmp (name, "nodsp") == 0)
12828 else if (strcmp (name, "nodsp") == 0)
12304 mips_opts.ase_dsp = 0;
12829 {
12830 mips_opts.ase_dsp = 0;
12831 mips_opts.ase_dspr2 = 0;
12832 }
12833 else if (strcmp (name, "dspr2") == 0)
12834 {
12835 if (!ISA_SUPPORTS_DSPR2_ASE)
12836 as_warn ("%s ISA does not support DSP R2 ASE",
12837 mips_cpu_info_from_isa (mips_opts.isa)->name);
12838 mips_opts.ase_dspr2 = 1;
12839 mips_opts.ase_dsp = 1;
12840 }
12841 else if (strcmp (name, "nodspr2") == 0)
12842 {
12843 mips_opts.ase_dspr2 = 0;
12844 mips_opts.ase_dsp = 0;
12845 }
12305 else if (strcmp (name, "mt") == 0)
12846 else if (strcmp (name, "mt") == 0)
12306 mips_opts.ase_mt = 1;
12847 {
12848 if (!ISA_SUPPORTS_MT_ASE)
12849 as_warn ("%s ISA does not support MT ASE",
12850 mips_cpu_info_from_isa (mips_opts.isa)->name);
12851 mips_opts.ase_mt = 1;
12852 }
12307 else if (strcmp (name, "nomt") == 0)
12308 mips_opts.ase_mt = 0;
12309 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12310 {
12311 int reset = 0;
12312
12313 /* Permit the user to change the ISA and architecture on the fly.
12314 Needless to say, misuse can cause serious problems. */

--- 94 unchanged lines hidden (view full) ---

12409 mips_opts_stack = s->next;
12410 free (s);
12411 }
12412 }
12413 else if (strcmp (name, "sym32") == 0)
12414 mips_opts.sym32 = TRUE;
12415 else if (strcmp (name, "nosym32") == 0)
12416 mips_opts.sym32 = FALSE;
12853 else if (strcmp (name, "nomt") == 0)
12854 mips_opts.ase_mt = 0;
12855 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12856 {
12857 int reset = 0;
12858
12859 /* Permit the user to change the ISA and architecture on the fly.
12860 Needless to say, misuse can cause serious problems. */

--- 94 unchanged lines hidden (view full) ---

12955 mips_opts_stack = s->next;
12956 free (s);
12957 }
12958 }
12959 else if (strcmp (name, "sym32") == 0)
12960 mips_opts.sym32 = TRUE;
12961 else if (strcmp (name, "nosym32") == 0)
12962 mips_opts.sym32 = FALSE;
12963 else if (strchr (name, ','))
12964 {
12965 /* Generic ".set" directive; use the generic handler. */
12966 *input_line_pointer = ch;
12967 input_line_pointer = name;
12968 s_set (0);
12969 return;
12970 }
12417 else
12418 {
12419 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12420 }
12421 *input_line_pointer = ch;
12422 demand_empty_rest_of_line ();
12423}
12424

--- 91 unchanged lines hidden (view full) ---

12516 daddu $reg2, $gp, $0
12517 lui $gp, %hi(%neg(%gp_rel(label)))
12518 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12519 daddu $gp, $gp, $reg1
12520 $reg1 is normally $25 == $t9.
12521
12522 The -mno-shared option replaces the last three instructions with
12523 lui $gp,%hi(_gp)
12971 else
12972 {
12973 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12974 }
12975 *input_line_pointer = ch;
12976 demand_empty_rest_of_line ();
12977}
12978

--- 91 unchanged lines hidden (view full) ---

13070 daddu $reg2, $gp, $0
13071 lui $gp, %hi(%neg(%gp_rel(label)))
13072 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
13073 daddu $gp, $gp, $reg1
13074 $reg1 is normally $25 == $t9.
13075
13076 The -mno-shared option replaces the last three instructions with
13077 lui $gp,%hi(_gp)
12524 addiu $gp,$gp,%lo(_gp)
12525 */
13078 addiu $gp,$gp,%lo(_gp) */
12526
12527static void
12528s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12529{
12530 expressionS ex_off;
12531 expressionS ex_sym;
12532 int reg1;
12533

--- 85 unchanged lines hidden (view full) ---

12619
12620 demand_empty_rest_of_line ();
12621}
12622
12623static void
12624s_cplocal (int ignore ATTRIBUTE_UNUSED)
12625{
12626 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
13079
13080static void
13081s_cpsetup (int ignore ATTRIBUTE_UNUSED)
13082{
13083 expressionS ex_off;
13084 expressionS ex_sym;
13085 int reg1;
13086

--- 85 unchanged lines hidden (view full) ---

13172
13173 demand_empty_rest_of_line ();
13174}
13175
13176static void
13177s_cplocal (int ignore ATTRIBUTE_UNUSED)
13178{
13179 /* If we are not generating SVR4 PIC code, or if this is not NewABI code,
12627 .cplocal is ignored. */
13180 .cplocal is ignored. */
12628 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12629 {
12630 s_ignore (0);
12631 return;
12632 }
12633
12634 mips_gp_register = tc_get_register (0);
12635 demand_empty_rest_of_line ();

--- 32 unchanged lines hidden (view full) ---

12668 demand_empty_rest_of_line ();
12669}
12670
12671/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
12672 was given in the preceding .cpsetup, it results in:
12673 ld $gp, offset($sp)
12674
12675 If a register $reg2 was given there, it results in:
13181 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
13182 {
13183 s_ignore (0);
13184 return;
13185 }
13186
13187 mips_gp_register = tc_get_register (0);
13188 demand_empty_rest_of_line ();

--- 32 unchanged lines hidden (view full) ---

13221 demand_empty_rest_of_line ();
13222}
13223
13224/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
13225 was given in the preceding .cpsetup, it results in:
13226 ld $gp, offset($sp)
13227
13228 If a register $reg2 was given there, it results in:
12676 daddu $gp, $reg2, $0
12677 */
13229 daddu $gp, $reg2, $0 */
13230
12678static void
12679s_cpreturn (int ignore ATTRIBUTE_UNUSED)
12680{
12681 expressionS ex;
12682
12683 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
12684 We also need NewABI support. */
12685 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)

--- 15 unchanged lines hidden (view full) ---

12701 else
12702 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
12703 mips_cpreturn_register, 0);
12704 macro_end ();
12705
12706 demand_empty_rest_of_line ();
12707}
12708
13231static void
13232s_cpreturn (int ignore ATTRIBUTE_UNUSED)
13233{
13234 expressionS ex;
13235
13236 /* If we are not generating SVR4 PIC code, .cpreturn is ignored.
13237 We also need NewABI support. */
13238 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)

--- 15 unchanged lines hidden (view full) ---

13254 else
13255 macro_build (NULL, "daddu", "d,v,t", mips_gp_register,
13256 mips_cpreturn_register, 0);
13257 macro_end ();
13258
13259 demand_empty_rest_of_line ();
13260}
13261
13262/* Handle the .dtprelword and .dtpreldword pseudo-ops. They generate
13263 a 32-bit or 64-bit DTP-relative relocation (BYTES says which) for
13264 use in DWARF debug information. */
13265
13266static void
13267s_dtprel_internal (size_t bytes)
13268{
13269 expressionS ex;
13270 char *p;
13271
13272 expression (&ex);
13273
13274 if (ex.X_op != O_symbol)
13275 {
13276 as_bad (_("Unsupported use of %s"), (bytes == 8
13277 ? ".dtpreldword"
13278 : ".dtprelword"));
13279 ignore_rest_of_line ();
13280 }
13281
13282 p = frag_more (bytes);
13283 md_number_to_chars (p, 0, bytes);
13284 fix_new_exp (frag_now, p - frag_now->fr_literal, bytes, &ex, FALSE,
13285 (bytes == 8
13286 ? BFD_RELOC_MIPS_TLS_DTPREL64
13287 : BFD_RELOC_MIPS_TLS_DTPREL32));
13288
13289 demand_empty_rest_of_line ();
13290}
13291
13292/* Handle .dtprelword. */
13293
13294static void
13295s_dtprelword (int ignore ATTRIBUTE_UNUSED)
13296{
13297 s_dtprel_internal (4);
13298}
13299
13300/* Handle .dtpreldword. */
13301
13302static void
13303s_dtpreldword (int ignore ATTRIBUTE_UNUSED)
13304{
13305 s_dtprel_internal (8);
13306}
13307
12709/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
12710 code. It sets the offset to use in gp_rel relocations. */
12711
12712static void
12713s_gpvalue (int ignore ATTRIBUTE_UNUSED)
12714{
12715 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
12716 We also need NewABI support. */

--- 9 unchanged lines hidden (view full) ---

12726}
12727
12728/* Handle the .gpword pseudo-op. This is used when generating PIC
12729 code. It generates a 32 bit GP relative reloc. */
12730
12731static void
12732s_gpword (int ignore ATTRIBUTE_UNUSED)
12733{
13308/* Handle the .gpvalue pseudo-op. This is used when generating NewABI PIC
13309 code. It sets the offset to use in gp_rel relocations. */
13310
13311static void
13312s_gpvalue (int ignore ATTRIBUTE_UNUSED)
13313{
13314 /* If we are not generating SVR4 PIC code, .gpvalue is ignored.
13315 We also need NewABI support. */

--- 9 unchanged lines hidden (view full) ---

13325}
13326
13327/* Handle the .gpword pseudo-op. This is used when generating PIC
13328 code. It generates a 32 bit GP relative reloc. */
13329
13330static void
13331s_gpword (int ignore ATTRIBUTE_UNUSED)
13332{
13333 segment_info_type *si;
13334 struct insn_label_list *l;
12734 symbolS *label;
12735 expressionS ex;
12736 char *p;
12737
12738 /* When not generating PIC code, this is treated as .word. */
12739 if (mips_pic != SVR4_PIC)
12740 {
12741 s_cons (2);
12742 return;
12743 }
12744
13335 symbolS *label;
13336 expressionS ex;
13337 char *p;
13338
13339 /* When not generating PIC code, this is treated as .word. */
13340 if (mips_pic != SVR4_PIC)
13341 {
13342 s_cons (2);
13343 return;
13344 }
13345
12745 label = insn_labels != NULL ? insn_labels->label : NULL;
13346 si = seg_info (now_seg);
13347 l = si->label_list;
13348 label = l != NULL ? l->label : NULL;
12746 mips_emit_delays ();
12747 if (auto_align)
12748 mips_align (2, 0, label);
12749 mips_clear_insn_labels ();
12750
12751 expression (&ex);
12752
12753 if (ex.X_op != O_symbol || ex.X_add_number != 0)

--- 8 unchanged lines hidden (view full) ---

12762 BFD_RELOC_GPREL32);
12763
12764 demand_empty_rest_of_line ();
12765}
12766
12767static void
12768s_gpdword (int ignore ATTRIBUTE_UNUSED)
12769{
13349 mips_emit_delays ();
13350 if (auto_align)
13351 mips_align (2, 0, label);
13352 mips_clear_insn_labels ();
13353
13354 expression (&ex);
13355
13356 if (ex.X_op != O_symbol || ex.X_add_number != 0)

--- 8 unchanged lines hidden (view full) ---

13365 BFD_RELOC_GPREL32);
13366
13367 demand_empty_rest_of_line ();
13368}
13369
13370static void
13371s_gpdword (int ignore ATTRIBUTE_UNUSED)
13372{
13373 segment_info_type *si;
13374 struct insn_label_list *l;
12770 symbolS *label;
12771 expressionS ex;
12772 char *p;
12773
12774 /* When not generating PIC code, this is treated as .dword. */
12775 if (mips_pic != SVR4_PIC)
12776 {
12777 s_cons (3);
12778 return;
12779 }
12780
13375 symbolS *label;
13376 expressionS ex;
13377 char *p;
13378
13379 /* When not generating PIC code, this is treated as .dword. */
13380 if (mips_pic != SVR4_PIC)
13381 {
13382 s_cons (3);
13383 return;
13384 }
13385
12781 label = insn_labels != NULL ? insn_labels->label : NULL;
13386 si = seg_info (now_seg);
13387 l = si->label_list;
13388 label = l != NULL ? l->label : NULL;
12782 mips_emit_delays ();
12783 if (auto_align)
12784 mips_align (3, 0, label);
12785 mips_clear_insn_labels ();
12786
12787 expression (&ex);
12788
12789 if (ex.X_op != O_symbol || ex.X_add_number != 0)

--- 65 unchanged lines hidden (view full) ---

12855s_mips_stab (int type)
12856{
12857 if (type == 'n')
12858 mips16_mark_labels ();
12859
12860 s_stab (type);
12861}
12862
13389 mips_emit_delays ();
13390 if (auto_align)
13391 mips_align (3, 0, label);
13392 mips_clear_insn_labels ();
13393
13394 expression (&ex);
13395
13396 if (ex.X_op != O_symbol || ex.X_add_number != 0)

--- 65 unchanged lines hidden (view full) ---

13462s_mips_stab (int type)
13463{
13464 if (type == 'n')
13465 mips16_mark_labels ();
13466
13467 s_stab (type);
13468}
13469
12863/* Handle the .weakext pseudo-op as defined in Kane and Heinrich.
12864 */
13470/* Handle the .weakext pseudo-op as defined in Kane and Heinrich. */
12865
12866static void
12867s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
12868{
12869 char *name;
12870 int c;
12871 symbolS *symbolP;
12872 expressionS exp;

--- 37 unchanged lines hidden (view full) ---

12910
12911/* Parse a register string into a number. Called from the ECOFF code
12912 to parse .frame. The argument is non-zero if this is the frame
12913 register, so that we can record it in mips_frame_reg. */
12914
12915int
12916tc_get_register (int frame)
12917{
13471
13472static void
13473s_mips_weakext (int ignore ATTRIBUTE_UNUSED)
13474{
13475 char *name;
13476 int c;
13477 symbolS *symbolP;
13478 expressionS exp;

--- 37 unchanged lines hidden (view full) ---

13516
13517/* Parse a register string into a number. Called from the ECOFF code
13518 to parse .frame. The argument is non-zero if this is the frame
13519 register, so that we can record it in mips_frame_reg. */
13520
13521int
13522tc_get_register (int frame)
13523{
12918 int reg;
13524 unsigned int reg;
12919
12920 SKIP_WHITESPACE ();
13525
13526 SKIP_WHITESPACE ();
12921 if (*input_line_pointer++ != '$')
12922 {
12923 as_warn (_("expected `$'"));
12924 reg = ZERO;
12925 }
12926 else if (ISDIGIT (*input_line_pointer))
12927 {
12928 reg = get_absolute_expression ();
12929 if (reg < 0 || reg >= 32)
12930 {
12931 as_warn (_("Bad register number"));
12932 reg = ZERO;
12933 }
12934 }
12935 else
12936 {
12937 if (strncmp (input_line_pointer, "ra", 2) == 0)
12938 {
12939 reg = RA;
12940 input_line_pointer += 2;
12941 }
12942 else if (strncmp (input_line_pointer, "fp", 2) == 0)
12943 {
12944 reg = FP;
12945 input_line_pointer += 2;
12946 }
12947 else if (strncmp (input_line_pointer, "sp", 2) == 0)
12948 {
12949 reg = SP;
12950 input_line_pointer += 2;
12951 }
12952 else if (strncmp (input_line_pointer, "gp", 2) == 0)
12953 {
12954 reg = GP;
12955 input_line_pointer += 2;
12956 }
12957 else if (strncmp (input_line_pointer, "at", 2) == 0)
12958 {
12959 reg = AT;
12960 input_line_pointer += 2;
12961 }
12962 else if (strncmp (input_line_pointer, "kt0", 3) == 0)
12963 {
12964 reg = KT0;
12965 input_line_pointer += 3;
12966 }
12967 else if (strncmp (input_line_pointer, "kt1", 3) == 0)
12968 {
12969 reg = KT1;
12970 input_line_pointer += 3;
12971 }
12972 else if (strncmp (input_line_pointer, "zero", 4) == 0)
12973 {
12974 reg = ZERO;
12975 input_line_pointer += 4;
12976 }
12977 else
12978 {
12979 as_warn (_("Unrecognized register name"));
12980 reg = ZERO;
12981 while (ISALNUM(*input_line_pointer))
12982 input_line_pointer++;
12983 }
12984 }
13527 if (! reg_lookup (&input_line_pointer, RWARN | RTYPE_NUM | RTYPE_GP, &reg))
13528 reg = 0;
12985 if (frame)
12986 {
12987 mips_frame_reg = reg != 0 ? reg : SP;
12988 mips_frame_reg_valid = 1;
12989 mips_cprestore_valid = 0;
12990 }
12991 return reg;
12992}
12993
12994valueT
12995md_section_align (asection *seg, valueT addr)
12996{
12997 int align = bfd_get_section_alignment (stdoutput, seg);
12998
13529 if (frame)
13530 {
13531 mips_frame_reg = reg != 0 ? reg : SP;
13532 mips_frame_reg_valid = 1;
13533 mips_cprestore_valid = 0;
13534 }
13535 return reg;
13536}
13537
13538valueT
13539md_section_align (asection *seg, valueT addr)
13540{
13541 int align = bfd_get_section_alignment (stdoutput, seg);
13542
12999#ifdef OBJ_ELF
13000 /* We don't need to align ELF sections to the full alignment.
13001 However, Irix 5 may prefer that we align them at least to a 16
13002 byte boundary. We don't bother to align the sections if we are
13003 targeted for an embedded system. */
13004 if (strcmp (TARGET_OS, "elf") == 0)
13005 return addr;
13006 if (align > 4)
13007 align = 4;
13008#endif
13543 if (IS_ELF)
13544 {
13545 /* We don't need to align ELF sections to the full alignment.
13546 However, Irix 5 may prefer that we align them at least to a 16
13547 byte boundary. We don't bother to align the sections if we
13548 are targeted for an embedded system. */
13549 if (strcmp (TARGET_OS, "elf") == 0)
13550 return addr;
13551 if (align > 4)
13552 align = 4;
13553 }
13009
13010 return ((addr + (1 << align) - 1) & (-1 << align));
13011}
13012
13013/* Utility routine, called from above as well. If called while the
13014 input file is still being read, it's only an approximation. (For
13015 example, a symbol may later become defined which appeared to be
13016 undefined earlier.) */

--- 49 unchanged lines hidden (view full) ---

13066 const char *segname;
13067
13068 segname = segment_name (S_GET_SEGMENT (sym));
13069 assert (strcmp (segname, ".lit8") != 0
13070 && strcmp (segname, ".lit4") != 0);
13071 change = (strcmp (segname, ".sdata") != 0
13072 && strcmp (segname, ".sbss") != 0
13073 && strncmp (segname, ".sdata.", 7) != 0
13554
13555 return ((addr + (1 << align) - 1) & (-1 << align));
13556}
13557
13558/* Utility routine, called from above as well. If called while the
13559 input file is still being read, it's only an approximation. (For
13560 example, a symbol may later become defined which appeared to be
13561 undefined earlier.) */

--- 49 unchanged lines hidden (view full) ---

13611 const char *segname;
13612
13613 segname = segment_name (S_GET_SEGMENT (sym));
13614 assert (strcmp (segname, ".lit8") != 0
13615 && strcmp (segname, ".lit4") != 0);
13616 change = (strcmp (segname, ".sdata") != 0
13617 && strcmp (segname, ".sbss") != 0
13618 && strncmp (segname, ".sdata.", 7) != 0
13619 && strncmp (segname, ".sbss.", 6) != 0
13620 && strncmp (segname, ".gnu.linkonce.sb.", 17) != 0
13074 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13075 }
13076 return change;
13077 }
13078 else
13079 /* We are not optimizing for the $gp register. */
13080 return 1;
13081}
13082
13083
13084/* Return true if the given symbol should be considered local for SVR4 PIC. */
13085
13086static bfd_boolean
13087pic_need_relax (symbolS *sym, asection *segtype)
13088{
13089 asection *symsec;
13621 && strncmp (segname, ".gnu.linkonce.s.", 16) != 0);
13622 }
13623 return change;
13624 }
13625 else
13626 /* We are not optimizing for the $gp register. */
13627 return 1;
13628}
13629
13630
13631/* Return true if the given symbol should be considered local for SVR4 PIC. */
13632
13633static bfd_boolean
13634pic_need_relax (symbolS *sym, asection *segtype)
13635{
13636 asection *symsec;
13090 bfd_boolean linkonce;
13091
13092 /* Handle the case of a symbol equated to another symbol. */
13093 while (symbol_equated_reloc_p (sym))
13094 {
13095 symbolS *n;
13096
13637
13638 /* Handle the case of a symbol equated to another symbol. */
13639 while (symbol_equated_reloc_p (sym))
13640 {
13641 symbolS *n;
13642
13097 /* It's possible to get a loop here in a badly written
13098 program. */
13643 /* It's possible to get a loop here in a badly written program. */
13099 n = symbol_get_value_expression (sym)->X_add_symbol;
13100 if (n == sym)
13101 break;
13102 sym = n;
13103 }
13104
13644 n = symbol_get_value_expression (sym)->X_add_symbol;
13645 if (n == sym)
13646 break;
13647 sym = n;
13648 }
13649
13650 if (symbol_section_p (sym))
13651 return TRUE;
13652
13105 symsec = S_GET_SEGMENT (sym);
13106
13653 symsec = S_GET_SEGMENT (sym);
13654
13107 /* duplicate the test for LINK_ONCE sections as in adjust_reloc_syms */
13108 linkonce = FALSE;
13109 if (symsec != segtype && ! S_IS_LOCAL (sym))
13110 {
13111 if ((bfd_get_section_flags (stdoutput, symsec) & SEC_LINK_ONCE)
13112 != 0)
13113 linkonce = TRUE;
13114
13115 /* The GNU toolchain uses an extension for ELF: a section
13116 beginning with the magic string .gnu.linkonce is a linkonce
13117 section. */
13118 if (strncmp (segment_name (symsec), ".gnu.linkonce",
13119 sizeof ".gnu.linkonce" - 1) == 0)
13120 linkonce = TRUE;
13121 }
13122
13123 /* This must duplicate the test in adjust_reloc_syms. */
13124 return (symsec != &bfd_und_section
13125 && symsec != &bfd_abs_section
13655 /* This must duplicate the test in adjust_reloc_syms. */
13656 return (symsec != &bfd_und_section
13657 && symsec != &bfd_abs_section
13126 && ! bfd_is_com_section (symsec)
13127 && !linkonce
13658 && !bfd_is_com_section (symsec)
13659 && !s_is_linkonce (sym, segtype)
13128#ifdef OBJ_ELF
13129 /* A global or weak symbol is treated as external. */
13660#ifdef OBJ_ELF
13661 /* A global or weak symbol is treated as external. */
13130 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
13131 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13662 && (!IS_ELF || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
13132#endif
13133 );
13134}
13135
13136
13137/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13138 extended opcode. SEC is the section the frag is in. */
13139
13140static int
13141mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13142{
13143 int type;
13663#endif
13664 );
13665}
13666
13667
13668/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13669 extended opcode. SEC is the section the frag is in. */
13670
13671static int
13672mips16_extended_frag (fragS *fragp, asection *sec, long stretch)
13673{
13674 int type;
13144 register const struct mips16_immed_operand *op;
13675 const struct mips16_immed_operand *op;
13145 offsetT val;
13146 int mintiny, maxtiny;
13147 segT symsec;
13148 fragS *sym_frag;
13149
13150 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13151 return 0;
13152 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))

--- 265 unchanged lines hidden (view full) ---

13418 /* We don't want to modify the EXTENDED bit here; it might get us
13419 into infinite loops. We change it only in mips_relax_frag(). */
13420 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13421
13422 if (mips_pic == NO_PIC)
13423 change = nopic_need_relax (fragp->fr_symbol, 0);
13424 else if (mips_pic == SVR4_PIC)
13425 change = pic_need_relax (fragp->fr_symbol, segtype);
13676 offsetT val;
13677 int mintiny, maxtiny;
13678 segT symsec;
13679 fragS *sym_frag;
13680
13681 if (RELAX_MIPS16_USER_SMALL (fragp->fr_subtype))
13682 return 0;
13683 if (RELAX_MIPS16_USER_EXT (fragp->fr_subtype))

--- 265 unchanged lines hidden (view full) ---

13949 /* We don't want to modify the EXTENDED bit here; it might get us
13950 into infinite loops. We change it only in mips_relax_frag(). */
13951 return (RELAX_MIPS16_EXTENDED (fragp->fr_subtype) ? 4 : 2);
13952
13953 if (mips_pic == NO_PIC)
13954 change = nopic_need_relax (fragp->fr_symbol, 0);
13955 else if (mips_pic == SVR4_PIC)
13956 change = pic_need_relax (fragp->fr_symbol, segtype);
13957 else if (mips_pic == VXWORKS_PIC)
13958 /* For vxworks, GOT16 relocations never have a corresponding LO16. */
13959 change = 0;
13426 else
13427 abort ();
13428
13429 if (change)
13430 {
13431 fragp->fr_subtype |= RELAX_USE_SECOND;
13432 return -RELAX_FIRST (fragp->fr_subtype);
13433 }
13434 else
13435 return -RELAX_SECOND (fragp->fr_subtype);
13436}
13437
13438/* This is called to see whether a reloc against a defined symbol
13439 should be converted into a reloc against a section. */
13440
13441int
13442mips_fix_adjustable (fixS *fixp)
13443{
13960 else
13961 abort ();
13962
13963 if (change)
13964 {
13965 fragp->fr_subtype |= RELAX_USE_SECOND;
13966 return -RELAX_FIRST (fragp->fr_subtype);
13967 }
13968 else
13969 return -RELAX_SECOND (fragp->fr_subtype);
13970}
13971
13972/* This is called to see whether a reloc against a defined symbol
13973 should be converted into a reloc against a section. */
13974
13975int
13976mips_fix_adjustable (fixS *fixp)
13977{
13444 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13445 about the format of the offset in the .o file. */
13446 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13447 return 0;
13448
13449 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13450 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13451 return 0;
13452
13453 if (fixp->fx_addsy == NULL)
13454 return 1;
13455
13456 /* If symbol SYM is in a mergeable section, relocations of the form

--- 6 unchanged lines hidden (view full) ---

13463 the merge data.
13464
13465 The linker has traditionally not looked for the parterning high part
13466 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13467 placed anywhere. Rather than break backwards compatibility by changing
13468 this, it seems better not to force the issue, and instead keep the
13469 original symbol. This will work with either linker behavior. */
13470 if ((fixp->fx_r_type == BFD_RELOC_LO16
13978 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13979 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13980 return 0;
13981
13982 if (fixp->fx_addsy == NULL)
13983 return 1;
13984
13985 /* If symbol SYM is in a mergeable section, relocations of the form

--- 6 unchanged lines hidden (view full) ---

13992 the merge data.
13993
13994 The linker has traditionally not looked for the parterning high part
13995 relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
13996 placed anywhere. Rather than break backwards compatibility by changing
13997 this, it seems better not to force the issue, and instead keep the
13998 original symbol. This will work with either linker behavior. */
13999 if ((fixp->fx_r_type == BFD_RELOC_LO16
14000 || fixp->fx_r_type == BFD_RELOC_MIPS16_LO16
13471 || reloc_needs_lo_p (fixp->fx_r_type))
13472 && HAVE_IN_PLACE_ADDENDS
13473 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13474 return 0;
13475
13476#ifdef OBJ_ELF
14001 || reloc_needs_lo_p (fixp->fx_r_type))
14002 && HAVE_IN_PLACE_ADDENDS
14003 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
14004 return 0;
14005
14006#ifdef OBJ_ELF
13477 /* Don't adjust relocations against mips16 symbols, so that the linker
13478 can find them if it needs to set up a stub. */
13479 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13480 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13481 && fixp->fx_subsy == NULL)
14007 /* R_MIPS16_26 relocations against non-MIPS16 functions might resolve
14008 to a floating-point stub. The same is true for non-R_MIPS16_26
14009 relocations against MIPS16 functions; in this case, the stub becomes
14010 the function's canonical address.
14011
14012 Floating-point stubs are stored in unique .mips16.call.* or
14013 .mips16.fn.* sections. If a stub T for function F is in section S,
14014 the first relocation in section S must be against F; this is how the
14015 linker determines the target function. All relocations that might
14016 resolve to T must also be against F. We therefore have the following
14017 restrictions, which are given in an intentionally-redundant way:
14018
14019 1. We cannot reduce R_MIPS16_26 relocations against non-MIPS16
14020 symbols.
14021
14022 2. We cannot reduce a stub's relocations against non-MIPS16 symbols
14023 if that stub might be used.
14024
14025 3. We cannot reduce non-R_MIPS16_26 relocations against MIPS16
14026 symbols.
14027
14028 4. We cannot reduce a stub's relocations against MIPS16 symbols if
14029 that stub might be used.
14030
14031 There is a further restriction:
14032
14033 5. We cannot reduce R_MIPS16_26 relocations against MIPS16 symbols
14034 on targets with in-place addends; the relocation field cannot
14035 encode the low bit.
14036
14037 For simplicity, we deal with (3)-(5) by not reducing _any_ relocation
14038 against a MIPS16 symbol.
14039
14040 We deal with (1)-(2) by saying that, if there's a R_MIPS16_26
14041 relocation against some symbol R, no relocation against R may be
14042 reduced. (Note that this deals with (2) as well as (1) because
14043 relocations against global symbols will never be reduced on ELF
14044 targets.) This approach is a little simpler than trying to detect
14045 stub sections, and gives the "all or nothing" per-symbol consistency
14046 that we have for MIPS16 symbols. */
14047 if (IS_ELF
14048 && fixp->fx_subsy == NULL
14049 && (S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
14050 || *symbol_get_tc (fixp->fx_addsy)))
13482 return 0;
13483#endif
13484
13485 return 1;
13486}
13487
13488/* Translate internal representation of relocation info to BFD target
13489 format. */

--- 13 unchanged lines hidden (view full) ---

13503
13504 if (fixp->fx_pcrel)
13505 {
13506 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
13507
13508 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13509 Relocations want only the symbol offset. */
13510 reloc->addend = fixp->fx_addnumber + reloc->address;
14051 return 0;
14052#endif
14053
14054 return 1;
14055}
14056
14057/* Translate internal representation of relocation info to BFD target
14058 format. */

--- 13 unchanged lines hidden (view full) ---

14072
14073 if (fixp->fx_pcrel)
14074 {
14075 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
14076
14077 /* At this point, fx_addnumber is "symbol offset - pcrel address".
14078 Relocations want only the symbol offset. */
14079 reloc->addend = fixp->fx_addnumber + reloc->address;
13511 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
14080 if (!IS_ELF)
13512 {
13513 /* A gruesome hack which is a result of the gruesome gas
13514 reloc handling. What's worse, for COFF (as opposed to
13515 ECOFF), we might need yet another copy of reloc->address.
13516 See bfd_install_relocation. */
13517 reloc->addend += reloc->address;
13518 }
13519 }

--- 82 unchanged lines hidden (view full) ---

13602 /* We generate a fixup instead of applying it right now
13603 because, if there are linker relaxations, we're going to
13604 need the relocations. */
13605 exp.X_op = O_symbol;
13606 exp.X_add_symbol = fragp->fr_symbol;
13607 exp.X_add_number = fragp->fr_offset;
13608
13609 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14081 {
14082 /* A gruesome hack which is a result of the gruesome gas
14083 reloc handling. What's worse, for COFF (as opposed to
14084 ECOFF), we might need yet another copy of reloc->address.
14085 See bfd_install_relocation. */
14086 reloc->addend += reloc->address;
14087 }
14088 }

--- 82 unchanged lines hidden (view full) ---

14171 /* We generate a fixup instead of applying it right now
14172 because, if there are linker relaxations, we're going to
14173 need the relocations. */
14174 exp.X_op = O_symbol;
14175 exp.X_add_symbol = fragp->fr_symbol;
14176 exp.X_add_number = fragp->fr_offset;
14177
14178 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13610 4, &exp, 1, BFD_RELOC_16_PCREL_S2);
14179 4, &exp, TRUE, BFD_RELOC_16_PCREL_S2);
13611 fixp->fx_file = fragp->fr_file;
13612 fixp->fx_line = fragp->fr_line;
13613
13614 md_number_to_chars ((char *) buf, insn, 4);
13615 buf += 4;
13616 }
13617 else
13618 {

--- 15 unchanged lines hidden (view full) ---

13634 have the condition reversed by tweaking a single
13635 bit, and their opcodes all have 0x4???????. */
13636 assert ((insn & 0xf1000000) == 0x41000000);
13637 insn ^= 0x00010000;
13638 break;
13639
13640 case 0:
13641 /* bltz 0x04000000 bgez 0x04010000
14180 fixp->fx_file = fragp->fr_file;
14181 fixp->fx_line = fragp->fr_line;
14182
14183 md_number_to_chars ((char *) buf, insn, 4);
14184 buf += 4;
14185 }
14186 else
14187 {

--- 15 unchanged lines hidden (view full) ---

14203 have the condition reversed by tweaking a single
14204 bit, and their opcodes all have 0x4???????. */
14205 assert ((insn & 0xf1000000) == 0x41000000);
14206 insn ^= 0x00010000;
14207 break;
14208
14209 case 0:
14210 /* bltz 0x04000000 bgez 0x04010000
13642 bltzal 0x04100000 bgezal 0x04110000 */
14211 bltzal 0x04100000 bgezal 0x04110000 */
13643 assert ((insn & 0xfc0e0000) == 0x04000000);
13644 insn ^= 0x00010000;
13645 break;
13646
13647 case 1:
13648 /* beq 0x10000000 bne 0x14000000
14212 assert ((insn & 0xfc0e0000) == 0x04000000);
14213 insn ^= 0x00010000;
14214 break;
14215
14216 case 1:
14217 /* beq 0x10000000 bne 0x14000000
13649 blez 0x18000000 bgtz 0x1c000000 */
14218 blez 0x18000000 bgtz 0x1c000000 */
13650 insn ^= 0x04000000;
13651 break;
13652
13653 default:
13654 abort ();
13655 }
13656 }
13657
13658 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13659 {
13660 /* Clear the and-link bit. */
13661 assert ((insn & 0xfc1c0000) == 0x04100000);
13662
14219 insn ^= 0x04000000;
14220 break;
14221
14222 default:
14223 abort ();
14224 }
14225 }
14226
14227 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
14228 {
14229 /* Clear the and-link bit. */
14230 assert ((insn & 0xfc1c0000) == 0x04100000);
14231
13663 /* bltzal 0x04100000 bgezal 0x04110000
13664 bltzall 0x04120000 bgezall 0x04130000 */
14232 /* bltzal 0x04100000 bgezal 0x04110000
14233 bltzall 0x04120000 bgezall 0x04130000 */
13665 insn &= ~0x00100000;
13666 }
13667
13668 /* Branch over the branch (if the branch was likely) or the
13669 full jump (not likely case). Compute the offset from the
13670 current instruction to branch to. */
13671 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13672 i = 16;

--- 8 unchanged lines hidden (view full) ---

13681 i >>= 2;
13682 /* Branch counts from the next instruction. */
13683 i--;
13684 insn |= i;
13685 /* Branch over the jump. */
13686 md_number_to_chars ((char *) buf, insn, 4);
13687 buf += 4;
13688
14234 insn &= ~0x00100000;
14235 }
14236
14237 /* Branch over the branch (if the branch was likely) or the
14238 full jump (not likely case). Compute the offset from the
14239 current instruction to branch to. */
14240 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14241 i = 16;

--- 8 unchanged lines hidden (view full) ---

14250 i >>= 2;
14251 /* Branch counts from the next instruction. */
14252 i--;
14253 insn |= i;
14254 /* Branch over the jump. */
14255 md_number_to_chars ((char *) buf, insn, 4);
14256 buf += 4;
14257
13689 /* Nop */
14258 /* nop */
13690 md_number_to_chars ((char *) buf, 0, 4);
13691 buf += 4;
13692
13693 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13694 {
13695 /* beql $0, $0, 2f */
13696 insn = 0x50000000;
13697 /* Compute the PC offset from the current instruction to

--- 21 unchanged lines hidden (view full) ---

13719 /* j or jal. */
13720 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13721 ? 0x0c000000 : 0x08000000);
13722 exp.X_op = O_symbol;
13723 exp.X_add_symbol = fragp->fr_symbol;
13724 exp.X_add_number = fragp->fr_offset;
13725
13726 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14259 md_number_to_chars ((char *) buf, 0, 4);
14260 buf += 4;
14261
14262 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
14263 {
14264 /* beql $0, $0, 2f */
14265 insn = 0x50000000;
14266 /* Compute the PC offset from the current instruction to

--- 21 unchanged lines hidden (view full) ---

14288 /* j or jal. */
14289 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
14290 ? 0x0c000000 : 0x08000000);
14291 exp.X_op = O_symbol;
14292 exp.X_add_symbol = fragp->fr_symbol;
14293 exp.X_add_number = fragp->fr_offset;
14294
14295 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13727 4, &exp, 0, BFD_RELOC_MIPS_JMP);
14296 4, &exp, FALSE, BFD_RELOC_MIPS_JMP);
13728 fixp->fx_file = fragp->fr_file;
13729 fixp->fx_line = fragp->fr_line;
13730
13731 md_number_to_chars ((char *) buf, insn, 4);
13732 buf += 4;
13733 }
13734 else
13735 {

--- 5 unchanged lines hidden (view full) ---

13741
13742 if (fragp->fr_offset)
13743 {
13744 exp.X_add_symbol = make_expr_symbol (&exp);
13745 exp.X_add_number = 0;
13746 }
13747
13748 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14297 fixp->fx_file = fragp->fr_file;
14298 fixp->fx_line = fragp->fr_line;
14299
14300 md_number_to_chars ((char *) buf, insn, 4);
14301 buf += 4;
14302 }
14303 else
14304 {

--- 5 unchanged lines hidden (view full) ---

14310
14311 if (fragp->fr_offset)
14312 {
14313 exp.X_add_symbol = make_expr_symbol (&exp);
14314 exp.X_add_number = 0;
14315 }
14316
14317 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13749 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
14318 4, &exp, FALSE, BFD_RELOC_MIPS_GOT16);
13750 fixp->fx_file = fragp->fr_file;
13751 fixp->fx_line = fragp->fr_line;
13752
13753 md_number_to_chars ((char *) buf, insn, 4);
13754 buf += 4;
13755
13756 if (mips_opts.isa == ISA_MIPS1)
13757 {
13758 /* nop */
13759 md_number_to_chars ((char *) buf, 0, 4);
13760 buf += 4;
13761 }
13762
13763 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13764 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13765
13766 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
14319 fixp->fx_file = fragp->fr_file;
14320 fixp->fx_line = fragp->fr_line;
14321
14322 md_number_to_chars ((char *) buf, insn, 4);
14323 buf += 4;
14324
14325 if (mips_opts.isa == ISA_MIPS1)
14326 {
14327 /* nop */
14328 md_number_to_chars ((char *) buf, 0, 4);
14329 buf += 4;
14330 }
14331
14332 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
14333 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
14334
14335 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13767 4, &exp, 0, BFD_RELOC_LO16);
14336 4, &exp, FALSE, BFD_RELOC_LO16);
13768 fixp->fx_file = fragp->fr_file;
13769 fixp->fx_line = fragp->fr_line;
13770
13771 md_number_to_chars ((char *) buf, insn, 4);
13772 buf += 4;
13773
13774 /* j(al)r $at. */
13775 if (RELAX_BRANCH_LINK (fragp->fr_subtype))

--- 12 unchanged lines hidden (view full) ---

13788 fragp->fr_fix += fragp->fr_var;
13789
13790 return;
13791 }
13792
13793 if (RELAX_MIPS16_P (fragp->fr_subtype))
13794 {
13795 int type;
14337 fixp->fx_file = fragp->fr_file;
14338 fixp->fx_line = fragp->fr_line;
14339
14340 md_number_to_chars ((char *) buf, insn, 4);
14341 buf += 4;
14342
14343 /* j(al)r $at. */
14344 if (RELAX_BRANCH_LINK (fragp->fr_subtype))

--- 12 unchanged lines hidden (view full) ---

14357 fragp->fr_fix += fragp->fr_var;
14358
14359 return;
14360 }
14361
14362 if (RELAX_MIPS16_P (fragp->fr_subtype))
14363 {
14364 int type;
13796 register const struct mips16_immed_operand *op;
14365 const struct mips16_immed_operand *op;
13797 bfd_boolean small, ext;
13798 offsetT val;
13799 bfd_byte *buf;
13800 unsigned long insn;
13801 bfd_boolean use_extend;
13802 unsigned short extend;
13803
13804 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);

--- 137 unchanged lines hidden (view full) ---

13942 back to even for the convenience of the debugger. */
13943
13944void
13945mips_frob_file_after_relocs (void)
13946{
13947 asymbol **syms;
13948 unsigned int count, i;
13949
14366 bfd_boolean small, ext;
14367 offsetT val;
14368 bfd_byte *buf;
14369 unsigned long insn;
14370 bfd_boolean use_extend;
14371 unsigned short extend;
14372
14373 type = RELAX_MIPS16_TYPE (fragp->fr_subtype);

--- 137 unchanged lines hidden (view full) ---

14511 back to even for the convenience of the debugger. */
14512
14513void
14514mips_frob_file_after_relocs (void)
14515{
14516 asymbol **syms;
14517 unsigned int count, i;
14518
13950 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
14519 if (!IS_ELF)
13951 return;
13952
13953 syms = bfd_get_outsymbols (stdoutput);
13954 count = bfd_get_symcount (stdoutput);
13955 for (i = 0; i < count; i++, syms++)
13956 {
13957 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
13958 && ((*syms)->value & 1) != 0)

--- 11 unchanged lines hidden (view full) ---

13970
13971/* This function is called whenever a label is defined. It is used
13972 when handling branch delays; if a branch has a label, we assume we
13973 can not move it. */
13974
13975void
13976mips_define_label (symbolS *sym)
13977{
14520 return;
14521
14522 syms = bfd_get_outsymbols (stdoutput);
14523 count = bfd_get_symcount (stdoutput);
14524 for (i = 0; i < count; i++, syms++)
14525 {
14526 if (elf_symbol (*syms)->internal_elf_sym.st_other == STO_MIPS16
14527 && ((*syms)->value & 1) != 0)

--- 11 unchanged lines hidden (view full) ---

14539
14540/* This function is called whenever a label is defined. It is used
14541 when handling branch delays; if a branch has a label, we assume we
14542 can not move it. */
14543
14544void
14545mips_define_label (symbolS *sym)
14546{
14547 segment_info_type *si = seg_info (now_seg);
13978 struct insn_label_list *l;
13979
13980 if (free_insn_labels == NULL)
13981 l = (struct insn_label_list *) xmalloc (sizeof *l);
13982 else
13983 {
13984 l = free_insn_labels;
13985 free_insn_labels = l->next;
13986 }
13987
13988 l->label = sym;
14548 struct insn_label_list *l;
14549
14550 if (free_insn_labels == NULL)
14551 l = (struct insn_label_list *) xmalloc (sizeof *l);
14552 else
14553 {
14554 l = free_insn_labels;
14555 free_insn_labels = l->next;
14556 }
14557
14558 l->label = sym;
13989 l->next = insn_labels;
13990 insn_labels = l;
14559 l->next = si->label_list;
14560 si->label_list = l;
14561
14562#ifdef OBJ_ELF
14563 dwarf2_emit_label (sym);
14564#endif
13991}
13992
13993#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
13994
13995/* Some special processing for a MIPS ELF file. */
13996
13997void
13998mips_elf_final_processing (void)

--- 41 unchanged lines hidden (view full) ---

14040 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14041 }
14042 if (mips_abicalls)
14043 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14044
14045 /* Set MIPS ELF flags for ASEs. */
14046 /* We may need to define a new flag for DSP ASE, and set this flag when
14047 file_ase_dsp is true. */
14565}
14566
14567#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
14568
14569/* Some special processing for a MIPS ELF file. */
14570
14571void
14572mips_elf_final_processing (void)

--- 41 unchanged lines hidden (view full) ---

14614 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14615 }
14616 if (mips_abicalls)
14617 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14618
14619 /* Set MIPS ELF flags for ASEs. */
14620 /* We may need to define a new flag for DSP ASE, and set this flag when
14621 file_ase_dsp is true. */
14622 /* Same for DSP R2. */
14048 /* We may need to define a new flag for MT ASE, and set this flag when
14049 file_ase_mt is true. */
14050 if (file_ase_mips16)
14051 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14052#if 0 /* XXX FIXME */
14053 if (file_ase_mips3d)
14054 elf_elfheader (stdoutput)->e_flags |= ???;
14055#endif

--- 14 unchanged lines hidden (view full) ---

14070 }
14071 else if (mips_abi == N32_ABI)
14072 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14073
14074 /* Nothing to do for N64_ABI. */
14075
14076 if (mips_32bitmode)
14077 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14623 /* We may need to define a new flag for MT ASE, and set this flag when
14624 file_ase_mt is true. */
14625 if (file_ase_mips16)
14626 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14627#if 0 /* XXX FIXME */
14628 if (file_ase_mips3d)
14629 elf_elfheader (stdoutput)->e_flags |= ???;
14630#endif

--- 14 unchanged lines hidden (view full) ---

14645 }
14646 else if (mips_abi == N32_ABI)
14647 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ABI2;
14648
14649 /* Nothing to do for N64_ABI. */
14650
14651 if (mips_32bitmode)
14652 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14653
14654#if 0 /* XXX FIXME */
14655 /* 32 bit code with 64 bit FP registers. */
14656 if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi))
14657 elf_elfheader (stdoutput)->e_flags |= ???;
14658#endif
14078}
14079
14080#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14081
14082typedef struct proc {
14083 symbolS *func_sym;
14084 symbolS *func_end_sym;
14085 unsigned long reg_mask;

--- 44 unchanged lines hidden (view full) ---

14130static void
14131md_obj_begin (void)
14132{
14133}
14134
14135static void
14136md_obj_end (void)
14137{
14659}
14660
14661#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14662
14663typedef struct proc {
14664 symbolS *func_sym;
14665 symbolS *func_end_sym;
14666 unsigned long reg_mask;

--- 44 unchanged lines hidden (view full) ---

14711static void
14712md_obj_begin (void)
14713{
14714}
14715
14716static void
14717md_obj_end (void)
14718{
14138 /* check for premature end, nesting errors, etc */
14719 /* Check for premature end, nesting errors, etc. */
14139 if (cur_proc_ptr)
14140 as_warn (_("missing .end at end of assembly"));
14141}
14142
14143static long
14144get_number (void)
14145{
14146 int negative = 0;

--- 66 unchanged lines hidden (view full) ---

14213
14214 /* Versions of GCC up to 3.1 start files with a ".file"
14215 directive even for stabs output. Make sure that this
14216 ".file" is handled. Note that you need a version of GCC
14217 after 3.1 in order to support DWARF-2 on MIPS. */
14218 if (filename != NULL && ! first_file_directive)
14219 {
14220 (void) new_logical_line (filename, -1);
14720 if (cur_proc_ptr)
14721 as_warn (_("missing .end at end of assembly"));
14722}
14723
14724static long
14725get_number (void)
14726{
14727 int negative = 0;

--- 66 unchanged lines hidden (view full) ---

14794
14795 /* Versions of GCC up to 3.1 start files with a ".file"
14796 directive even for stabs output. Make sure that this
14797 ".file" is handled. Note that you need a version of GCC
14798 after 3.1 in order to support DWARF-2 on MIPS. */
14799 if (filename != NULL && ! first_file_directive)
14800 {
14801 (void) new_logical_line (filename, -1);
14221 s_app_file_string (filename);
14802 s_app_file_string (filename, 0);
14222 }
14223 first_file_directive = 1;
14224 }
14225}
14226
14227/* The .loc directive, implying DWARF-2. */
14228
14229static void

--- 57 unchanged lines hidden (view full) ---

14287 exp->X_add_symbol = symbol_temp_new_now ();
14288 exp->X_op_symbol = p;
14289 exp->X_add_number = 0;
14290
14291 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14292 }
14293
14294 /* Generate a .pdr section. */
14803 }
14804 first_file_directive = 1;
14805 }
14806}
14807
14808/* The .loc directive, implying DWARF-2. */
14809
14810static void

--- 57 unchanged lines hidden (view full) ---

14868 exp->X_add_symbol = symbol_temp_new_now ();
14869 exp->X_op_symbol = p;
14870 exp->X_add_number = 0;
14871
14872 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14873 }
14874
14875 /* Generate a .pdr section. */
14295 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14296 && mips_flag_pdr)
14876 if (IS_ELF && !ECOFF_DEBUGGING && mips_flag_pdr)
14297 {
14298 segT saved_seg = now_seg;
14299 subsegT saved_subseg = now_subseg;
14300 valueT dot;
14301 expressionS exp;
14302 char *fragp;
14303
14304 dot = frag_now_fix ();

--- 77 unchanged lines hidden (view full) ---

14382 s_mips_frame is used so that we can set the PDR information correctly.
14383 We can't use the ecoff routines because they make reference to the ecoff
14384 symbol table (in the mdebug section). */
14385
14386static void
14387s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14388{
14389#ifdef OBJ_ELF
14877 {
14878 segT saved_seg = now_seg;
14879 subsegT saved_subseg = now_subseg;
14880 valueT dot;
14881 expressionS exp;
14882 char *fragp;
14883
14884 dot = frag_now_fix ();

--- 77 unchanged lines hidden (view full) ---

14962 s_mips_frame is used so that we can set the PDR information correctly.
14963 We can't use the ecoff routines because they make reference to the ecoff
14964 symbol table (in the mdebug section). */
14965
14966static void
14967s_mips_frame (int ignore ATTRIBUTE_UNUSED)
14968{
14969#ifdef OBJ_ELF
14390 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
14970 if (IS_ELF && !ECOFF_DEBUGGING)
14391 {
14392 long val;
14393
14394 if (cur_proc_ptr == (procS *) NULL)
14395 {
14396 as_warn (_(".frame outside of .ent"));
14397 demand_empty_rest_of_line ();
14398 return;

--- 26 unchanged lines hidden (view full) ---

14425 embedded targets, s_mips_mask is used so that we can set the PDR
14426 information correctly. We can't use the ecoff routines because they
14427 make reference to the ecoff symbol table (in the mdebug section). */
14428
14429static void
14430s_mips_mask (int reg_type)
14431{
14432#ifdef OBJ_ELF
14971 {
14972 long val;
14973
14974 if (cur_proc_ptr == (procS *) NULL)
14975 {
14976 as_warn (_(".frame outside of .ent"));
14977 demand_empty_rest_of_line ();
14978 return;

--- 26 unchanged lines hidden (view full) ---

15005 embedded targets, s_mips_mask is used so that we can set the PDR
15006 information correctly. We can't use the ecoff routines because they
15007 make reference to the ecoff symbol table (in the mdebug section). */
15008
15009static void
15010s_mips_mask (int reg_type)
15011{
15012#ifdef OBJ_ELF
14433 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING)
15013 if (IS_ELF && !ECOFF_DEBUGGING)
14434 {
14435 long mask, off;
14436
14437 if (cur_proc_ptr == (procS *) NULL)
14438 {
14439 as_warn (_(".mask/.fmask outside of .ent"));
14440 demand_empty_rest_of_line ();
14441 return;

--- 30 unchanged lines hidden (view full) ---

14472/* A table describing all the processors gas knows about. Names are
14473 matched in the order listed.
14474
14475 To ease comparison, please keep this table in the same order as
14476 gcc's mips_cpu_info_table[]. */
14477static const struct mips_cpu_info mips_cpu_info_table[] =
14478{
14479 /* Entries for generic ISAs */
15014 {
15015 long mask, off;
15016
15017 if (cur_proc_ptr == (procS *) NULL)
15018 {
15019 as_warn (_(".mask/.fmask outside of .ent"));
15020 demand_empty_rest_of_line ();
15021 return;

--- 30 unchanged lines hidden (view full) ---

15052/* A table describing all the processors gas knows about. Names are
15053 matched in the order listed.
15054
15055 To ease comparison, please keep this table in the same order as
15056 gcc's mips_cpu_info_table[]. */
15057static const struct mips_cpu_info mips_cpu_info_table[] =
15058{
15059 /* Entries for generic ISAs */
14480 { "mips1", 1, ISA_MIPS1, CPU_R3000 },
14481 { "mips2", 1, ISA_MIPS2, CPU_R6000 },
14482 { "mips3", 1, ISA_MIPS3, CPU_R4000 },
14483 { "mips4", 1, ISA_MIPS4, CPU_R8000 },
14484 { "mips5", 1, ISA_MIPS5, CPU_MIPS5 },
14485 { "mips32", 1, ISA_MIPS32, CPU_MIPS32 },
14486 { "mips32r2", 1, ISA_MIPS32R2, CPU_MIPS32R2 },
14487 { "mips64", 1, ISA_MIPS64, CPU_MIPS64 },
14488 { "mips64r2", 1, ISA_MIPS64R2, CPU_MIPS64R2 },
15060 { "mips1", MIPS_CPU_IS_ISA, ISA_MIPS1, CPU_R3000 },
15061 { "mips2", MIPS_CPU_IS_ISA, ISA_MIPS2, CPU_R6000 },
15062 { "mips3", MIPS_CPU_IS_ISA, ISA_MIPS3, CPU_R4000 },
15063 { "mips4", MIPS_CPU_IS_ISA, ISA_MIPS4, CPU_R8000 },
15064 { "mips5", MIPS_CPU_IS_ISA, ISA_MIPS5, CPU_MIPS5 },
15065 { "mips32", MIPS_CPU_IS_ISA, ISA_MIPS32, CPU_MIPS32 },
15066 { "mips32r2", MIPS_CPU_IS_ISA, ISA_MIPS32R2, CPU_MIPS32R2 },
15067 { "mips64", MIPS_CPU_IS_ISA, ISA_MIPS64, CPU_MIPS64 },
15068 { "mips64r2", MIPS_CPU_IS_ISA, ISA_MIPS64R2, CPU_MIPS64R2 },
14489
14490 /* MIPS I */
15069
15070 /* MIPS I */
14491 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
14492 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
14493 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
15071 { "r3000", 0, ISA_MIPS1, CPU_R3000 },
15072 { "r2000", 0, ISA_MIPS1, CPU_R3000 },
15073 { "r3900", 0, ISA_MIPS1, CPU_R3900 },
14494
14495 /* MIPS II */
15074
15075 /* MIPS II */
14496 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
15076 { "r6000", 0, ISA_MIPS2, CPU_R6000 },
14497
14498 /* MIPS III */
15077
15078 /* MIPS III */
14499 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
14500 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
14501 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
14502 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
14503 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
14504 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
14505 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
14506 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
14507 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
14508 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
14509 { "orion", 0, ISA_MIPS3, CPU_R4600 },
14510 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
15079 { "r4000", 0, ISA_MIPS3, CPU_R4000 },
15080 { "r4010", 0, ISA_MIPS2, CPU_R4010 },
15081 { "vr4100", 0, ISA_MIPS3, CPU_VR4100 },
15082 { "vr4111", 0, ISA_MIPS3, CPU_R4111 },
15083 { "vr4120", 0, ISA_MIPS3, CPU_VR4120 },
15084 { "vr4130", 0, ISA_MIPS3, CPU_VR4120 },
15085 { "vr4181", 0, ISA_MIPS3, CPU_R4111 },
15086 { "vr4300", 0, ISA_MIPS3, CPU_R4300 },
15087 { "r4400", 0, ISA_MIPS3, CPU_R4400 },
15088 { "r4600", 0, ISA_MIPS3, CPU_R4600 },
15089 { "orion", 0, ISA_MIPS3, CPU_R4600 },
15090 { "r4650", 0, ISA_MIPS3, CPU_R4650 },
14511
14512 /* MIPS IV */
15091
15092 /* MIPS IV */
14513 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
14514 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
14515 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
14516 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
14517 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14518 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14519 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14520 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14521 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14522 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14523 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14524 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14525 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
15093 { "r8000", 0, ISA_MIPS4, CPU_R8000 },
15094 { "r10000", 0, ISA_MIPS4, CPU_R10000 },
15095 { "r12000", 0, ISA_MIPS4, CPU_R12000 },
15096 { "vr5000", 0, ISA_MIPS4, CPU_R5000 },
15097 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
15098 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
15099 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
15100 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
15101 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
15102 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
15103 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
15104 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
15105 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
14526
14527 /* MIPS 32 */
15106
15107 /* MIPS 32 */
14528 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14529 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14530 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15108 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
15109 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
15110 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
15111 { "4ksc", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32, CPU_MIPS32 },
14531
15112
14532 /* MIPS32 Release 2 */
14533 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14534 { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14535 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14536 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14537 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15113 /* MIPS 32 Release 2 */
15114 { "4kec", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15115 { "4kem", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15116 { "4kep", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15117 { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 },
15118 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15119 { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15120 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15121 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15122 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
15123 /* 24KE is a 24K with DSP ASE, other ASEs are optional. */
15124 { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15125 { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15126 { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 },
15127 /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */
15128 { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15129 ISA_MIPS32R2, CPU_MIPS32R2 },
15130 { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15131 ISA_MIPS32R2, CPU_MIPS32R2 },
15132 { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT,
15133 ISA_MIPS32R2, CPU_MIPS32R2 },
15134 /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */
15135 { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15136 ISA_MIPS32R2, CPU_MIPS32R2 },
15137 { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15138 ISA_MIPS32R2, CPU_MIPS32R2 },
15139 { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2,
15140 ISA_MIPS32R2, CPU_MIPS32R2 },
14538
14539 /* MIPS 64 */
15141
15142 /* MIPS 64 */
14540 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14541 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
14542 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
15143 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
15144 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
15145 { "20kc", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
15146 { "25kf", MIPS_CPU_ASE_MIPS3D, ISA_MIPS64, CPU_MIPS64 },
14543
15147
15148 /* MIPS 64 Release 2 */
15149
14544 /* Broadcom SB-1 CPU core */
15150 /* Broadcom SB-1 CPU core */
14545 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
15151 { "sb1", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15152 ISA_MIPS64, CPU_SB1 },
15153 /* Broadcom SB-1A CPU core */
15154 { "sb1a", MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
15155 ISA_MIPS64, CPU_SB1 },
14546
14547 /* Cavium Networks Octeon CPU core */
14548 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
14549
14550 /* End marker */
14551 { NULL, 0, 0, 0 }
14552};
14553

--- 101 unchanged lines hidden (view full) ---

14655 ISA_MIPS* enumeration). */
14656
14657static const struct mips_cpu_info *
14658mips_cpu_info_from_isa (int isa)
14659{
14660 int i;
14661
14662 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
15156
15157 /* Cavium Networks Octeon CPU core */
15158 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
15159
15160 /* End marker */
15161 { NULL, 0, 0, 0 }
15162};
15163

--- 101 unchanged lines hidden (view full) ---

15265 ISA_MIPS* enumeration). */
15266
15267static const struct mips_cpu_info *
15268mips_cpu_info_from_isa (int isa)
15269{
15270 int i;
15271
15272 for (i = 0; mips_cpu_info_table[i].name != NULL; i++)
14663 if (mips_cpu_info_table[i].is_isa
15273 if ((mips_cpu_info_table[i].flags & MIPS_CPU_IS_ISA)
14664 && isa == mips_cpu_info_table[i].isa)
14665 return (&mips_cpu_info_table[i]);
14666
14667 return NULL;
14668}
14669
14670static const struct mips_cpu_info *
14671mips_cpu_info_from_arch (int arch)

--- 77 unchanged lines hidden (view full) ---

14749 show (stream, "4100", &column, &first);
14750 show (stream, "4650", &column, &first);
14751 fputc ('\n', stream);
14752
14753 fprintf (stream, _("\
14754-mips16 generate mips16 instructions\n\
14755-no-mips16 do not generate mips16 instructions\n"));
14756 fprintf (stream, _("\
15274 && isa == mips_cpu_info_table[i].isa)
15275 return (&mips_cpu_info_table[i]);
15276
15277 return NULL;
15278}
15279
15280static const struct mips_cpu_info *
15281mips_cpu_info_from_arch (int arch)

--- 77 unchanged lines hidden (view full) ---

15359 show (stream, "4100", &column, &first);
15360 show (stream, "4650", &column, &first);
15361 fputc ('\n', stream);
15362
15363 fprintf (stream, _("\
15364-mips16 generate mips16 instructions\n\
15365-no-mips16 do not generate mips16 instructions\n"));
15366 fprintf (stream, _("\
15367-msmartmips generate smartmips instructions\n\
15368-mno-smartmips do not generate smartmips instructions\n"));
15369 fprintf (stream, _("\
14757-mdsp generate DSP instructions\n\
14758-mno-dsp do not generate DSP instructions\n"));
14759 fprintf (stream, _("\
15370-mdsp generate DSP instructions\n\
15371-mno-dsp do not generate DSP instructions\n"));
15372 fprintf (stream, _("\
15373-mdspr2 generate DSP R2 instructions\n\
15374-mno-dspr2 do not generate DSP R2 instructions\n"));
15375 fprintf (stream, _("\
14760-mmt generate MT instructions\n\
14761-mno-mt do not generate MT instructions\n"));
14762 fprintf (stream, _("\
14763-mfix-vr4120 work around certain VR4120 errata\n\
14764-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14765-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14766-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
15376-mmt generate MT instructions\n\
15377-mno-mt do not generate MT instructions\n"));
15378 fprintf (stream, _("\
15379-mfix-vr4120 work around certain VR4120 errata\n\
15380-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
15381-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
15382-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14767-mno-shared optimize output for executables\n\
14768-msym32 assume all symbols have 32-bit values\n\
14769-O0 remove unneeded NOPs, do not swap branches\n\
14770-O remove unneeded NOPs and swap branches\n\
14771--[no-]construct-floats [dis]allow floating point values to be constructed\n\
14772--trap, --no-break trap exception on div by 0 and mult overflow\n\
14773--break, --no-trap break exception on div by 0 and mult overflow\n"));
14774#ifdef OBJ_ELF
14775 fprintf (stream, _("\
14776-KPIC, -call_shared generate SVR4 position independent code\n\
15383-msym32 assume all symbols have 32-bit values\n\
15384-O0 remove unneeded NOPs, do not swap branches\n\
15385-O remove unneeded NOPs and swap branches\n\
15386--[no-]construct-floats [dis]allow floating point values to be constructed\n\
15387--trap, --no-break trap exception on div by 0 and mult overflow\n\
15388--break, --no-trap break exception on div by 0 and mult overflow\n"));
15389#ifdef OBJ_ELF
15390 fprintf (stream, _("\
15391-KPIC, -call_shared generate SVR4 position independent code\n\
15392-mvxworks-pic generate VxWorks position independent code\n\
14777-non_shared do not generate position independent code\n\
14778-xgot assume a 32 bit GOT\n\
14779-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14780-mshared, -mno-shared disable/enable .cpload optimization for\n\
15393-non_shared do not generate position independent code\n\
15394-xgot assume a 32 bit GOT\n\
15395-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
15396-mshared, -mno-shared disable/enable .cpload optimization for\n\
14781 non-shared code\n\
15397 position dependent (non shared) code\n\
14782-mabi=ABI create ABI conformant object file for:\n"));
14783
14784 first = 1;
14785
14786 show (stream, "32", &column, &first);
14787 show (stream, "o64", &column, &first);
14788 show (stream, "n32", &column, &first);
14789 show (stream, "64", &column, &first);

--- 40 unchanged lines hidden (view full) ---

14830
14831/* Standard calling conventions leave the CFA at SP on entry. */
14832void
14833mips_cfi_frame_initial_instructions (void)
14834{
14835 cfi_add_CFA_def_cfa_register (SP);
14836}
14837
15398-mabi=ABI create ABI conformant object file for:\n"));
15399
15400 first = 1;
15401
15402 show (stream, "32", &column, &first);
15403 show (stream, "o64", &column, &first);
15404 show (stream, "n32", &column, &first);
15405 show (stream, "64", &column, &first);

--- 40 unchanged lines hidden (view full) ---

15446
15447/* Standard calling conventions leave the CFA at SP on entry. */
15448void
15449mips_cfi_frame_initial_instructions (void)
15450{
15451 cfi_add_CFA_def_cfa_register (SP);
15452}
15453
15454int
15455tc_mips_regname_to_dw2regnum (char *regname)
15456{
15457 unsigned int regnum = -1;
15458 unsigned int reg;
15459
15460 if (reg_lookup (&regname, RTYPE_GP | RTYPE_NUM, &reg))
15461 regnum = reg;
15462
15463 return regnum;
15464}