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tc-mips.c (185925) tc-mips.c (208737)
1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
1/* tc-mips.c -- assemble code for a MIPS chip.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
3 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
4 Contributed by the OSF and Ralph Campbell.
5 Written by Keith Knowles and Ralph Campbell, working independently.
6 Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus
7 Support.
8
9 This file is part of GAS.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 02111-1307, USA. */
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
25
26#include "as.h"
27#include "config.h"
28#include "subsegs.h"
29#include "safe-ctype.h"
30
31#include <stdarg.h>
32
33#include "opcode/mips.h"
34#include "itbl-ops.h"
35#include "dwarf2dbg.h"
25
26#include "as.h"
27#include "config.h"
28#include "subsegs.h"
29#include "safe-ctype.h"
30
31#include <stdarg.h>
32
33#include "opcode/mips.h"
34#include "itbl-ops.h"
35#include "dwarf2dbg.h"
36#include "dw2gencfi.h"
36
37#ifdef DEBUG
38#define DBG(x) printf x
39#else
40#define DBG(x)
41#endif
42
43#ifdef OBJ_MAYBE_ELF

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78 linker doesn't know about and discards them, but relocations against them
79 remain, leading to rld crashes. */
80#ifdef TE_IRIX
81int mips_flag_pdr = FALSE;
82#else
83int mips_flag_pdr = TRUE;
84#endif
85
37
38#ifdef DEBUG
39#define DBG(x) printf x
40#else
41#define DBG(x)
42#endif
43
44#ifdef OBJ_MAYBE_ELF

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79 linker doesn't know about and discards them, but relocations against them
80 remain, leading to rld crashes. */
81#ifdef TE_IRIX
82int mips_flag_pdr = FALSE;
83#else
84int mips_flag_pdr = TRUE;
85#endif
86
87/* Control generation of error message for unsupported instructions in
88 Octeon. Octeon does not have floating point, and all the instructions
89 that use floating point registers are not allowed in Elf targets but
90 are allowed in Linux targets by default. */
91#ifdef OCTEON_ERROR_ON_UNSUPPORTED
92static int octeon_error_on_unsupported = 1;
93#else
94static int octeon_error_on_unsupported = 0;
95#endif
96
97/* Control generation of Octeon/MIPS unaligned load/store instructions.
98 For ELF target, default to Octeon load/store instructions.
99 For Linux target, default to MIPS load/store instructions. */
100#ifdef OCTEON_USE_UNALIGN
101static int octeon_use_unalign = 1;
102#else
103static int octeon_use_unalign = 0;
104#endif
105
86#include "ecoff.h"
87
88#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
89static char *mips_regmask_frag;
90#endif
91
92#define ZERO 0
93#define AT 1

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106
107#ifndef ECOFF_LITTLE_FORMAT
108#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
109#endif
110
111extern int target_big_endian;
112
113/* The name of the readonly data section. */
106#include "ecoff.h"
107
108#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
109static char *mips_regmask_frag;
110#endif
111
112#define ZERO 0
113#define AT 1

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126
127#ifndef ECOFF_LITTLE_FORMAT
128#define ECOFF_LITTLE_FORMAT "ecoff-littlemips"
129#endif
130
131extern int target_big_endian;
132
133/* The name of the readonly data section. */
114#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_aout_flavour \
115 ? ".data" \
116 : OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
134#define RDATA_SECTION_NAME (OUTPUT_FLAVOR == bfd_target_ecoff_flavour \
117 ? ".rdata" \
118 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
119 ? ".rdata" \
120 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
121 ? ".rodata" \
122 : (abort (), ""))
123
135 ? ".rdata" \
136 : OUTPUT_FLAVOR == bfd_target_coff_flavour \
137 ? ".rdata" \
138 : OUTPUT_FLAVOR == bfd_target_elf_flavour \
139 ? ".rodata" \
140 : (abort (), ""))
141
142/* Information about an instruction, including its format, operands
143 and fixups. */
144struct mips_cl_insn
145{
146 /* The opcode's entry in mips_opcodes or mips16_opcodes. */
147 const struct mips_opcode *insn_mo;
148
149 /* True if this is a mips16 instruction and if we want the extended
150 form of INSN_MO. */
151 bfd_boolean use_extend;
152
153 /* The 16-bit extension instruction to use when USE_EXTEND is true. */
154 unsigned short extend;
155
156 /* The 16-bit or 32-bit bitstring of the instruction itself. This is
157 a copy of INSN_MO->match with the operands filled in. */
158 unsigned long insn_opcode;
159
160 /* The frag that contains the instruction. */
161 struct frag *frag;
162
163 /* The offset into FRAG of the first instruction byte. */
164 long where;
165
166 /* The relocs associated with the instruction, if any. */
167 fixS *fixp[3];
168
169 /* True if this entry cannot be moved from its current position. */
170 unsigned int fixed_p : 1;
171
172 /* True if this instruction occured in a .set noreorder block. */
173 unsigned int noreorder_p : 1;
174
175 /* True for mips16 instructions that jump to an absolute address. */
176 unsigned int mips16_absolute_jump_p : 1;
177};
178
124/* The ABI to use. */
125enum mips_abi_level
126{
127 NO_ABI = 0,
128 O32_ABI,
129 O64_ABI,
130 N32_ABI,
131 N64_ABI,
132 EABI_ABI
133};
134
135/* MIPS ABI we are using for this output file. */
136static enum mips_abi_level mips_abi = NO_ABI;
137
138/* Whether or not we have code that can call pic code. */
139int mips_abicalls = FALSE;
140
179/* The ABI to use. */
180enum mips_abi_level
181{
182 NO_ABI = 0,
183 O32_ABI,
184 O64_ABI,
185 N32_ABI,
186 N64_ABI,
187 EABI_ABI
188};
189
190/* MIPS ABI we are using for this output file. */
191static enum mips_abi_level mips_abi = NO_ABI;
192
193/* Whether or not we have code that can call pic code. */
194int mips_abicalls = FALSE;
195
196/* Whether or not we have code which can be put into a shared
197 library. */
198static bfd_boolean mips_in_shared = TRUE;
199
141/* This is the set of options which may be modified by the .set
142 pseudo-op. We use a struct so that .set push and .set pop are more
143 reliable. */
144
145struct mips_set_options
146{
147 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
148 if it has not been initialized. Changed by `.set mipsN', and the
149 -mipsN command line option, and the default CPU. */
150 int isa;
151 /* Enabled Application Specific Extensions (ASEs). These are set to -1
152 if they have not been initialized. Changed by `.set <asename>', by
153 command line options, and based on the default architecture. */
154 int ase_mips3d;
155 int ase_mdmx;
200/* This is the set of options which may be modified by the .set
201 pseudo-op. We use a struct so that .set push and .set pop are more
202 reliable. */
203
204struct mips_set_options
205{
206 /* MIPS ISA (Instruction Set Architecture) level. This is set to -1
207 if it has not been initialized. Changed by `.set mipsN', and the
208 -mipsN command line option, and the default CPU. */
209 int isa;
210 /* Enabled Application Specific Extensions (ASEs). These are set to -1
211 if they have not been initialized. Changed by `.set <asename>', by
212 command line options, and based on the default architecture. */
213 int ase_mips3d;
214 int ase_mdmx;
215 int ase_dsp;
216 int ase_mt;
156 /* Whether we are assembling for the mips16 processor. 0 if we are
157 not, 1 if we are, and -1 if the value has not been initialized.
158 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
159 -nomips16 command line options, and the default CPU. */
160 int mips16;
161 /* Non-zero if we should not reorder instructions. Changed by `.set
162 reorder' and `.set noreorder'. */
163 int noreorder;

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182 /* Restrict general purpose registers and floating point registers
183 to 32 bit. This is initially determined when -mgp32 or -mfp32
184 is passed but can changed if the assembler code uses .set mipsN. */
185 int gp32;
186 int fp32;
187 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
188 command line option, and the default CPU. */
189 int arch;
217 /* Whether we are assembling for the mips16 processor. 0 if we are
218 not, 1 if we are, and -1 if the value has not been initialized.
219 Changed by `.set mips16' and `.set nomips16', and the -mips16 and
220 -nomips16 command line options, and the default CPU. */
221 int mips16;
222 /* Non-zero if we should not reorder instructions. Changed by `.set
223 reorder' and `.set noreorder'. */
224 int noreorder;

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243 /* Restrict general purpose registers and floating point registers
244 to 32 bit. This is initially determined when -mgp32 or -mfp32
245 is passed but can changed if the assembler code uses .set mipsN. */
246 int gp32;
247 int fp32;
248 /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march
249 command line option, and the default CPU. */
250 int arch;
251 /* True if ".set sym32" is in effect. */
252 bfd_boolean sym32;
190};
191
192/* True if -mgp32 was passed. */
193static int file_mips_gp32 = -1;
194
195/* True if -mfp32 was passed. */
196static int file_mips_fp32 = -1;
197
198/* This is the struct we use to hold the current set of options. Note
199 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
200 -1 to indicate that they have not been initialized. */
201
202static struct mips_set_options mips_opts =
203{
253};
254
255/* True if -mgp32 was passed. */
256static int file_mips_gp32 = -1;
257
258/* True if -mfp32 was passed. */
259static int file_mips_fp32 = -1;
260
261/* This is the struct we use to hold the current set of options. Note
262 that we must set the isa field to ISA_UNKNOWN and the ASE fields to
263 -1 to indicate that they have not been initialized. */
264
265static struct mips_set_options mips_opts =
266{
204 ISA_UNKNOWN, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN
267 ISA_UNKNOWN, -1, -1, -1, -1, -1, 0, 0, 0, 0, 0, 0, 0, 0, CPU_UNKNOWN, FALSE
205};
206
207/* These variables are filled in with the masks of registers used.
208 The object format code reads them and puts them in the appropriate
209 place. */
210unsigned long mips_gprmask;
211unsigned long mips_cprmask[4];
212

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220/* True if -mips3d was passed or implied by arguments passed on the
221 command line (e.g., by -march). */
222static int file_ase_mips3d;
223
224/* True if -mdmx was passed or implied by arguments passed on the
225 command line (e.g., by -march). */
226static int file_ase_mdmx;
227
268};
269
270/* These variables are filled in with the masks of registers used.
271 The object format code reads them and puts them in the appropriate
272 place. */
273unsigned long mips_gprmask;
274unsigned long mips_cprmask[4];
275

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283/* True if -mips3d was passed or implied by arguments passed on the
284 command line (e.g., by -march). */
285static int file_ase_mips3d;
286
287/* True if -mdmx was passed or implied by arguments passed on the
288 command line (e.g., by -march). */
289static int file_ase_mdmx;
290
291/* True if -mdsp was passed or implied by arguments passed on the
292 command line (e.g., by -march). */
293static int file_ase_dsp;
294
295/* True if -mmt was passed or implied by arguments passed on the
296 command line (e.g., by -march). */
297static int file_ase_mt;
298
228/* The argument of the -march= flag. The architecture we are assembling. */
229static int file_mips_arch = CPU_UNKNOWN;
230static const char *mips_arch_string;
231
232/* The argument of the -mtune= flag. The architecture for which we
233 are optimizing. */
234static int mips_tune = CPU_UNKNOWN;
235static const char *mips_tune_string;

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263
264/* Return true if ISA supports 32-bit right rotate (ror et al.)
265 instructions. */
266#define ISA_HAS_ROR(ISA) ( \
267 (ISA) == ISA_MIPS32R2 \
268 || (ISA) == ISA_MIPS64R2 \
269 )
270
299/* The argument of the -march= flag. The architecture we are assembling. */
300static int file_mips_arch = CPU_UNKNOWN;
301static const char *mips_arch_string;
302
303/* The argument of the -mtune= flag. The architecture for which we
304 are optimizing. */
305static int mips_tune = CPU_UNKNOWN;
306static const char *mips_tune_string;

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334
335/* Return true if ISA supports 32-bit right rotate (ror et al.)
336 instructions. */
337#define ISA_HAS_ROR(ISA) ( \
338 (ISA) == ISA_MIPS32R2 \
339 || (ISA) == ISA_MIPS64R2 \
340 )
341
342/* Return true if ISA supports ins instructions. */
343#define ISA_HAS_INS(ISA) ( \
344 (ISA) == ISA_MIPS32R2 \
345 || (ISA) == ISA_MIPS64R2 \
346 )
347
271#define HAVE_32BIT_GPRS \
272 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
273
274#define HAVE_32BIT_FPRS \
275 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
276
277#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
278#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
279
280#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
281
282#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
283
284/* True if relocations are stored in-place. */
285#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
286
348#define HAVE_32BIT_GPRS \
349 (mips_opts.gp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
350
351#define HAVE_32BIT_FPRS \
352 (mips_opts.fp32 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
353
354#define HAVE_64BIT_GPRS (! HAVE_32BIT_GPRS)
355#define HAVE_64BIT_FPRS (! HAVE_32BIT_FPRS)
356
357#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI)
358
359#define HAVE_64BIT_OBJECTS (mips_abi == N64_ABI)
360
361/* True if relocations are stored in-place. */
362#define HAVE_IN_PLACE_ADDENDS (!HAVE_NEWABI)
363
287/* We can only have 64bit addresses if the object file format
288 supports it. */
289#define HAVE_32BIT_ADDRESSES \
290 (HAVE_32BIT_GPRS \
291 || ((bfd_arch_bits_per_address (stdoutput) == 32 \
292 || ! HAVE_64BIT_OBJECTS) \
293 && mips_pic != EMBEDDED_PIC))
364/* The ABI-derived address size. */
365#define HAVE_64BIT_ADDRESSES \
366 (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI))
367#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES)
294
368
295#define HAVE_64BIT_ADDRESSES (! HAVE_32BIT_ADDRESSES)
369/* The size of symbolic constants (i.e., expressions of the form
370 "SYMBOL" or "SYMBOL + OFFSET"). */
371#define HAVE_32BIT_SYMBOLS \
372 (HAVE_32BIT_ADDRESSES || !HAVE_64BIT_OBJECTS || mips_opts.sym32)
373#define HAVE_64BIT_SYMBOLS (!HAVE_32BIT_SYMBOLS)
296
297/* Addresses are loaded in different ways, depending on the address size
298 in use. The n32 ABI Documentation also mandates the use of additions
299 with overflow checking, but existing implementations don't follow it. */
300#define ADDRESS_ADD_INSN \
301 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
302
303#define ADDRESS_ADDI_INSN \

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317/* Return true if the given CPU supports the MIPS3D ASE. */
318#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
319 )
320
321/* Return true if the given CPU supports the MDMX ASE. */
322#define CPU_HAS_MDMX(cpu) (FALSE \
323 )
324
374
375/* Addresses are loaded in different ways, depending on the address size
376 in use. The n32 ABI Documentation also mandates the use of additions
377 with overflow checking, but existing implementations don't follow it. */
378#define ADDRESS_ADD_INSN \
379 (HAVE_32BIT_ADDRESSES ? "addu" : "daddu")
380
381#define ADDRESS_ADDI_INSN \

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395/* Return true if the given CPU supports the MIPS3D ASE. */
396#define CPU_HAS_MIPS3D(cpu) ((cpu) == CPU_SB1 \
397 )
398
399/* Return true if the given CPU supports the MDMX ASE. */
400#define CPU_HAS_MDMX(cpu) (FALSE \
401 )
402
403/* Return true if the given CPU supports the DSP ASE. */
404#define CPU_HAS_DSP(cpu) (FALSE \
405 )
406
407/* Return true if the given CPU supports the MT ASE. */
408#define CPU_HAS_MT(cpu) (FALSE \
409 )
410
325/* True if CPU has a dror instruction. */
326#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
327
328/* True if CPU has a ror instruction. */
329#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
330
331/* True if mflo and mfhi can be immediately followed by instructions
332 which write to the HI and LO registers.

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344 (mips_opts.isa == ISA_MIPS32 \
345 || mips_opts.isa == ISA_MIPS32R2 \
346 || mips_opts.isa == ISA_MIPS64 \
347 || mips_opts.isa == ISA_MIPS64R2 \
348 || mips_opts.arch == CPU_R4010 \
349 || mips_opts.arch == CPU_R10000 \
350 || mips_opts.arch == CPU_R12000 \
351 || mips_opts.arch == CPU_RM7000 \
411/* True if CPU has a dror instruction. */
412#define CPU_HAS_DROR(CPU) ((CPU) == CPU_VR5400 || (CPU) == CPU_VR5500)
413
414/* True if CPU has a ror instruction. */
415#define CPU_HAS_ROR(CPU) CPU_HAS_DROR (CPU)
416
417/* True if mflo and mfhi can be immediately followed by instructions
418 which write to the HI and LO registers.

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430 (mips_opts.isa == ISA_MIPS32 \
431 || mips_opts.isa == ISA_MIPS32R2 \
432 || mips_opts.isa == ISA_MIPS64 \
433 || mips_opts.isa == ISA_MIPS64R2 \
434 || mips_opts.arch == CPU_R4010 \
435 || mips_opts.arch == CPU_R10000 \
436 || mips_opts.arch == CPU_R12000 \
437 || mips_opts.arch == CPU_RM7000 \
352 || mips_opts.arch == CPU_SB1 \
353 || mips_opts.arch == CPU_VR5500 \
354 )
355
356/* Whether the processor uses hardware interlocks to protect reads
357 from the GPRs after they are loaded from memory, and thus does not
358 require nops to be inserted. This applies to instructions marked
359 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
360 level I. */
361#define gpr_interlocks \
362 (mips_opts.isa != ISA_MIPS1 \
438 || mips_opts.arch == CPU_VR5500 \
439 )
440
441/* Whether the processor uses hardware interlocks to protect reads
442 from the GPRs after they are loaded from memory, and thus does not
443 require nops to be inserted. This applies to instructions marked
444 INSN_LOAD_MEMORY_DELAY. These nops are only required at MIPS ISA
445 level I. */
446#define gpr_interlocks \
447 (mips_opts.isa != ISA_MIPS1 \
363 || mips_opts.arch == CPU_VR5400 \
364 || mips_opts.arch == CPU_VR5500 \
365 || mips_opts.arch == CPU_R3900)
366
367/* Whether the processor uses hardware interlocks to avoid delays
368 required by coprocessor instructions, and thus does not require
369 nops to be inserted. This applies to instructions marked
370 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
371 between instructions marked INSN_WRITE_COND_CODE and ones marked
372 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
373 levels I, II, and III. */
374/* Itbl support may require additional care here. */
375#define cop_interlocks \
376 ((mips_opts.isa != ISA_MIPS1 \
377 && mips_opts.isa != ISA_MIPS2 \
378 && mips_opts.isa != ISA_MIPS3) \
379 || mips_opts.arch == CPU_R4300 \
448 || mips_opts.arch == CPU_R3900)
449
450/* Whether the processor uses hardware interlocks to avoid delays
451 required by coprocessor instructions, and thus does not require
452 nops to be inserted. This applies to instructions marked
453 INSN_LOAD_COPROC_DELAY, INSN_COPROC_MOVE_DELAY, and to delays
454 between instructions marked INSN_WRITE_COND_CODE and ones marked
455 INSN_READ_COND_CODE. These nops are only required at MIPS ISA
456 levels I, II, and III. */
457/* Itbl support may require additional care here. */
458#define cop_interlocks \
459 ((mips_opts.isa != ISA_MIPS1 \
460 && mips_opts.isa != ISA_MIPS2 \
461 && mips_opts.isa != ISA_MIPS3) \
462 || mips_opts.arch == CPU_R4300 \
380 || mips_opts.arch == CPU_VR5400 \
381 || mips_opts.arch == CPU_VR5500 \
382 || mips_opts.arch == CPU_SB1 \
383 )
384
385/* Whether the processor uses hardware interlocks to protect reads
386 from coprocessor registers after they are loaded from memory, and
387 thus does not require nops to be inserted. This applies to
388 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
389 requires at MIPS ISA level I. */
390#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)

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516 of 1 means to not swap branches. A value of 0 means to always
517 insert NOPs. */
518static int mips_optimize = 2;
519
520/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
521 equivalent to seeing no -g option at all. */
522static int mips_debug = 0;
523
463 )
464
465/* Whether the processor uses hardware interlocks to protect reads
466 from coprocessor registers after they are loaded from memory, and
467 thus does not require nops to be inserted. This applies to
468 instructions marked INSN_COPROC_MEMORY_DELAY. These nops are only
469 requires at MIPS ISA level I. */
470#define cop_mem_interlocks (mips_opts.isa != ISA_MIPS1)

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596 of 1 means to not swap branches. A value of 0 means to always
597 insert NOPs. */
598static int mips_optimize = 2;
599
600/* Debugging level. -g sets this to 2. -gN sets this to N. -g0 is
601 equivalent to seeing no -g option at all. */
602static int mips_debug = 0;
603
524/* The previous instruction. */
525static struct mips_cl_insn prev_insn;
604/* The maximum number of NOPs needed to avoid the VR4130 mflo/mfhi errata. */
605#define MAX_VR4130_NOPS 4
526
606
527/* The instruction before prev_insn. */
528static struct mips_cl_insn prev_prev_insn;
607/* The maximum number of NOPs needed to fill delay slots. */
608#define MAX_DELAY_NOPS 2
529
609
530/* If we don't want information for prev_insn or prev_prev_insn, we
531 point the insn_mo field at this dummy integer. */
532static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0 };
610/* The maximum number of NOPs needed for any purpose. */
611#define MAX_NOPS 4
533
612
534/* Non-zero if prev_insn is valid. */
535static int prev_insn_valid;
613/* A list of previous instructions, with index 0 being the most recent.
614 We need to look back MAX_NOPS instructions when filling delay slots
615 or working around processor errata. We need to look back one
616 instruction further if we're thinking about using history[0] to
617 fill a branch delay slot. */
618static struct mips_cl_insn history[1 + MAX_NOPS];
536
619
537/* The frag for the previous instruction. */
538static struct frag *prev_insn_frag;
620/* Nop instructions used by emit_nop. */
621static struct mips_cl_insn nop_insn, mips16_nop_insn;
539
622
540/* The offset into prev_insn_frag for the previous instruction. */
541static long prev_insn_where;
623/* The appropriate nop for the current mode. */
624#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
542
625
543/* The reloc type for the previous instruction, if any. */
544static bfd_reloc_code_real_type prev_insn_reloc_type[3];
545
546/* The reloc for the previous instruction, if any. */
547static fixS *prev_insn_fixp[3];
548
549/* Non-zero if the previous instruction was in a delay slot. */
550static int prev_insn_is_delay_slot;
551
552/* Non-zero if the previous instruction was in a .set noreorder. */
553static int prev_insn_unreordered;
554
555/* Non-zero if the previous instruction uses an extend opcode (if
556 mips16). */
557static int prev_insn_extended;
558
559/* Non-zero if the previous previous instruction was in a .set
560 noreorder. */
561static int prev_prev_insn_unreordered;
562
563/* If this is set, it points to a frag holding nop instructions which
564 were inserted before the start of a noreorder section. If those
565 nops turn out to be unnecessary, the size of the frag can be
566 decreased. */
567static fragS *prev_nop_frag;
568
569/* The number of nop instructions we created in prev_nop_frag. */
570static int prev_nop_frag_holds;

--- 49 unchanged lines hidden (view full) ---

620
621/* Map mips16 register numbers to normal MIPS register numbers. */
622
623static const unsigned int mips16_to_32_reg_map[] =
624{
625 16, 17, 2, 3, 4, 5, 6, 7
626};
627
626/* If this is set, it points to a frag holding nop instructions which
627 were inserted before the start of a noreorder section. If those
628 nops turn out to be unnecessary, the size of the frag can be
629 decreased. */
630static fragS *prev_nop_frag;
631
632/* The number of nop instructions we created in prev_nop_frag. */
633static int prev_nop_frag_holds;

--- 49 unchanged lines hidden (view full) ---

683
684/* Map mips16 register numbers to normal MIPS register numbers. */
685
686static const unsigned int mips16_to_32_reg_map[] =
687{
688 16, 17, 2, 3, 4, 5, 6, 7
689};
690
691/* Classifies the kind of instructions we're interested in when
692 implementing -mfix-vr4120. */
693enum fix_vr4120_class {
694 FIX_VR4120_MACC,
695 FIX_VR4120_DMACC,
696 FIX_VR4120_MULT,
697 FIX_VR4120_DMULT,
698 FIX_VR4120_DIV,
699 FIX_VR4120_MTHILO,
700 NUM_FIX_VR4120_CLASSES
701};
702
703/* Given two FIX_VR4120_* values X and Y, bit Y of element X is set if
704 there must be at least one other instruction between an instruction
705 of type X and an instruction of type Y. */
706static unsigned int vr4120_conflicts[NUM_FIX_VR4120_CLASSES];
707
708/* True if -mfix-vr4120 is in force. */
628static int mips_fix_vr4120;
629
709static int mips_fix_vr4120;
710
711/* ...likewise -mfix-vr4130. */
712static int mips_fix_vr4130;
713
630/* We don't relax branches by default, since this causes us to expand
631 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
632 fail to compute the offset before expanding the macro to the most
633 efficient expansion. */
634
635static int mips_relax_branch;
636
637/* The expansion of many macros depends on the type of symbol that

--- 177 unchanged lines hidden (view full) ---

815 (((x) &~ (offsetT) 0x7fffffff) == 0 \
816 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
817
818/* Is the given value a sign-extended 16-bit value? */
819#define IS_SEXT_16BIT_NUM(x) \
820 (((x) &~ (offsetT) 0x7fff) == 0 \
821 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
822
714/* We don't relax branches by default, since this causes us to expand
715 `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
716 fail to compute the offset before expanding the macro to the most
717 efficient expansion. */
718
719static int mips_relax_branch;
720
721/* The expansion of many macros depends on the type of symbol that

--- 177 unchanged lines hidden (view full) ---

899 (((x) &~ (offsetT) 0x7fffffff) == 0 \
900 || (((x) &~ (offsetT) 0x7fffffff) == ~ (offsetT) 0x7fffffff))
901
902/* Is the given value a sign-extended 16-bit value? */
903#define IS_SEXT_16BIT_NUM(x) \
904 (((x) &~ (offsetT) 0x7fff) == 0 \
905 || (((x) &~ (offsetT) 0x7fff) == ~ (offsetT) 0x7fff))
906
907/* Is the given value a zero-extended 32-bit value? Or a negated one? */
908#define IS_ZEXT_32BIT_NUM(x) \
909 (((x) &~ (offsetT) 0xffffffff) == 0 \
910 || (((x) &~ (offsetT) 0xffffffff) == ~ (offsetT) 0xffffffff))
911
912/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
913 VALUE << SHIFT. VALUE is evaluated exactly once. */
914#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
915 (STRUCT) = (((STRUCT) & ~((MASK) << (SHIFT))) \
916 | (((VALUE) & (MASK)) << (SHIFT)))
917
918/* Extract bits MASK << SHIFT from STRUCT and shift them right
919 SHIFT places. */
920#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
921 (((STRUCT) >> (SHIFT)) & (MASK))
922
923/* Change INSN's opcode so that the operand given by FIELD has value VALUE.
924 INSN is a mips_cl_insn structure and VALUE is evaluated exactly once.
925
926 include/opcode/mips.h specifies operand fields using the macros
927 OP_MASK_<FIELD> and OP_SH_<FIELD>. The MIPS16 equivalents start
928 with "MIPS16OP" instead of "OP". */
929#define INSERT_OPERAND(FIELD, INSN, VALUE) \
930 INSERT_BITS ((INSN).insn_opcode, VALUE, OP_MASK_##FIELD, OP_SH_##FIELD)
931#define MIPS16_INSERT_OPERAND(FIELD, INSN, VALUE) \
932 INSERT_BITS ((INSN).insn_opcode, VALUE, \
933 MIPS16OP_MASK_##FIELD, MIPS16OP_SH_##FIELD)
934
935/* Extract the operand given by FIELD from mips_cl_insn INSN. */
936#define EXTRACT_OPERAND(FIELD, INSN) \
937 EXTRACT_BITS ((INSN).insn_opcode, OP_MASK_##FIELD, OP_SH_##FIELD)
938#define MIPS16_EXTRACT_OPERAND(FIELD, INSN) \
939 EXTRACT_BITS ((INSN).insn_opcode, \
940 MIPS16OP_MASK_##FIELD, \
941 MIPS16OP_SH_##FIELD)
823
824/* Global variables used when generating relaxable macros. See the
825 comment above RELAX_ENCODE for more details about how relaxation
826 is used. */
827static struct {
828 /* 0 if we're not emitting a relaxable macro.
829 1 if we're emitting the first of the two relaxation alternatives.
830 2 if we're emitting the second alternative. */

--- 30 unchanged lines hidden (view full) ---

861
862#define internalError() \
863 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
864
865enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
866
867static void append_insn
868 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
942
943/* Global variables used when generating relaxable macros. See the
944 comment above RELAX_ENCODE for more details about how relaxation
945 is used. */
946static struct {
947 /* 0 if we're not emitting a relaxable macro.
948 1 if we're emitting the first of the two relaxation alternatives.
949 2 if we're emitting the second alternative. */

--- 30 unchanged lines hidden (view full) ---

980
981#define internalError() \
982 as_fatal (_("internal Error, line %d, %s"), __LINE__, __FILE__)
983
984enum mips_regclass { MIPS_GR_REG, MIPS_FP_REG, MIPS16_REG };
985
986static void append_insn
987 (struct mips_cl_insn *ip, expressionS *p, bfd_reloc_code_real_type *r);
869static void mips_no_prev_insn (int);
988static void mips_no_prev_insn (void);
870static void mips16_macro_build
871 (expressionS *, const char *, const char *, va_list);
872static void load_register (int, expressionS *, int);
873static void macro_start (void);
874static void macro_end (void);
875static void macro (struct mips_cl_insn * ip);
876static void mips16_macro (struct mips_cl_insn * ip);
877#ifdef LOSING_COMPILER

--- 209 unchanged lines hidden (view full) ---

1087
1088/* The default target format to use. */
1089
1090const char *
1091mips_target_format (void)
1092{
1093 switch (OUTPUT_FLAVOR)
1094 {
989static void mips16_macro_build
990 (expressionS *, const char *, const char *, va_list);
991static void load_register (int, expressionS *, int);
992static void macro_start (void);
993static void macro_end (void);
994static void macro (struct mips_cl_insn * ip);
995static void mips16_macro (struct mips_cl_insn * ip);
996#ifdef LOSING_COMPILER

--- 209 unchanged lines hidden (view full) ---

1206
1207/* The default target format to use. */
1208
1209const char *
1210mips_target_format (void)
1211{
1212 switch (OUTPUT_FLAVOR)
1213 {
1095 case bfd_target_aout_flavour:
1096 return target_big_endian ? "a.out-mips-big" : "a.out-mips-little";
1097 case bfd_target_ecoff_flavour:
1098 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1099 case bfd_target_coff_flavour:
1100 return "pe-mips";
1101 case bfd_target_elf_flavour:
1102#ifdef TE_TMIPS
1103 /* This is traditional mips. */
1104 return (target_big_endian

--- 17 unchanged lines hidden (view full) ---

1122 ? "elf32-nlittlemips" : "elf32-littlemips")));
1123#endif
1124 default:
1125 abort ();
1126 return NULL;
1127 }
1128}
1129
1214 case bfd_target_ecoff_flavour:
1215 return target_big_endian ? "ecoff-bigmips" : ECOFF_LITTLE_FORMAT;
1216 case bfd_target_coff_flavour:
1217 return "pe-mips";
1218 case bfd_target_elf_flavour:
1219#ifdef TE_TMIPS
1220 /* This is traditional mips. */
1221 return (target_big_endian

--- 17 unchanged lines hidden (view full) ---

1239 ? "elf32-nlittlemips" : "elf32-littlemips")));
1240#endif
1241 default:
1242 abort ();
1243 return NULL;
1244 }
1245}
1246
1247/* Return the length of instruction INSN. */
1248
1249static inline unsigned int
1250insn_length (const struct mips_cl_insn *insn)
1251{
1252 if (!mips_opts.mips16)
1253 return 4;
1254 return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
1255}
1256
1257/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
1258
1259static void
1260create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
1261{
1262 size_t i;
1263
1264 insn->insn_mo = mo;
1265 insn->use_extend = FALSE;
1266 insn->extend = 0;
1267 insn->insn_opcode = mo->match;
1268 insn->frag = NULL;
1269 insn->where = 0;
1270 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1271 insn->fixp[i] = NULL;
1272 insn->fixed_p = (mips_opts.noreorder > 0);
1273 insn->noreorder_p = (mips_opts.noreorder > 0);
1274 insn->mips16_absolute_jump_p = 0;
1275}
1276
1277/* Install INSN at the location specified by its "frag" and "where" fields. */
1278
1279static void
1280install_insn (const struct mips_cl_insn *insn)
1281{
1282 char *f = insn->frag->fr_literal + insn->where;
1283 if (!mips_opts.mips16)
1284 md_number_to_chars (f, insn->insn_opcode, 4);
1285 else if (insn->mips16_absolute_jump_p)
1286 {
1287 md_number_to_chars (f, insn->insn_opcode >> 16, 2);
1288 md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
1289 }
1290 else
1291 {
1292 if (insn->use_extend)
1293 {
1294 md_number_to_chars (f, 0xf000 | insn->extend, 2);
1295 f += 2;
1296 }
1297 md_number_to_chars (f, insn->insn_opcode, 2);
1298 }
1299}
1300
1301/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
1302 and install the opcode in the new location. */
1303
1304static void
1305move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
1306{
1307 size_t i;
1308
1309 insn->frag = frag;
1310 insn->where = where;
1311 for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
1312 if (insn->fixp[i] != NULL)
1313 {
1314 insn->fixp[i]->fx_frag = frag;
1315 insn->fixp[i]->fx_where = where;
1316 }
1317 install_insn (insn);
1318}
1319
1320/* Add INSN to the end of the output. */
1321
1322static void
1323add_fixed_insn (struct mips_cl_insn *insn)
1324{
1325 char *f = frag_more (insn_length (insn));
1326 move_insn (insn, frag_now, f - frag_now->fr_literal);
1327}
1328
1329/* Start a variant frag and move INSN to the start of the variant part,
1330 marking it as fixed. The other arguments are as for frag_var. */
1331
1332static void
1333add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
1334 relax_substateT subtype, symbolS *symbol, offsetT offset)
1335{
1336 frag_grow (max_chars);
1337 move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
1338 insn->fixed_p = 1;
1339 frag_var (rs_machine_dependent, max_chars, var,
1340 subtype, symbol, offset, NULL);
1341}
1342
1343/* Insert N copies of INSN into the history buffer, starting at
1344 position FIRST. Neither FIRST nor N need to be clipped. */
1345
1346static void
1347insert_into_history (unsigned int first, unsigned int n,
1348 const struct mips_cl_insn *insn)
1349{
1350 if (mips_relax.sequence != 2)
1351 {
1352 unsigned int i;
1353
1354 for (i = ARRAY_SIZE (history); i-- > first;)
1355 if (i >= first + n)
1356 history[i] = history[i - n];
1357 else
1358 history[i] = *insn;
1359 }
1360}
1361
1362/* Emit a nop instruction, recording it in the history buffer. */
1363
1364static void
1365emit_nop (void)
1366{
1367 add_fixed_insn (NOP_INSN);
1368 insert_into_history (0, 1, NOP_INSN);
1369}
1370
1371/* Initialize vr4120_conflicts. There is a bit of duplication here:
1372 the idea is to make it obvious at a glance that each errata is
1373 included. */
1374
1375static void
1376init_vr4120_conflicts (void)
1377{
1378#define CONFLICT(FIRST, SECOND) \
1379 vr4120_conflicts[FIX_VR4120_##FIRST] |= 1 << FIX_VR4120_##SECOND
1380
1381 /* Errata 21 - [D]DIV[U] after [D]MACC */
1382 CONFLICT (MACC, DIV);
1383 CONFLICT (DMACC, DIV);
1384
1385 /* Errata 23 - Continuous DMULT[U]/DMACC instructions. */
1386 CONFLICT (DMULT, DMULT);
1387 CONFLICT (DMULT, DMACC);
1388 CONFLICT (DMACC, DMULT);
1389 CONFLICT (DMACC, DMACC);
1390
1391 /* Errata 24 - MT{LO,HI} after [D]MACC */
1392 CONFLICT (MACC, MTHILO);
1393 CONFLICT (DMACC, MTHILO);
1394
1395 /* VR4181A errata MD(1): "If a MULT, MULTU, DMULT or DMULTU
1396 instruction is executed immediately after a MACC or DMACC
1397 instruction, the result of [either instruction] is incorrect." */
1398 CONFLICT (MACC, MULT);
1399 CONFLICT (MACC, DMULT);
1400 CONFLICT (DMACC, MULT);
1401 CONFLICT (DMACC, DMULT);
1402
1403 /* VR4181A errata MD(4): "If a MACC or DMACC instruction is
1404 executed immediately after a DMULT, DMULTU, DIV, DIVU,
1405 DDIV or DDIVU instruction, the result of the MACC or
1406 DMACC instruction is incorrect.". */
1407 CONFLICT (DMULT, MACC);
1408 CONFLICT (DMULT, DMACC);
1409 CONFLICT (DIV, MACC);
1410 CONFLICT (DIV, DMACC);
1411
1412#undef CONFLICT
1413}
1414
1130/* This function is called once, at assembler startup time. It should
1131 set up all the tables, etc. that the MD part of the assembler will need. */
1132
1133void
1134md_begin (void)
1135{
1136 register const char *retval = NULL;
1137 int i = 0;
1138 int broken = 0;
1139
1415/* This function is called once, at assembler startup time. It should
1416 set up all the tables, etc. that the MD part of the assembler will need. */
1417
1418void
1419md_begin (void)
1420{
1421 register const char *retval = NULL;
1422 int i = 0;
1423 int broken = 0;
1424
1425 if (mips_pic != NO_PIC)
1426 {
1427 if (g_switch_seen && g_switch_value != 0)
1428 as_bad (_("-G may not be used in position-independent code"));
1429 g_switch_value = 0;
1430 }
1431
1140 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1141 as_warn (_("Could not set architecture and machine"));
1142
1143 op_hash = hash_new ();
1144
1145 for (i = 0; i < NUMOPCODES;)
1146 {
1147 const char *name = mips_opcodes[i].name;

--- 7 unchanged lines hidden (view full) ---

1155 as_fatal (_("Broken assembler. No assembly attempted."));
1156 }
1157 do
1158 {
1159 if (mips_opcodes[i].pinfo != INSN_MACRO)
1160 {
1161 if (!validate_mips_insn (&mips_opcodes[i]))
1162 broken = 1;
1432 if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
1433 as_warn (_("Could not set architecture and machine"));
1434
1435 op_hash = hash_new ();
1436
1437 for (i = 0; i < NUMOPCODES;)
1438 {
1439 const char *name = mips_opcodes[i].name;

--- 7 unchanged lines hidden (view full) ---

1447 as_fatal (_("Broken assembler. No assembly attempted."));
1448 }
1449 do
1450 {
1451 if (mips_opcodes[i].pinfo != INSN_MACRO)
1452 {
1453 if (!validate_mips_insn (&mips_opcodes[i]))
1454 broken = 1;
1455 if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1456 {
1457 create_insn (&nop_insn, mips_opcodes + i);
1458 nop_insn.fixed_p = 1;
1459 }
1163 }
1164 ++i;
1165 }
1166 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1167 }
1168
1169 mips16_op_hash = hash_new ();
1170

--- 11 unchanged lines hidden (view full) ---

1182 if (mips16_opcodes[i].pinfo != INSN_MACRO
1183 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1184 != mips16_opcodes[i].match))
1185 {
1186 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1187 mips16_opcodes[i].name, mips16_opcodes[i].args);
1188 broken = 1;
1189 }
1460 }
1461 ++i;
1462 }
1463 while ((i < NUMOPCODES) && !strcmp (mips_opcodes[i].name, name));
1464 }
1465
1466 mips16_op_hash = hash_new ();
1467

--- 11 unchanged lines hidden (view full) ---

1479 if (mips16_opcodes[i].pinfo != INSN_MACRO
1480 && ((mips16_opcodes[i].match & mips16_opcodes[i].mask)
1481 != mips16_opcodes[i].match))
1482 {
1483 fprintf (stderr, _("internal error: bad mips16 opcode: %s %s\n"),
1484 mips16_opcodes[i].name, mips16_opcodes[i].args);
1485 broken = 1;
1486 }
1487 if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
1488 {
1489 create_insn (&mips16_nop_insn, mips16_opcodes + i);
1490 mips16_nop_insn.fixed_p = 1;
1491 }
1190 ++i;
1191 }
1192 while (i < bfd_mips16_num_opcodes
1193 && strcmp (mips16_opcodes[i].name, name) == 0);
1194 }
1195
1196 if (broken)
1197 as_fatal (_("Broken assembler. No assembly attempted."));

--- 36 unchanged lines hidden (view full) ---

1234 {
1235 char buf[6];
1236
1237 sprintf (buf, "$fcc%i", i);
1238 symbol_table_insert (symbol_new (buf, reg_section, -1,
1239 &zero_address_frag));
1240 }
1241
1492 ++i;
1493 }
1494 while (i < bfd_mips16_num_opcodes
1495 && strcmp (mips16_opcodes[i].name, name) == 0);
1496 }
1497
1498 if (broken)
1499 as_fatal (_("Broken assembler. No assembly attempted."));

--- 36 unchanged lines hidden (view full) ---

1536 {
1537 char buf[6];
1538
1539 sprintf (buf, "$fcc%i", i);
1540 symbol_table_insert (symbol_new (buf, reg_section, -1,
1541 &zero_address_frag));
1542 }
1543
1242 mips_no_prev_insn (FALSE);
1544 mips_no_prev_insn ();
1243
1244 mips_gprmask = 0;
1245 mips_cprmask[0] = 0;
1246 mips_cprmask[1] = 0;
1247 mips_cprmask[2] = 0;
1248 mips_cprmask[3] = 0;
1249
1250 /* set the default alignment for the text section (2**2) */
1251 record_alignment (text_section, 2);
1252
1545
1546 mips_gprmask = 0;
1547 mips_cprmask[0] = 0;
1548 mips_cprmask[1] = 0;
1549 mips_cprmask[2] = 0;
1550 mips_cprmask[3] = 0;
1551
1552 /* set the default alignment for the text section (2**2) */
1553 record_alignment (text_section, 2);
1554
1253 if (USE_GLOBAL_POINTER_OPT)
1254 bfd_set_gp_size (stdoutput, g_switch_value);
1555 bfd_set_gp_size (stdoutput, g_switch_value);
1255
1256 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1257 {
1258 /* On a native system, sections must be aligned to 16 byte
1556
1557 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
1558 {
1559 /* On a native system, sections must be aligned to 16 byte
1259 boundaries. When configured for an embedded ELF target, we
1560 boundaries. When configured for an embedded ELF target, we
1260 don't bother. */
1561 don't bother. */
1261 if (strcmp (TARGET_OS, "elf") != 0)
1562 if (strcmp (TARGET_OS, "elf") != 0
1563 && strcmp (TARGET_OS, "vxworks") != 0)
1262 {
1263 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1264 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1265 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1266 }
1267
1268 /* Create a .reginfo section for register masks and a .mdebug
1269 section for debugging information. */

--- 71 unchanged lines hidden (view full) ---

1341#endif
1342
1343 subseg_set (seg, subseg);
1344 }
1345 }
1346
1347 if (! ECOFF_DEBUGGING)
1348 md_obj_begin ();
1564 {
1565 (void) bfd_set_section_alignment (stdoutput, text_section, 4);
1566 (void) bfd_set_section_alignment (stdoutput, data_section, 4);
1567 (void) bfd_set_section_alignment (stdoutput, bss_section, 4);
1568 }
1569
1570 /* Create a .reginfo section for register masks and a .mdebug
1571 section for debugging information. */

--- 71 unchanged lines hidden (view full) ---

1643#endif
1644
1645 subseg_set (seg, subseg);
1646 }
1647 }
1648
1649 if (! ECOFF_DEBUGGING)
1650 md_obj_begin ();
1651
1652 if (mips_fix_vr4120)
1653 init_vr4120_conflicts ();
1349}
1350
1351void
1352md_mips_end (void)
1353{
1354 if (! ECOFF_DEBUGGING)
1355 md_obj_end ();
1356}

--- 46 unchanged lines hidden (view full) ---

1403 else if (offset_expr.X_op != O_absent)
1404 append_insn (&insn, &offset_expr, offset_reloc);
1405 else
1406 append_insn (&insn, NULL, unused_reloc);
1407 }
1408}
1409
1410/* Return true if the given relocation might need a matching %lo().
1654}
1655
1656void
1657md_mips_end (void)
1658{
1659 if (! ECOFF_DEBUGGING)
1660 md_obj_end ();
1661}

--- 46 unchanged lines hidden (view full) ---

1708 else if (offset_expr.X_op != O_absent)
1709 append_insn (&insn, &offset_expr, offset_reloc);
1710 else
1711 append_insn (&insn, NULL, unused_reloc);
1712 }
1713}
1714
1715/* Return true if the given relocation might need a matching %lo().
1411 Note that R_MIPS_GOT16 relocations only need a matching %lo() when
1412 applied to local symbols. */
1716 This is only "might" because SVR4 R_MIPS_GOT16 relocations only
1717 need a matching %lo() when applied to local symbols. */
1413
1414static inline bfd_boolean
1415reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1416{
1417 return (reloc == BFD_RELOC_HI16_S
1418 || reloc == BFD_RELOC_MIPS_GOT16);
1419}
1420

--- 8 unchanged lines hidden (view full) ---

1429 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1430 && fixp->fx_offset == fixp->fx_next->fx_offset);
1431}
1432
1433/* See whether instruction IP reads register REG. CLASS is the type
1434 of register. */
1435
1436static int
1718
1719static inline bfd_boolean
1720reloc_needs_lo_p (bfd_reloc_code_real_type reloc)
1721{
1722 return (reloc == BFD_RELOC_HI16_S
1723 || reloc == BFD_RELOC_MIPS_GOT16);
1724}
1725

--- 8 unchanged lines hidden (view full) ---

1734 && fixp->fx_addsy == fixp->fx_next->fx_addsy
1735 && fixp->fx_offset == fixp->fx_next->fx_offset);
1736}
1737
1738/* See whether instruction IP reads register REG. CLASS is the type
1739 of register. */
1740
1741static int
1437insn_uses_reg (struct mips_cl_insn *ip, unsigned int reg,
1742insn_uses_reg (const struct mips_cl_insn *ip, unsigned int reg,
1438 enum mips_regclass class)
1439{
1440 if (class == MIPS16_REG)
1441 {
1442 assert (mips_opts.mips16);
1443 reg = mips16_to_32_reg_map[reg];
1444 class = MIPS_GR_REG;
1445 }

--- 8 unchanged lines hidden (view full) ---

1454 /* If we are called with either $f0 or $f1, we must check $f0.
1455 This is not optimal, because it will introduce an unnecessary
1456 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1457 need to distinguish reading both $f0 and $f1 or just one of
1458 them. Note that we don't have to check the other way,
1459 because there is no instruction that sets both $f0 and $f1
1460 and requires a delay. */
1461 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1743 enum mips_regclass class)
1744{
1745 if (class == MIPS16_REG)
1746 {
1747 assert (mips_opts.mips16);
1748 reg = mips16_to_32_reg_map[reg];
1749 class = MIPS_GR_REG;
1750 }

--- 8 unchanged lines hidden (view full) ---

1759 /* If we are called with either $f0 or $f1, we must check $f0.
1760 This is not optimal, because it will introduce an unnecessary
1761 NOP between "lwc1 $f0" and "swc1 $f1". To fix this we would
1762 need to distinguish reading both $f0 and $f1 or just one of
1763 them. Note that we don't have to check the other way,
1764 because there is no instruction that sets both $f0 and $f1
1765 and requires a delay. */
1766 if ((ip->insn_mo->pinfo & INSN_READ_FPR_S)
1462 && ((((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS) &~(unsigned)1)
1767 && ((EXTRACT_OPERAND (FS, *ip) & ~(unsigned) 1)
1463 == (reg &~ (unsigned) 1)))
1464 return 1;
1465 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1768 == (reg &~ (unsigned) 1)))
1769 return 1;
1770 if ((ip->insn_mo->pinfo & INSN_READ_FPR_T)
1466 && ((((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT) &~(unsigned)1)
1771 && ((EXTRACT_OPERAND (FT, *ip) & ~(unsigned) 1)
1467 == (reg &~ (unsigned) 1)))
1468 return 1;
1469 }
1470 else if (! mips_opts.mips16)
1471 {
1472 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1772 == (reg &~ (unsigned) 1)))
1773 return 1;
1774 }
1775 else if (! mips_opts.mips16)
1776 {
1777 if ((ip->insn_mo->pinfo & INSN_READ_GPR_S)
1473 && ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS) == reg)
1778 && EXTRACT_OPERAND (RS, *ip) == reg)
1474 return 1;
1475 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1779 return 1;
1780 if ((ip->insn_mo->pinfo & INSN_READ_GPR_T)
1476 && ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT) == reg)
1781 && EXTRACT_OPERAND (RT, *ip) == reg)
1477 return 1;
1478 }
1479 else
1480 {
1481 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1782 return 1;
1783 }
1784 else
1785 {
1786 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_X)
1482 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RX)
1483 & MIPS16OP_MASK_RX)]
1484 == reg))
1787 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, *ip)] == reg)
1485 return 1;
1486 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1788 return 1;
1789 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Y)
1487 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_RY)
1488 & MIPS16OP_MASK_RY)]
1489 == reg))
1790 && mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RY, *ip)] == reg)
1490 return 1;
1491 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1791 return 1;
1792 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_Z)
1492 && (mips16_to_32_reg_map[((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
1493 & MIPS16OP_MASK_MOVE32Z)]
1793 && (mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]
1494 == reg))
1495 return 1;
1496 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1497 return 1;
1498 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1499 return 1;
1500 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1501 return 1;
1502 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1794 == reg))
1795 return 1;
1796 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_T) && reg == TREG)
1797 return 1;
1798 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_SP) && reg == SP)
1799 return 1;
1800 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_31) && reg == RA)
1801 return 1;
1802 if ((ip->insn_mo->pinfo & MIPS16_INSN_READ_GPR_X)
1503 && ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
1504 & MIPS16OP_MASK_REGR32) == reg)
1803 && MIPS16_EXTRACT_OPERAND (REGR32, *ip) == reg)
1505 return 1;
1506 }
1507
1508 return 0;
1509}
1510
1511/* This function returns true if modifying a register requires a
1512 delay. */
1513
1514static int
1515reg_needs_delay (unsigned int reg)
1516{
1517 unsigned long prev_pinfo;
1518
1804 return 1;
1805 }
1806
1807 return 0;
1808}
1809
1810/* This function returns true if modifying a register requires a
1811 delay. */
1812
1813static int
1814reg_needs_delay (unsigned int reg)
1815{
1816 unsigned long prev_pinfo;
1817
1519 prev_pinfo = prev_insn.insn_mo->pinfo;
1818 prev_pinfo = history[0].insn_mo->pinfo;
1520 if (! mips_opts.noreorder
1521 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1522 && ! gpr_interlocks)
1523 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1524 && ! cop_interlocks)))
1525 {
1526 /* A load from a coprocessor or from memory. All load delays
1527 delay the use of general register rt for one instruction. */
1528 /* Itbl support may require additional care here. */
1529 know (prev_pinfo & INSN_WRITE_GPR_T);
1819 if (! mips_opts.noreorder
1820 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1821 && ! gpr_interlocks)
1822 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1823 && ! cop_interlocks)))
1824 {
1825 /* A load from a coprocessor or from memory. All load delays
1826 delay the use of general register rt for one instruction. */
1827 /* Itbl support may require additional care here. */
1828 know (prev_pinfo & INSN_WRITE_GPR_T);
1530 if (reg == ((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT))
1829 if (reg == EXTRACT_OPERAND (RT, history[0]))
1531 return 1;
1532 }
1533
1534 return 0;
1535}
1536
1830 return 1;
1831 }
1832
1833 return 0;
1834}
1835
1836/* Move all labels in insn_labels to the current insertion point. */
1837
1838static void
1839mips_move_labels (void)
1840{
1841 struct insn_label_list *l;
1842 valueT val;
1843
1844 for (l = insn_labels; l != NULL; l = l->next)
1845 {
1846 assert (S_GET_SEGMENT (l->label) == now_seg);
1847 symbol_set_frag (l->label, frag_now);
1848 val = (valueT) frag_now_fix ();
1849 /* mips16 text labels are stored as odd. */
1850 if (mips_opts.mips16)
1851 ++val;
1852 S_SET_VALUE (l->label, val);
1853 }
1854}
1855
1537/* Mark instruction labels in mips16 mode. This permits the linker to
1538 handle them specially, such as generating jalx instructions when
1539 needed. We also make them odd for the duration of the assembly, in
1540 order to generate the right sort of code. We will make them even
1541 in the adjust_symtab routine, while leaving them marked. This is
1542 convenient for the debugger and the disassembler. The linker knows
1543 to make them odd again. */
1544

--- 59 unchanged lines hidden (view full) ---

1604static void
1605relax_end (void)
1606{
1607 assert (mips_relax.sequence == 2);
1608 relax_close_frag ();
1609 mips_relax.sequence = 0;
1610}
1611
1856/* Mark instruction labels in mips16 mode. This permits the linker to
1857 handle them specially, such as generating jalx instructions when
1858 needed. We also make them odd for the duration of the assembly, in
1859 order to generate the right sort of code. We will make them even
1860 in the adjust_symtab routine, while leaving them marked. This is
1861 convenient for the debugger and the disassembler. The linker knows
1862 to make them odd again. */
1863

--- 59 unchanged lines hidden (view full) ---

1923static void
1924relax_end (void)
1925{
1926 assert (mips_relax.sequence == 2);
1927 relax_close_frag ();
1928 mips_relax.sequence = 0;
1929}
1930
1612/* Output an instruction. IP is the instruction information.
1613 ADDRESS_EXPR is an operand of the instruction to be used with
1614 RELOC_TYPE. */
1931/* Classify an instruction according to the FIX_VR4120_* enumeration.
1932 Return NUM_FIX_VR4120_CLASSES if the instruction isn't affected
1933 by VR4120 errata. */
1615
1934
1616static void
1617append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
1618 bfd_reloc_code_real_type *reloc_type)
1935static unsigned int
1936classify_vr4120_insn (const char *name)
1619{
1937{
1620 register unsigned long prev_pinfo, pinfo;
1621 char *f;
1622 fixS *fixp[3];
1623 int nops = 0;
1624 relax_stateT prev_insn_frag_type = 0;
1625 bfd_boolean relaxed_branch = FALSE;
1626 bfd_boolean force_new_frag = FALSE;
1938 if (strncmp (name, "macc", 4) == 0)
1939 return FIX_VR4120_MACC;
1940 if (strncmp (name, "dmacc", 5) == 0)
1941 return FIX_VR4120_DMACC;
1942 if (strncmp (name, "mult", 4) == 0)
1943 return FIX_VR4120_MULT;
1944 if (strncmp (name, "dmult", 5) == 0)
1945 return FIX_VR4120_DMULT;
1946 if (strstr (name, "div"))
1947 return FIX_VR4120_DIV;
1948 if (strcmp (name, "mtlo") == 0 || strcmp (name, "mthi") == 0)
1949 return FIX_VR4120_MTHILO;
1950 return NUM_FIX_VR4120_CLASSES;
1951}
1627
1952
1628 /* Mark instruction labels in mips16 mode. */
1629 mips16_mark_labels ();
1953/* Return the number of instructions that must separate INSN1 and INSN2,
1954 where INSN1 is the earlier instruction. Return the worst-case value
1955 for any INSN2 if INSN2 is null. */
1630
1956
1631 prev_pinfo = prev_insn.insn_mo->pinfo;
1632 pinfo = ip->insn_mo->pinfo;
1957static unsigned int
1958insns_between (const struct mips_cl_insn *insn1,
1959 const struct mips_cl_insn *insn2)
1960{
1961 unsigned long pinfo1, pinfo2;
1633
1962
1634 if (mips_relax.sequence != 2
1635 && (!mips_opts.noreorder || prev_nop_frag != NULL))
1636 {
1637 int prev_prev_nop;
1963 /* This function needs to know which pinfo flags are set for INSN2
1964 and which registers INSN2 uses. The former is stored in PINFO2 and
1965 the latter is tested via INSN2_USES_REG. If INSN2 is null, PINFO2
1966 will have every flag set and INSN2_USES_REG will always return true. */
1967 pinfo1 = insn1->insn_mo->pinfo;
1968 pinfo2 = insn2 ? insn2->insn_mo->pinfo : ~0U;
1638
1969
1639 /* If the previous insn required any delay slots, see if we need
1640 to insert a NOP or two. There are eight kinds of possible
1641 hazards, of which an instruction can have at most one type.
1642 (1) a load from memory delay
1643 (2) a load from a coprocessor delay
1644 (3) an unconditional branch delay
1645 (4) a conditional branch delay
1646 (5) a move to coprocessor register delay
1647 (6) a load coprocessor register from memory delay
1648 (7) a coprocessor condition code delay
1649 (8) a HI/LO special register delay
1970#define INSN2_USES_REG(REG, CLASS) \
1971 (insn2 == NULL || insn_uses_reg (insn2, REG, CLASS))
1650
1972
1651 There are a lot of optimizations we could do that we don't.
1652 In particular, we do not, in general, reorder instructions.
1653 If you use gcc with optimization, it will reorder
1654 instructions and generally do much more optimization then we
1655 do here; repeating all that work in the assembler would only
1656 benefit hand written assembly code, and does not seem worth
1657 it. */
1973 /* For most targets, write-after-read dependencies on the HI and LO
1974 registers must be separated by at least two instructions. */
1975 if (!hilo_interlocks)
1976 {
1977 if ((pinfo1 & INSN_READ_LO) && (pinfo2 & INSN_WRITE_LO))
1978 return 2;
1979 if ((pinfo1 & INSN_READ_HI) && (pinfo2 & INSN_WRITE_HI))
1980 return 2;
1981 }
1658
1982
1659 /* This is how a NOP is emitted. */
1660#define emit_nop() \
1661 (mips_opts.mips16 \
1662 ? md_number_to_chars (frag_more (2), 0x6500, 2) \
1663 : md_number_to_chars (frag_more (4), 0, 4))
1983 /* If we're working around r7000 errata, there must be two instructions
1984 between an mfhi or mflo and any instruction that uses the result. */
1985 if (mips_7000_hilo_fix
1986 && MF_HILO_INSN (pinfo1)
1987 && INSN2_USES_REG (EXTRACT_OPERAND (RD, *insn1), MIPS_GR_REG))
1988 return 2;
1664
1989
1665 /* The previous insn might require a delay slot, depending upon
1666 the contents of the current insn. */
1667 if (! mips_opts.mips16
1668 && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY)
1669 && ! gpr_interlocks)
1670 || ((prev_pinfo & INSN_LOAD_COPROC_DELAY)
1671 && ! cop_interlocks)))
1990 /* If working around VR4120 errata, check for combinations that need
1991 a single intervening instruction. */
1992 if (mips_fix_vr4120)
1993 {
1994 unsigned int class1, class2;
1995
1996 class1 = classify_vr4120_insn (insn1->insn_mo->name);
1997 if (class1 != NUM_FIX_VR4120_CLASSES && vr4120_conflicts[class1] != 0)
1672 {
1998 {
1673 /* A load from a coprocessor or from memory. All load
1674 delays delay the use of general register rt for one
1675 instruction. */
1676 /* Itbl support may require additional care here. */
1677 know (prev_pinfo & INSN_WRITE_GPR_T);
1678 if (mips_optimize == 0
1679 || insn_uses_reg (ip,
1680 ((prev_insn.insn_opcode >> OP_SH_RT)
1681 & OP_MASK_RT),
1682 MIPS_GR_REG))
1683 ++nops;
1999 if (insn2 == NULL)
2000 return 1;
2001 class2 = classify_vr4120_insn (insn2->insn_mo->name);
2002 if (vr4120_conflicts[class1] & (1 << class2))
2003 return 1;
1684 }
2004 }
1685 else if (! mips_opts.mips16
1686 && (((prev_pinfo & INSN_COPROC_MOVE_DELAY)
1687 && ! cop_interlocks)
1688 || ((prev_pinfo & INSN_COPROC_MEMORY_DELAY)
1689 && ! cop_mem_interlocks)))
2005 }
2006
2007 if (!mips_opts.mips16)
2008 {
2009 /* Check for GPR or coprocessor load delays. All such delays
2010 are on the RT register. */
2011 /* Itbl support may require additional care here. */
2012 if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
2013 || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
1690 {
2014 {
1691 /* A generic coprocessor delay. The previous instruction
1692 modified a coprocessor general or control register. If
1693 it modified a control register, we need to avoid any
1694 coprocessor instruction (this is probably not always
1695 required, but it sometimes is). If it modified a general
1696 register, we avoid using that register.
2015 know (pinfo1 & INSN_WRITE_GPR_T);
2016 if (INSN2_USES_REG (EXTRACT_OPERAND (RT, *insn1), MIPS_GR_REG))
2017 return 1;
2018 }
1697
2019
1698 This case is not handled very well. There is no special
1699 knowledge of CP0 handling, and the coprocessors other
1700 than the floating point unit are not distinguished at
1701 all. */
1702 /* Itbl support may require additional care here. FIXME!
1703 Need to modify this to include knowledge about
1704 user specified delays! */
1705 if (prev_pinfo & INSN_WRITE_FPR_T)
2020 /* Check for generic coprocessor hazards.
2021
2022 This case is not handled very well. There is no special
2023 knowledge of CP0 handling, and the coprocessors other than
2024 the floating point unit are not distinguished at all. */
2025 /* Itbl support may require additional care here. FIXME!
2026 Need to modify this to include knowledge about
2027 user specified delays! */
2028 else if ((!cop_interlocks && (pinfo1 & INSN_COPROC_MOVE_DELAY))
2029 || (!cop_mem_interlocks && (pinfo1 & INSN_COPROC_MEMORY_DELAY)))
2030 {
2031 /* Handle cases where INSN1 writes to a known general coprocessor
2032 register. There must be a one instruction delay before INSN2
2033 if INSN2 reads that register, otherwise no delay is needed. */
2034 if (pinfo1 & INSN_WRITE_FPR_T)
1706 {
2035 {
1707 if (mips_optimize == 0
1708 || insn_uses_reg (ip,
1709 ((prev_insn.insn_opcode >> OP_SH_FT)
1710 & OP_MASK_FT),
1711 MIPS_FP_REG))
1712 ++nops;
2036 if (INSN2_USES_REG (EXTRACT_OPERAND (FT, *insn1), MIPS_FP_REG))
2037 return 1;
1713 }
2038 }
1714 else if (prev_pinfo & INSN_WRITE_FPR_S)
2039 else if (pinfo1 & INSN_WRITE_FPR_S)
1715 {
2040 {
1716 if (mips_optimize == 0
1717 || insn_uses_reg (ip,
1718 ((prev_insn.insn_opcode >> OP_SH_FS)
1719 & OP_MASK_FS),
1720 MIPS_FP_REG))
1721 ++nops;
2041 if (INSN2_USES_REG (EXTRACT_OPERAND (FS, *insn1), MIPS_FP_REG))
2042 return 1;
1722 }
1723 else
1724 {
2043 }
2044 else
2045 {
1725 /* We don't know exactly what the previous instruction
1726 does. If the current instruction uses a coprocessor
1727 register, we must insert a NOP. If previous
1728 instruction may set the condition codes, and the
1729 current instruction uses them, we must insert two
1730 NOPS. */
1731 /* Itbl support may require additional care here. */
1732 if (mips_optimize == 0
1733 || ((prev_pinfo & INSN_WRITE_COND_CODE)
1734 && (pinfo & INSN_READ_COND_CODE)))
1735 nops += 2;
1736 else if (pinfo & INSN_COP)
1737 ++nops;
2046 /* Read-after-write dependencies on the control registers
2047 require a two-instruction gap. */
2048 if ((pinfo1 & INSN_WRITE_COND_CODE)
2049 && (pinfo2 & INSN_READ_COND_CODE))
2050 return 2;
2051
2052 /* We don't know exactly what INSN1 does. If INSN2 is
2053 also a coprocessor instruction, assume there must be
2054 a one instruction gap. */
2055 if (pinfo2 & INSN_COP)
2056 return 1;
1738 }
1739 }
2057 }
2058 }
1740 else if (! mips_opts.mips16
1741 && (prev_pinfo & INSN_WRITE_COND_CODE)
1742 && ! cop_interlocks)
1743 {
1744 /* The previous instruction sets the coprocessor condition
1745 codes, but does not require a general coprocessor delay
1746 (this means it is a floating point comparison
1747 instruction). If this instruction uses the condition
1748 codes, we need to insert a single NOP. */
1749 /* Itbl support may require additional care here. */
1750 if (mips_optimize == 0
1751 || (pinfo & INSN_READ_COND_CODE))
1752 ++nops;
1753 }
1754
2059
1755 /* If we're fixing up mfhi/mflo for the r7000 and the
1756 previous insn was an mfhi/mflo and the current insn
1757 reads the register that the mfhi/mflo wrote to, then
1758 insert two nops. */
2060 /* Check for read-after-write dependencies on the coprocessor
2061 control registers in cases where INSN1 does not need a general
2062 coprocessor delay. This means that INSN1 is a floating point
2063 comparison instruction. */
2064 /* Itbl support may require additional care here. */
2065 else if (!cop_interlocks
2066 && (pinfo1 & INSN_WRITE_COND_CODE)
2067 && (pinfo2 & INSN_READ_COND_CODE))
2068 return 1;
2069 }
1759
2070
1760 else if (mips_7000_hilo_fix
1761 && MF_HILO_INSN (prev_pinfo)
1762 && insn_uses_reg (ip, ((prev_insn.insn_opcode >> OP_SH_RD)
1763 & OP_MASK_RD),
1764 MIPS_GR_REG))
1765 {
1766 nops += 2;
1767 }
2071#undef INSN2_USES_REG
1768
2072
1769 /* If we're fixing up mfhi/mflo for the r7000 and the
1770 2nd previous insn was an mfhi/mflo and the current insn
1771 reads the register that the mfhi/mflo wrote to, then
1772 insert one nop. */
2073 return 0;
2074}
1773
2075
1774 else if (mips_7000_hilo_fix
1775 && MF_HILO_INSN (prev_prev_insn.insn_opcode)
1776 && insn_uses_reg (ip, ((prev_prev_insn.insn_opcode >> OP_SH_RD)
1777 & OP_MASK_RD),
1778 MIPS_GR_REG))
2076/* Return the number of nops that would be needed to work around the
2077 VR4130 mflo/mfhi errata if instruction INSN immediately followed
2078 the MAX_VR4130_NOPS instructions described by HISTORY. */
1779
2079
1780 {
1781 ++nops;
1782 }
2080static int
2081nops_for_vr4130 (const struct mips_cl_insn *history,
2082 const struct mips_cl_insn *insn)
2083{
2084 int i, j, reg;
1783
2085
1784 else if (prev_pinfo & INSN_READ_LO)
1785 {
1786 /* The previous instruction reads the LO register; if the
1787 current instruction writes to the LO register, we must
1788 insert two NOPS. Some newer processors have interlocks.
1789 Also the tx39's multiply instructions can be executed
1790 immediately after a read from HI/LO (without the delay),
1791 though the tx39's divide insns still do require the
1792 delay. */
1793 if (! (hilo_interlocks
1794 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1795 && (mips_optimize == 0
1796 || (pinfo & INSN_WRITE_LO)))
1797 nops += 2;
1798 /* Most mips16 branch insns don't have a delay slot.
1799 If a read from LO is immediately followed by a branch
1800 to a write to LO we have a read followed by a write
1801 less than 2 insns away. We assume the target of
1802 a branch might be a write to LO, and insert a nop
1803 between a read and an immediately following branch. */
1804 else if (mips_opts.mips16
1805 && (mips_optimize == 0
1806 || (pinfo & MIPS16_INSN_BRANCH)))
1807 ++nops;
1808 }
1809 else if (prev_insn.insn_mo->pinfo & INSN_READ_HI)
1810 {
1811 /* The previous instruction reads the HI register; if the
1812 current instruction writes to the HI register, we must
1813 insert a NOP. Some newer processors have interlocks.
1814 Also the note tx39's multiply above. */
1815 if (! (hilo_interlocks
1816 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
1817 && (mips_optimize == 0
1818 || (pinfo & INSN_WRITE_HI)))
1819 nops += 2;
1820 /* Most mips16 branch insns don't have a delay slot.
1821 If a read from HI is immediately followed by a branch
1822 to a write to HI we have a read followed by a write
1823 less than 2 insns away. We assume the target of
1824 a branch might be a write to HI, and insert a nop
1825 between a read and an immediately following branch. */
1826 else if (mips_opts.mips16
1827 && (mips_optimize == 0
1828 || (pinfo & MIPS16_INSN_BRANCH)))
1829 ++nops;
1830 }
2086 /* Check if the instruction writes to HI or LO. MTHI and MTLO
2087 are not affected by the errata. */
2088 if (insn != 0
2089 && ((insn->insn_mo->pinfo & (INSN_WRITE_HI | INSN_WRITE_LO)) == 0
2090 || strcmp (insn->insn_mo->name, "mtlo") == 0
2091 || strcmp (insn->insn_mo->name, "mthi") == 0))
2092 return 0;
1831
2093
1832 /* If the previous instruction was in a noreorder section, then
1833 we don't want to insert the nop after all. */
1834 /* Itbl support may require additional care here. */
1835 if (prev_insn_unreordered)
1836 nops = 0;
2094 /* Search for the first MFLO or MFHI. */
2095 for (i = 0; i < MAX_VR4130_NOPS; i++)
2096 if (!history[i].noreorder_p && MF_HILO_INSN (history[i].insn_mo->pinfo))
2097 {
2098 /* Extract the destination register. */
2099 if (mips_opts.mips16)
2100 reg = mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RX, history[i])];
2101 else
2102 reg = EXTRACT_OPERAND (RD, history[i]);
1837
2103
1838 /* There are two cases which require two intervening
1839 instructions: 1) setting the condition codes using a move to
1840 coprocessor instruction which requires a general coprocessor
1841 delay and then reading the condition codes 2) reading the HI
1842 or LO register and then writing to it (except on processors
1843 which have interlocks). If we are not already emitting a NOP
1844 instruction, we must check for these cases compared to the
1845 instruction previous to the previous instruction. */
1846 if ((! mips_opts.mips16
1847 && (prev_prev_insn.insn_mo->pinfo & INSN_COPROC_MOVE_DELAY)
1848 && (prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
1849 && (pinfo & INSN_READ_COND_CODE)
1850 && ! cop_interlocks)
1851 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_LO)
1852 && (pinfo & INSN_WRITE_LO)
1853 && ! (hilo_interlocks
1854 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT))))
1855 || ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
1856 && (pinfo & INSN_WRITE_HI)
1857 && ! (hilo_interlocks
1858 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))))
1859 prev_prev_nop = 1;
1860 else
1861 prev_prev_nop = 0;
2104 /* No nops are needed if INSN reads that register. */
2105 if (insn != NULL && insn_uses_reg (insn, reg, MIPS_GR_REG))
2106 return 0;
1862
2107
1863 if (prev_prev_insn_unreordered)
1864 prev_prev_nop = 0;
2108 /* ...or if any of the intervening instructions do. */
2109 for (j = 0; j < i; j++)
2110 if (insn_uses_reg (&history[j], reg, MIPS_GR_REG))
2111 return 0;
1865
2112
1866 if (prev_prev_nop && nops == 0)
1867 ++nops;
2113 return MAX_VR4130_NOPS - i;
2114 }
2115 return 0;
2116}
1868
2117
1869 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
1870 {
1871 /* We're out of bits in pinfo, so we must resort to string
1872 ops here. Shortcuts are selected based on opcodes being
1873 limited to the VR4120 instruction set. */
1874 int min_nops = 0;
1875 const char *pn = prev_insn.insn_mo->name;
1876 const char *tn = ip->insn_mo->name;
1877 if (strncmp(pn, "macc", 4) == 0
1878 || strncmp(pn, "dmacc", 5) == 0)
1879 {
1880 /* Errata 21 - [D]DIV[U] after [D]MACC */
1881 if (strstr (tn, "div"))
1882 {
1883 min_nops = 1;
1884 }
2118/* Return the number of nops that would be needed if instruction INSN
2119 immediately followed the MAX_NOPS instructions given by HISTORY,
2120 where HISTORY[0] is the most recent instruction. If INSN is null,
2121 return the worse-case number of nops for any instruction. */
1885
2122
1886 /* Errata 23 - Continuous DMULT[U]/DMACC instructions */
1887 if (pn[0] == 'd' /* dmacc */
1888 && (strncmp(tn, "dmult", 5) == 0
1889 || strncmp(tn, "dmacc", 5) == 0))
1890 {
1891 min_nops = 1;
1892 }
2123static int
2124nops_for_insn (const struct mips_cl_insn *history,
2125 const struct mips_cl_insn *insn)
2126{
2127 int i, nops, tmp_nops;
1893
2128
1894 /* Errata 24 - MT{LO,HI} after [D]MACC */
1895 if (strcmp (tn, "mtlo") == 0
1896 || strcmp (tn, "mthi") == 0)
1897 {
1898 min_nops = 1;
1899 }
2129 nops = 0;
2130 for (i = 0; i < MAX_DELAY_NOPS; i++)
2131 if (!history[i].noreorder_p)
2132 {
2133 tmp_nops = insns_between (history + i, insn) - i;
2134 if (tmp_nops > nops)
2135 nops = tmp_nops;
2136 }
1900
2137
1901 }
1902 else if (strncmp(pn, "dmult", 5) == 0
1903 && (strncmp(tn, "dmult", 5) == 0
1904 || strncmp(tn, "dmacc", 5) == 0))
1905 {
1906 /* Here is the rest of errata 23. */
1907 min_nops = 1;
1908 }
1909 if (nops < min_nops)
1910 nops = min_nops;
1911 }
2138 if (mips_fix_vr4130)
2139 {
2140 tmp_nops = nops_for_vr4130 (history, insn);
2141 if (tmp_nops > nops)
2142 nops = tmp_nops;
2143 }
1912
2144
1913 /* If we are being given a nop instruction, don't bother with
1914 one of the nops we would otherwise output. This will only
1915 happen when a nop instruction is used with mips_optimize set
1916 to 0. */
1917 if (nops > 0
1918 && ! mips_opts.noreorder
1919 && ip->insn_opcode == (unsigned) (mips_opts.mips16 ? 0x6500 : 0))
1920 --nops;
2145 return nops;
2146}
1921
2147
1922 /* Now emit the right number of NOP instructions. */
1923 if (nops > 0 && ! mips_opts.noreorder)
2148/* The variable arguments provide NUM_INSNS extra instructions that
2149 might be added to HISTORY. Return the largest number of nops that
2150 would be needed after the extended sequence. */
2151
2152static int
2153nops_for_sequence (int num_insns, const struct mips_cl_insn *history, ...)
2154{
2155 va_list args;
2156 struct mips_cl_insn buffer[MAX_NOPS];
2157 struct mips_cl_insn *cursor;
2158 int nops;
2159
2160 va_start (args, history);
2161 cursor = buffer + num_insns;
2162 memcpy (cursor, history, (MAX_NOPS - num_insns) * sizeof (*cursor));
2163 while (cursor > buffer)
2164 *--cursor = *va_arg (args, const struct mips_cl_insn *);
2165
2166 nops = nops_for_insn (buffer, NULL);
2167 va_end (args);
2168 return nops;
2169}
2170
2171/* Like nops_for_insn, but if INSN is a branch, take into account the
2172 worst-case delay for the branch target. */
2173
2174static int
2175nops_for_insn_or_target (const struct mips_cl_insn *history,
2176 const struct mips_cl_insn *insn)
2177{
2178 int nops, tmp_nops;
2179
2180 nops = nops_for_insn (history, insn);
2181 if (insn->insn_mo->pinfo & (INSN_UNCOND_BRANCH_DELAY
2182 | INSN_COND_BRANCH_DELAY
2183 | INSN_COND_BRANCH_LIKELY))
2184 {
2185 tmp_nops = nops_for_sequence (2, history, insn, NOP_INSN);
2186 if (tmp_nops > nops)
2187 nops = tmp_nops;
2188 }
2189 else if (mips_opts.mips16 && (insn->insn_mo->pinfo & MIPS16_INSN_BRANCH))
2190 {
2191 tmp_nops = nops_for_sequence (1, history, insn);
2192 if (tmp_nops > nops)
2193 nops = tmp_nops;
2194 }
2195 return nops;
2196}
2197
2198/* Output an instruction. IP is the instruction information.
2199 ADDRESS_EXPR is an operand of the instruction to be used with
2200 RELOC_TYPE. */
2201
2202static void
2203append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
2204 bfd_reloc_code_real_type *reloc_type)
2205{
2206 register unsigned long prev_pinfo, pinfo;
2207 relax_stateT prev_insn_frag_type = 0;
2208 bfd_boolean relaxed_branch = FALSE;
2209
2210 /* Mark instruction labels in mips16 mode. */
2211 mips16_mark_labels ();
2212
2213 prev_pinfo = history[0].insn_mo->pinfo;
2214 pinfo = ip->insn_mo->pinfo;
2215
2216 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2217 {
2218 /* There are a lot of optimizations we could do that we don't.
2219 In particular, we do not, in general, reorder instructions.
2220 If you use gcc with optimization, it will reorder
2221 instructions and generally do much more optimization then we
2222 do here; repeating all that work in the assembler would only
2223 benefit hand written assembly code, and does not seem worth
2224 it. */
2225 int nops = (mips_optimize == 0
2226 ? nops_for_insn (history, NULL)
2227 : nops_for_insn_or_target (history, ip));
2228 if (nops > 0)
1924 {
1925 fragS *old_frag;
1926 unsigned long old_frag_offset;
1927 int i;
2229 {
2230 fragS *old_frag;
2231 unsigned long old_frag_offset;
2232 int i;
1928 struct insn_label_list *l;
1929
1930 old_frag = frag_now;
1931 old_frag_offset = frag_now_fix ();
1932
1933 for (i = 0; i < nops; i++)
1934 emit_nop ();
1935
1936 if (listing)

--- 5 unchanged lines hidden (view full) ---

1942 argument to frag_grow here must be at least as large
1943 as the argument to all other calls to frag_grow in
1944 this file. We don't have to worry about being in the
1945 middle of a variant frag, because the variants insert
1946 all needed nop instructions themselves. */
1947 frag_grow (40);
1948 }
1949
2233
2234 old_frag = frag_now;
2235 old_frag_offset = frag_now_fix ();
2236
2237 for (i = 0; i < nops; i++)
2238 emit_nop ();
2239
2240 if (listing)

--- 5 unchanged lines hidden (view full) ---

2246 argument to frag_grow here must be at least as large
2247 as the argument to all other calls to frag_grow in
2248 this file. We don't have to worry about being in the
2249 middle of a variant frag, because the variants insert
2250 all needed nop instructions themselves. */
2251 frag_grow (40);
2252 }
2253
1950 for (l = insn_labels; l != NULL; l = l->next)
1951 {
1952 valueT val;
2254 mips_move_labels ();
1953
2255
1954 assert (S_GET_SEGMENT (l->label) == now_seg);
1955 symbol_set_frag (l->label, frag_now);
1956 val = (valueT) frag_now_fix ();
1957 /* mips16 text labels are stored as odd. */
1958 if (mips_opts.mips16)
1959 ++val;
1960 S_SET_VALUE (l->label, val);
1961 }
1962
1963#ifndef NO_ECOFF_DEBUGGING
1964 if (ECOFF_DEBUGGING)
1965 ecoff_fix_loc (old_frag, old_frag_offset);
1966#endif
1967 }
2256#ifndef NO_ECOFF_DEBUGGING
2257 if (ECOFF_DEBUGGING)
2258 ecoff_fix_loc (old_frag, old_frag_offset);
2259#endif
2260 }
1968 else if (prev_nop_frag != NULL)
1969 {
1970 /* We have a frag holding nops we may be able to remove. If
1971 we don't need any nops, we can decrease the size of
1972 prev_nop_frag by the size of one instruction. If we do
1973 need some nops, we count them in prev_nops_required. */
1974 if (prev_nop_frag_since == 0)
1975 {
1976 if (nops == 0)
1977 {
1978 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1979 --prev_nop_frag_holds;
1980 }
1981 else
1982 prev_nop_frag_required += nops;
1983 }
1984 else
1985 {
1986 if (prev_prev_nop == 0)
1987 {
1988 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
1989 --prev_nop_frag_holds;
1990 }
1991 else
1992 ++prev_nop_frag_required;
1993 }
2261 }
2262 else if (mips_relax.sequence != 2 && prev_nop_frag != NULL)
2263 {
2264 /* Work out how many nops in prev_nop_frag are needed by IP. */
2265 int nops = nops_for_insn_or_target (history, ip);
2266 assert (nops <= prev_nop_frag_holds);
1994
2267
1995 if (prev_nop_frag_holds <= prev_nop_frag_required)
1996 prev_nop_frag = NULL;
2268 /* Enforce NOPS as a minimum. */
2269 if (nops > prev_nop_frag_required)
2270 prev_nop_frag_required = nops;
1997
2271
1998 ++prev_nop_frag_since;
1999
2000 /* Sanity check: by the time we reach the second instruction
2001 after prev_nop_frag, we should have used up all the nops
2002 one way or another. */
2003 assert (prev_nop_frag_since <= 1 || prev_nop_frag == NULL);
2272 if (prev_nop_frag_holds == prev_nop_frag_required)
2273 {
2274 /* Settle for the current number of nops. Update the history
2275 accordingly (for the benefit of any future .set reorder code). */
2276 prev_nop_frag = NULL;
2277 insert_into_history (prev_nop_frag_since,
2278 prev_nop_frag_holds, NOP_INSN);
2004 }
2279 }
2280 else
2281 {
2282 /* Allow this instruction to replace one of the nops that was
2283 tentatively added to prev_nop_frag. */
2284 prev_nop_frag->fr_fix -= mips_opts.mips16 ? 2 : 4;
2285 prev_nop_frag_holds--;
2286 prev_nop_frag_since++;
2287 }
2005 }
2006
2288 }
2289
2290#ifdef OBJ_ELF
2291 /* The value passed to dwarf2_emit_insn is the distance between
2292 the beginning of the current instruction and the address that
2293 should be recorded in the debug tables. For MIPS16 debug info
2294 we want to use ISA-encoded addresses, so we pass -1 for an
2295 address higher by one than the current. */
2296 dwarf2_emit_insn (mips_opts.mips16 ? -1 : 0);
2297#endif
2298
2007 /* Record the frag type before frag_var. */
2299 /* Record the frag type before frag_var. */
2008 if (prev_insn_frag)
2009 prev_insn_frag_type = prev_insn_frag->fr_type;
2300 if (history[0].frag)
2301 prev_insn_frag_type = history[0].frag->fr_type;
2010
2011 if (address_expr
2012 && *reloc_type == BFD_RELOC_16_PCREL_S2
2013 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2014 || pinfo & INSN_COND_BRANCH_LIKELY)
2015 && mips_relax_branch
2016 /* Don't try branch relaxation within .set nomacro, or within
2017 .set noat if we use $at for PIC computations. If it turns
2018 out that the branch was out-of-range, we'll get an error. */
2019 && !mips_opts.warn_about_macros
2020 && !(mips_opts.noat && mips_pic != NO_PIC)
2021 && !mips_opts.mips16)
2022 {
2023 relaxed_branch = TRUE;
2302
2303 if (address_expr
2304 && *reloc_type == BFD_RELOC_16_PCREL_S2
2305 && (pinfo & INSN_UNCOND_BRANCH_DELAY || pinfo & INSN_COND_BRANCH_DELAY
2306 || pinfo & INSN_COND_BRANCH_LIKELY)
2307 && mips_relax_branch
2308 /* Don't try branch relaxation within .set nomacro, or within
2309 .set noat if we use $at for PIC computations. If it turns
2310 out that the branch was out-of-range, we'll get an error. */
2311 && !mips_opts.warn_about_macros
2312 && !(mips_opts.noat && mips_pic != NO_PIC)
2313 && !mips_opts.mips16)
2314 {
2315 relaxed_branch = TRUE;
2024 f = frag_var (rs_machine_dependent,
2025 relaxed_branch_length
2026 (NULL, NULL,
2027 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2028 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
2029 RELAX_BRANCH_ENCODE
2030 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2031 pinfo & INSN_COND_BRANCH_LIKELY,
2032 pinfo & INSN_WRITE_GPR_31,
2033 0),
2034 address_expr->X_add_symbol,
2035 address_expr->X_add_number,
2036 0);
2316 add_relaxed_insn (ip, (relaxed_branch_length
2317 (NULL, NULL,
2318 (pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
2319 : (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
2320 : 0)), 4,
2321 RELAX_BRANCH_ENCODE
2322 (pinfo & INSN_UNCOND_BRANCH_DELAY,
2323 pinfo & INSN_COND_BRANCH_LIKELY,
2324 pinfo & INSN_WRITE_GPR_31,
2325 0),
2326 address_expr->X_add_symbol,
2327 address_expr->X_add_number);
2037 *reloc_type = BFD_RELOC_UNUSED;
2038 }
2039 else if (*reloc_type > BFD_RELOC_UNUSED)
2040 {
2041 /* We need to set up a variant frag. */
2042 assert (mips_opts.mips16 && address_expr != NULL);
2328 *reloc_type = BFD_RELOC_UNUSED;
2329 }
2330 else if (*reloc_type > BFD_RELOC_UNUSED)
2331 {
2332 /* We need to set up a variant frag. */
2333 assert (mips_opts.mips16 && address_expr != NULL);
2043 f = frag_var (rs_machine_dependent, 4, 0,
2044 RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
2045 mips16_small, mips16_ext,
2046 (prev_pinfo
2047 & INSN_UNCOND_BRANCH_DELAY),
2048 (*prev_insn_reloc_type
2049 == BFD_RELOC_MIPS16_JMP)),
2050 make_expr_symbol (address_expr), 0, NULL);
2334 add_relaxed_insn (ip, 4, 0,
2335 RELAX_MIPS16_ENCODE
2336 (*reloc_type - BFD_RELOC_UNUSED,
2337 mips16_small, mips16_ext,
2338 prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
2339 history[0].mips16_absolute_jump_p),
2340 make_expr_symbol (address_expr), 0);
2051 }
2052 else if (mips_opts.mips16
2053 && ! ip->use_extend
2054 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2055 {
2341 }
2342 else if (mips_opts.mips16
2343 && ! ip->use_extend
2344 && *reloc_type != BFD_RELOC_MIPS16_JMP)
2345 {
2056 /* Make sure there is enough room to swap this instruction with
2057 a following jump instruction. */
2058 frag_grow (6);
2059 f = frag_more (2);
2346 if ((pinfo & INSN_UNCOND_BRANCH_DELAY) == 0)
2347 /* Make sure there is enough room to swap this instruction with
2348 a following jump instruction. */
2349 frag_grow (6);
2350 add_fixed_insn (ip);
2060 }
2061 else
2062 {
2063 if (mips_opts.mips16
2064 && mips_opts.noreorder
2065 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2066 as_warn (_("extended instruction in delay slot"));
2067

--- 7 unchanged lines hidden (view full) ---

2075 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2076 }
2077
2078 if (mips_relax.sequence != 2)
2079 mips_macro_warning.sizes[0] += 4;
2080 if (mips_relax.sequence != 1)
2081 mips_macro_warning.sizes[1] += 4;
2082
2351 }
2352 else
2353 {
2354 if (mips_opts.mips16
2355 && mips_opts.noreorder
2356 && (prev_pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
2357 as_warn (_("extended instruction in delay slot"));
2358

--- 7 unchanged lines hidden (view full) ---

2366 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2367 }
2368
2369 if (mips_relax.sequence != 2)
2370 mips_macro_warning.sizes[0] += 4;
2371 if (mips_relax.sequence != 1)
2372 mips_macro_warning.sizes[1] += 4;
2373
2083 f = frag_more (4);
2374 if (mips_opts.mips16)
2375 {
2376 ip->fixed_p = 1;
2377 ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
2378 }
2379 add_fixed_insn (ip);
2084 }
2085
2380 }
2381
2086 fixp[0] = fixp[1] = fixp[2] = NULL;
2087 if (address_expr != NULL && *reloc_type < BFD_RELOC_UNUSED)
2382 if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
2088 {
2089 if (address_expr->X_op == O_constant)
2090 {
2383 {
2384 if (address_expr->X_op == O_constant)
2385 {
2091 valueT tmp;
2386 unsigned int tmp;
2092
2093 switch (*reloc_type)
2094 {
2095 case BFD_RELOC_32:
2096 ip->insn_opcode |= address_expr->X_add_number;
2097 break;
2098
2099 case BFD_RELOC_MIPS_HIGHEST:
2387
2388 switch (*reloc_type)
2389 {
2390 case BFD_RELOC_32:
2391 ip->insn_opcode |= address_expr->X_add_number;
2392 break;
2393
2394 case BFD_RELOC_MIPS_HIGHEST:
2100 tmp = (address_expr->X_add_number
2101 + ((valueT) 0x8000 << 32) + 0x80008000) >> 16;
2102 tmp >>= 16;
2103 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2395 tmp = (address_expr->X_add_number + 0x800080008000ull) >> 48;
2396 ip->insn_opcode |= tmp & 0xffff;
2104 break;
2105
2106 case BFD_RELOC_MIPS_HIGHER:
2397 break;
2398
2399 case BFD_RELOC_MIPS_HIGHER:
2107 tmp = (address_expr->X_add_number + 0x80008000) >> 16;
2108 ip->insn_opcode |= (tmp >> 16) & 0xffff;
2400 tmp = (address_expr->X_add_number + 0x80008000ull) >> 32;
2401 ip->insn_opcode |= tmp & 0xffff;
2109 break;
2110
2111 case BFD_RELOC_HI16_S:
2402 break;
2403
2404 case BFD_RELOC_HI16_S:
2112 ip->insn_opcode |= ((address_expr->X_add_number + 0x8000)
2113 >> 16) & 0xffff;
2405 tmp = (address_expr->X_add_number + 0x8000) >> 16;
2406 ip->insn_opcode |= tmp & 0xffff;
2114 break;
2115
2116 case BFD_RELOC_HI16:
2117 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2118 break;
2119
2407 break;
2408
2409 case BFD_RELOC_HI16:
2410 ip->insn_opcode |= (address_expr->X_add_number >> 16) & 0xffff;
2411 break;
2412
2413 case BFD_RELOC_UNUSED:
2120 case BFD_RELOC_LO16:
2121 case BFD_RELOC_MIPS_GOT_DISP:
2122 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2123 break;
2124
2125 case BFD_RELOC_MIPS_JMP:
2126 if ((address_expr->X_add_number & 3) != 0)
2127 as_bad (_("jump to misaligned address (0x%lx)"),
2128 (unsigned long) address_expr->X_add_number);
2414 case BFD_RELOC_LO16:
2415 case BFD_RELOC_MIPS_GOT_DISP:
2416 ip->insn_opcode |= address_expr->X_add_number & 0xffff;
2417 break;
2418
2419 case BFD_RELOC_MIPS_JMP:
2420 if ((address_expr->X_add_number & 3) != 0)
2421 as_bad (_("jump to misaligned address (0x%lx)"),
2422 (unsigned long) address_expr->X_add_number);
2129 if (address_expr->X_add_number & ~0xfffffff)
2130 as_bad (_("jump address range overflow (0x%lx)"),
2131 (unsigned long) address_expr->X_add_number);
2132 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2133 break;
2134
2135 case BFD_RELOC_MIPS16_JMP:
2136 if ((address_expr->X_add_number & 3) != 0)
2137 as_bad (_("jump to misaligned address (0x%lx)"),
2138 (unsigned long) address_expr->X_add_number);
2423 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0x3ffffff;
2424 break;
2425
2426 case BFD_RELOC_MIPS16_JMP:
2427 if ((address_expr->X_add_number & 3) != 0)
2428 as_bad (_("jump to misaligned address (0x%lx)"),
2429 (unsigned long) address_expr->X_add_number);
2139 if (address_expr->X_add_number & ~0xfffffff)
2140 as_bad (_("jump address range overflow (0x%lx)"),
2141 (unsigned long) address_expr->X_add_number);
2142 ip->insn_opcode |=
2143 (((address_expr->X_add_number & 0x7c0000) << 3)
2144 | ((address_expr->X_add_number & 0xf800000) >> 7)
2145 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2146 break;
2147
2148 case BFD_RELOC_16_PCREL_S2:
2430 ip->insn_opcode |=
2431 (((address_expr->X_add_number & 0x7c0000) << 3)
2432 | ((address_expr->X_add_number & 0xf800000) >> 7)
2433 | ((address_expr->X_add_number & 0x3fffc) >> 2));
2434 break;
2435
2436 case BFD_RELOC_16_PCREL_S2:
2149 goto need_reloc;
2437 if ((address_expr->X_add_number & 3) != 0)
2438 as_bad (_("branch to misaligned address (0x%lx)"),
2439 (unsigned long) address_expr->X_add_number);
2440 if (mips_relax_branch)
2441 goto need_reloc;
2442 if ((address_expr->X_add_number + 0x20000) & ~0x3ffff)
2443 as_bad (_("branch address range overflow (0x%lx)"),
2444 (unsigned long) address_expr->X_add_number);
2445 ip->insn_opcode |= (address_expr->X_add_number >> 2) & 0xffff;
2446 break;
2150
2151 default:
2152 internalError ();
2153 }
2154 }
2447
2448 default:
2449 internalError ();
2450 }
2451 }
2155 else
2452 else if (*reloc_type < BFD_RELOC_UNUSED)
2156 need_reloc:
2157 {
2158 reloc_howto_type *howto;
2159 int i;
2160
2161 /* In a compound relocation, it is the final (outermost)
2162 operator that determines the relocated field. */
2163 for (i = 1; i < 3; i++)
2164 if (reloc_type[i] == BFD_RELOC_UNUSED)
2165 break;
2166
2167 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2453 need_reloc:
2454 {
2455 reloc_howto_type *howto;
2456 int i;
2457
2458 /* In a compound relocation, it is the final (outermost)
2459 operator that determines the relocated field. */
2460 for (i = 1; i < 3; i++)
2461 if (reloc_type[i] == BFD_RELOC_UNUSED)
2462 break;
2463
2464 howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
2168 fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
2169 bfd_get_reloc_size(howto),
2170 address_expr,
2171 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2172 reloc_type[0]);
2465 ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
2466 bfd_get_reloc_size (howto),
2467 address_expr,
2468 reloc_type[0] == BFD_RELOC_16_PCREL_S2,
2469 reloc_type[0]);
2173
2174 /* These relocations can have an addend that won't fit in
2175 4 octets for 64bit assembly. */
2176 if (HAVE_64BIT_GPRS
2177 && ! howto->partial_inplace
2178 && (reloc_type[0] == BFD_RELOC_16
2179 || reloc_type[0] == BFD_RELOC_32
2180 || reloc_type[0] == BFD_RELOC_MIPS_JMP

--- 5 unchanged lines hidden (view full) ---

2186 || reloc_type[0] == BFD_RELOC_64
2187 || reloc_type[0] == BFD_RELOC_CTOR
2188 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2189 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2190 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2191 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2192 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2193 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2470
2471 /* These relocations can have an addend that won't fit in
2472 4 octets for 64bit assembly. */
2473 if (HAVE_64BIT_GPRS
2474 && ! howto->partial_inplace
2475 && (reloc_type[0] == BFD_RELOC_16
2476 || reloc_type[0] == BFD_RELOC_32
2477 || reloc_type[0] == BFD_RELOC_MIPS_JMP

--- 5 unchanged lines hidden (view full) ---

2483 || reloc_type[0] == BFD_RELOC_64
2484 || reloc_type[0] == BFD_RELOC_CTOR
2485 || reloc_type[0] == BFD_RELOC_MIPS_SUB
2486 || reloc_type[0] == BFD_RELOC_MIPS_HIGHEST
2487 || reloc_type[0] == BFD_RELOC_MIPS_HIGHER
2488 || reloc_type[0] == BFD_RELOC_MIPS_SCN_DISP
2489 || reloc_type[0] == BFD_RELOC_MIPS_REL16
2490 || reloc_type[0] == BFD_RELOC_MIPS_RELGOT))
2194 fixp[0]->fx_no_overflow = 1;
2491 ip->fixp[0]->fx_no_overflow = 1;
2195
2196 if (mips_relax.sequence)
2197 {
2198 if (mips_relax.first_fixup == 0)
2492
2493 if (mips_relax.sequence)
2494 {
2495 if (mips_relax.first_fixup == 0)
2199 mips_relax.first_fixup = fixp[0];
2496 mips_relax.first_fixup = ip->fixp[0];
2200 }
2201 else if (reloc_needs_lo_p (*reloc_type))
2202 {
2203 struct mips_hi_fixup *hi_fixup;
2204
2205 /* Reuse the last entry if it already has a matching %lo. */
2206 hi_fixup = mips_hi_fixup_list;
2207 if (hi_fixup == 0
2208 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2209 {
2210 hi_fixup = ((struct mips_hi_fixup *)
2211 xmalloc (sizeof (struct mips_hi_fixup)));
2212 hi_fixup->next = mips_hi_fixup_list;
2213 mips_hi_fixup_list = hi_fixup;
2214 }
2497 }
2498 else if (reloc_needs_lo_p (*reloc_type))
2499 {
2500 struct mips_hi_fixup *hi_fixup;
2501
2502 /* Reuse the last entry if it already has a matching %lo. */
2503 hi_fixup = mips_hi_fixup_list;
2504 if (hi_fixup == 0
2505 || !fixup_has_matching_lo_p (hi_fixup->fixp))
2506 {
2507 hi_fixup = ((struct mips_hi_fixup *)
2508 xmalloc (sizeof (struct mips_hi_fixup)));
2509 hi_fixup->next = mips_hi_fixup_list;
2510 mips_hi_fixup_list = hi_fixup;
2511 }
2215 hi_fixup->fixp = fixp[0];
2512 hi_fixup->fixp = ip->fixp[0];
2216 hi_fixup->seg = now_seg;
2217 }
2218
2219 /* Add fixups for the second and third relocations, if given.
2220 Note that the ABI allows the second relocation to be
2221 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2222 moment we only use RSS_UNDEF, but we could add support
2223 for the others if it ever becomes necessary. */
2224 for (i = 1; i < 3; i++)
2225 if (reloc_type[i] != BFD_RELOC_UNUSED)
2226 {
2513 hi_fixup->seg = now_seg;
2514 }
2515
2516 /* Add fixups for the second and third relocations, if given.
2517 Note that the ABI allows the second relocation to be
2518 against RSS_UNDEF, RSS_GP, RSS_GP0 or RSS_LOC. At the
2519 moment we only use RSS_UNDEF, but we could add support
2520 for the others if it ever becomes necessary. */
2521 for (i = 1; i < 3; i++)
2522 if (reloc_type[i] != BFD_RELOC_UNUSED)
2523 {
2227 address_expr->X_op = O_absent;
2228 address_expr->X_add_symbol = 0;
2229 address_expr->X_add_number = 0;
2230
2231 fixp[i] = fix_new_exp (frag_now, fixp[0]->fx_where,
2232 fixp[0]->fx_size, address_expr,
2524 ip->fixp[i] = fix_new (ip->frag, ip->where,
2525 ip->fixp[0]->fx_size, NULL, 0,
2233 FALSE, reloc_type[i]);
2526 FALSE, reloc_type[i]);
2527
2528 /* Use fx_tcbit to mark compound relocs. */
2529 ip->fixp[0]->fx_tcbit = 1;
2530 ip->fixp[i]->fx_tcbit = 1;
2234 }
2235 }
2236 }
2531 }
2532 }
2533 }
2534 install_insn (ip);
2237
2535
2238 if (! mips_opts.mips16)
2239 {
2240 md_number_to_chars (f, ip->insn_opcode, 4);
2241#ifdef OBJ_ELF
2242 dwarf2_emit_insn (4);
2243#endif
2244 }
2245 else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
2246 {
2247 md_number_to_chars (f, ip->insn_opcode >> 16, 2);
2248 md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
2249#ifdef OBJ_ELF
2250 dwarf2_emit_insn (4);
2251#endif
2252 }
2253 else
2254 {
2255 if (ip->use_extend)
2256 {
2257 md_number_to_chars (f, 0xf000 | ip->extend, 2);
2258 f += 2;
2259 }
2260 md_number_to_chars (f, ip->insn_opcode, 2);
2261#ifdef OBJ_ELF
2262 dwarf2_emit_insn (ip->use_extend ? 4 : 2);
2263#endif
2264 }
2265
2266 /* Update the register mask information. */
2267 if (! mips_opts.mips16)
2268 {
2269 if (pinfo & INSN_WRITE_GPR_D)
2536 /* Update the register mask information. */
2537 if (! mips_opts.mips16)
2538 {
2539 if (pinfo & INSN_WRITE_GPR_D)
2270 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD);
2540 mips_gprmask |= 1 << EXTRACT_OPERAND (RD, *ip);
2271 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2541 if ((pinfo & (INSN_WRITE_GPR_T | INSN_READ_GPR_T)) != 0)
2272 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RT) & OP_MASK_RT);
2542 mips_gprmask |= 1 << EXTRACT_OPERAND (RT, *ip);
2273 if (pinfo & INSN_READ_GPR_S)
2543 if (pinfo & INSN_READ_GPR_S)
2274 mips_gprmask |= 1 << ((ip->insn_opcode >> OP_SH_RS) & OP_MASK_RS);
2544 mips_gprmask |= 1 << EXTRACT_OPERAND (RS, *ip);
2275 if (pinfo & INSN_WRITE_GPR_31)
2276 mips_gprmask |= 1 << RA;
2277 if (pinfo & INSN_WRITE_FPR_D)
2545 if (pinfo & INSN_WRITE_GPR_31)
2546 mips_gprmask |= 1 << RA;
2547 if (pinfo & INSN_WRITE_FPR_D)
2278 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FD) & OP_MASK_FD);
2548 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FD, *ip);
2279 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2549 if ((pinfo & (INSN_WRITE_FPR_S | INSN_READ_FPR_S)) != 0)
2280 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FS) & OP_MASK_FS);
2550 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FS, *ip);
2281 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2551 if ((pinfo & (INSN_WRITE_FPR_T | INSN_READ_FPR_T)) != 0)
2282 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FT) & OP_MASK_FT);
2552 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FT, *ip);
2283 if ((pinfo & INSN_READ_FPR_R) != 0)
2553 if ((pinfo & INSN_READ_FPR_R) != 0)
2284 mips_cprmask[1] |= 1 << ((ip->insn_opcode >> OP_SH_FR) & OP_MASK_FR);
2554 mips_cprmask[1] |= 1 << EXTRACT_OPERAND (FR, *ip);
2285 if (pinfo & INSN_COP)
2286 {
2287 /* We don't keep enough information to sort these cases out.
2288 The itbl support does keep this information however, although
2289 we currently don't support itbl fprmats as part of the cop
2290 instruction. May want to add this support in the future. */
2291 }
2292 /* Never set the bit for $0, which is always zero. */
2293 mips_gprmask &= ~1 << 0;
2294 }
2295 else
2296 {
2297 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2555 if (pinfo & INSN_COP)
2556 {
2557 /* We don't keep enough information to sort these cases out.
2558 The itbl support does keep this information however, although
2559 we currently don't support itbl fprmats as part of the cop
2560 instruction. May want to add this support in the future. */
2561 }
2562 /* Never set the bit for $0, which is always zero. */
2563 mips_gprmask &= ~1 << 0;
2564 }
2565 else
2566 {
2567 if (pinfo & (MIPS16_INSN_WRITE_X | MIPS16_INSN_READ_X))
2298 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RX)
2299 & MIPS16OP_MASK_RX);
2568 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RX, *ip);
2300 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2569 if (pinfo & (MIPS16_INSN_WRITE_Y | MIPS16_INSN_READ_Y))
2301 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RY)
2302 & MIPS16OP_MASK_RY);
2570 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RY, *ip);
2303 if (pinfo & MIPS16_INSN_WRITE_Z)
2571 if (pinfo & MIPS16_INSN_WRITE_Z)
2304 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_RZ)
2305 & MIPS16OP_MASK_RZ);
2572 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (RZ, *ip);
2306 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2307 mips_gprmask |= 1 << TREG;
2308 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2309 mips_gprmask |= 1 << SP;
2310 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2311 mips_gprmask |= 1 << RA;
2312 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2313 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2314 if (pinfo & MIPS16_INSN_READ_Z)
2573 if (pinfo & (MIPS16_INSN_WRITE_T | MIPS16_INSN_READ_T))
2574 mips_gprmask |= 1 << TREG;
2575 if (pinfo & (MIPS16_INSN_WRITE_SP | MIPS16_INSN_READ_SP))
2576 mips_gprmask |= 1 << SP;
2577 if (pinfo & (MIPS16_INSN_WRITE_31 | MIPS16_INSN_READ_31))
2578 mips_gprmask |= 1 << RA;
2579 if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
2580 mips_gprmask |= 1 << MIPS16OP_EXTRACT_REG32R (ip->insn_opcode);
2581 if (pinfo & MIPS16_INSN_READ_Z)
2315 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_MOVE32Z)
2316 & MIPS16OP_MASK_MOVE32Z);
2582 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip);
2317 if (pinfo & MIPS16_INSN_READ_GPR_X)
2583 if (pinfo & MIPS16_INSN_READ_GPR_X)
2318 mips_gprmask |= 1 << ((ip->insn_opcode >> MIPS16OP_SH_REGR32)
2319 & MIPS16OP_MASK_REGR32);
2584 mips_gprmask |= 1 << MIPS16_EXTRACT_OPERAND (REGR32, *ip);
2320 }
2321
2322 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2323 {
2324 /* Filling the branch delay slot is more complex. We try to
2325 switch the branch with the previous instruction, which we can
2326 do if the previous instruction does not set up a condition
2327 that the branch tests and if the branch is not itself the
2328 target of any branch. */
2329 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2330 || (pinfo & INSN_COND_BRANCH_DELAY))
2331 {
2332 if (mips_optimize < 2
2333 /* If we have seen .set volatile or .set nomove, don't
2334 optimize. */
2335 || mips_opts.nomove != 0
2585 }
2586
2587 if (mips_relax.sequence != 2 && !mips_opts.noreorder)
2588 {
2589 /* Filling the branch delay slot is more complex. We try to
2590 switch the branch with the previous instruction, which we can
2591 do if the previous instruction does not set up a condition
2592 that the branch tests and if the branch is not itself the
2593 target of any branch. */
2594 if ((pinfo & INSN_UNCOND_BRANCH_DELAY)
2595 || (pinfo & INSN_COND_BRANCH_DELAY))
2596 {
2597 if (mips_optimize < 2
2598 /* If we have seen .set volatile or .set nomove, don't
2599 optimize. */
2600 || mips_opts.nomove != 0
2336 /* If we had to emit any NOP instructions, then we
2337 already know we can not swap. */
2338 || nops != 0
2339 /* If we don't even know the previous insn, we can not
2340 swap. */
2341 || ! prev_insn_valid
2342 /* If the previous insn is already in a branch delay
2343 slot, then we can not swap. */
2344 || prev_insn_is_delay_slot
2601 /* We can't swap if the previous instruction's position
2602 is fixed. */
2603 || history[0].fixed_p
2345 /* If the previous previous insn was in a .set
2346 noreorder, we can't swap. Actually, the MIPS
2347 assembler will swap in this situation. However, gcc
2348 configured -with-gnu-as will generate code like
2349 .set noreorder
2350 lw $4,XXX
2351 .set reorder
2352 INSN
2353 bne $4,$0,foo
2354 in which we can not swap the bne and INSN. If gcc is
2355 not configured -with-gnu-as, it does not output the
2604 /* If the previous previous insn was in a .set
2605 noreorder, we can't swap. Actually, the MIPS
2606 assembler will swap in this situation. However, gcc
2607 configured -with-gnu-as will generate code like
2608 .set noreorder
2609 lw $4,XXX
2610 .set reorder
2611 INSN
2612 bne $4,$0,foo
2613 in which we can not swap the bne and INSN. If gcc is
2614 not configured -with-gnu-as, it does not output the
2356 .set pseudo-ops. We don't have to check
2357 prev_insn_unreordered, because prev_insn_valid will
2358 be 0 in that case. We don't want to use
2359 prev_prev_insn_valid, because we do want to be able
2360 to swap at the start of a function. */
2361 || prev_prev_insn_unreordered
2615 .set pseudo-ops. */
2616 || history[1].noreorder_p
2362 /* If the branch is itself the target of a branch, we
2363 can not swap. We cheat on this; all we check for is
2364 whether there is a label on this instruction. If
2365 there are any branches to anything other than a
2366 label, users must use .set noreorder. */
2367 || insn_labels != NULL
2368 /* If the previous instruction is in a variant frag
2369 other than this branch's one, we cannot do the swap.
2370 This does not apply to the mips16, which uses variant
2371 frags for different purposes. */
2372 || (! mips_opts.mips16
2373 && prev_insn_frag_type == rs_machine_dependent)
2617 /* If the branch is itself the target of a branch, we
2618 can not swap. We cheat on this; all we check for is
2619 whether there is a label on this instruction. If
2620 there are any branches to anything other than a
2621 label, users must use .set noreorder. */
2622 || insn_labels != NULL
2623 /* If the previous instruction is in a variant frag
2624 other than this branch's one, we cannot do the swap.
2625 This does not apply to the mips16, which uses variant
2626 frags for different purposes. */
2627 || (! mips_opts.mips16
2628 && prev_insn_frag_type == rs_machine_dependent)
2374 /* If the branch reads the condition codes, we don't
2375 even try to swap, because in the sequence
2376 ctc1 $X,$31
2377 INSN
2378 INSN
2379 bc1t LABEL
2380 we can not swap, and I don't feel like handling that
2381 case. */
2382 || (! mips_opts.mips16
2383 && (pinfo & INSN_READ_COND_CODE)
2384 && ! cop_interlocks)
2385 /* We can not swap with an instruction that requires a
2386 delay slot, because the target of the branch might
2387 interfere with that instruction. */
2388 || (! mips_opts.mips16
2389 && (prev_pinfo
2390 /* Itbl support may require additional care here. */
2391 & (INSN_LOAD_COPROC_DELAY
2392 | INSN_COPROC_MOVE_DELAY
2393 | INSN_WRITE_COND_CODE))
2394 && ! cop_interlocks)
2395 || (! (hilo_interlocks
2396 || (mips_opts.arch == CPU_R3900 && (pinfo & INSN_MULT)))
2397 && (prev_pinfo
2398 & (INSN_READ_LO
2399 | INSN_READ_HI)))
2400 || (! mips_opts.mips16
2401 && (prev_pinfo & INSN_LOAD_MEMORY_DELAY)
2402 && ! gpr_interlocks)
2403 || (! mips_opts.mips16
2404 /* Itbl support may require additional care here. */
2405 && (prev_pinfo & INSN_COPROC_MEMORY_DELAY)
2406 && ! cop_mem_interlocks)
2407 /* We can not swap with a branch instruction. */
2408 || (prev_pinfo
2409 & (INSN_UNCOND_BRANCH_DELAY
2410 | INSN_COND_BRANCH_DELAY
2411 | INSN_COND_BRANCH_LIKELY))
2629 /* Check for conflicts between the branch and the instructions
2630 before the candidate delay slot. */
2631 || nops_for_insn (history + 1, ip) > 0
2632 /* Check for conflicts between the swapped sequence and the
2633 target of the branch. */
2634 || nops_for_sequence (2, history + 1, ip, history) > 0
2412 /* We do not swap with a trap instruction, since it
2413 complicates trap handlers to have the trap
2414 instruction be in a delay slot. */
2415 || (prev_pinfo & INSN_TRAP)
2416 /* If the branch reads a register that the previous
2417 instruction sets, we can not swap. */
2418 || (! mips_opts.mips16
2419 && (prev_pinfo & INSN_WRITE_GPR_T)
2635 /* We do not swap with a trap instruction, since it
2636 complicates trap handlers to have the trap
2637 instruction be in a delay slot. */
2638 || (prev_pinfo & INSN_TRAP)
2639 /* If the branch reads a register that the previous
2640 instruction sets, we can not swap. */
2641 || (! mips_opts.mips16
2642 && (prev_pinfo & INSN_WRITE_GPR_T)
2420 && insn_uses_reg (ip,
2421 ((prev_insn.insn_opcode >> OP_SH_RT)
2422 & OP_MASK_RT),
2643 && insn_uses_reg (ip, EXTRACT_OPERAND (RT, history[0]),
2423 MIPS_GR_REG))
2424 || (! mips_opts.mips16
2425 && (prev_pinfo & INSN_WRITE_GPR_D)
2644 MIPS_GR_REG))
2645 || (! mips_opts.mips16
2646 && (prev_pinfo & INSN_WRITE_GPR_D)
2426 && insn_uses_reg (ip,
2427 ((prev_insn.insn_opcode >> OP_SH_RD)
2428 & OP_MASK_RD),
2647 && insn_uses_reg (ip, EXTRACT_OPERAND (RD, history[0]),
2429 MIPS_GR_REG))
2430 || (mips_opts.mips16
2431 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2648 MIPS_GR_REG))
2649 || (mips_opts.mips16
2650 && (((prev_pinfo & MIPS16_INSN_WRITE_X)
2432 && insn_uses_reg (ip,
2433 ((prev_insn.insn_opcode
2434 >> MIPS16OP_SH_RX)
2435 & MIPS16OP_MASK_RX),
2436 MIPS16_REG))
2651 && (insn_uses_reg
2652 (ip, MIPS16_EXTRACT_OPERAND (RX, history[0]),
2653 MIPS16_REG)))
2437 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2654 || ((prev_pinfo & MIPS16_INSN_WRITE_Y)
2438 && insn_uses_reg (ip,
2439 ((prev_insn.insn_opcode
2440 >> MIPS16OP_SH_RY)
2441 & MIPS16OP_MASK_RY),
2442 MIPS16_REG))
2655 && (insn_uses_reg
2656 (ip, MIPS16_EXTRACT_OPERAND (RY, history[0]),
2657 MIPS16_REG)))
2443 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2658 || ((prev_pinfo & MIPS16_INSN_WRITE_Z)
2444 && insn_uses_reg (ip,
2445 ((prev_insn.insn_opcode
2446 >> MIPS16OP_SH_RZ)
2447 & MIPS16OP_MASK_RZ),
2448 MIPS16_REG))
2659 && (insn_uses_reg
2660 (ip, MIPS16_EXTRACT_OPERAND (RZ, history[0]),
2661 MIPS16_REG)))
2449 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2450 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2451 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2452 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2453 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2454 && insn_uses_reg (ip,
2662 || ((prev_pinfo & MIPS16_INSN_WRITE_T)
2663 && insn_uses_reg (ip, TREG, MIPS_GR_REG))
2664 || ((prev_pinfo & MIPS16_INSN_WRITE_31)
2665 && insn_uses_reg (ip, RA, MIPS_GR_REG))
2666 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2667 && insn_uses_reg (ip,
2455 MIPS16OP_EXTRACT_REG32R (prev_insn.
2456 insn_opcode),
2668 MIPS16OP_EXTRACT_REG32R
2669 (history[0].insn_opcode),
2457 MIPS_GR_REG))))
2458 /* If the branch writes a register that the previous
2459 instruction sets, we can not swap (we know that
2460 branches write only to RD or to $31). */
2461 || (! mips_opts.mips16
2462 && (prev_pinfo & INSN_WRITE_GPR_T)
2463 && (((pinfo & INSN_WRITE_GPR_D)
2670 MIPS_GR_REG))))
2671 /* If the branch writes a register that the previous
2672 instruction sets, we can not swap (we know that
2673 branches write only to RD or to $31). */
2674 || (! mips_opts.mips16
2675 && (prev_pinfo & INSN_WRITE_GPR_T)
2676 && (((pinfo & INSN_WRITE_GPR_D)
2464 && (((prev_insn.insn_opcode >> OP_SH_RT) & OP_MASK_RT)
2465 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2677 && (EXTRACT_OPERAND (RT, history[0])
2678 == EXTRACT_OPERAND (RD, *ip)))
2466 || ((pinfo & INSN_WRITE_GPR_31)
2679 || ((pinfo & INSN_WRITE_GPR_31)
2467 && (((prev_insn.insn_opcode >> OP_SH_RT)
2468 & OP_MASK_RT)
2469 == RA))))
2680 && EXTRACT_OPERAND (RT, history[0]) == RA)))
2470 || (! mips_opts.mips16
2471 && (prev_pinfo & INSN_WRITE_GPR_D)
2472 && (((pinfo & INSN_WRITE_GPR_D)
2681 || (! mips_opts.mips16
2682 && (prev_pinfo & INSN_WRITE_GPR_D)
2683 && (((pinfo & INSN_WRITE_GPR_D)
2473 && (((prev_insn.insn_opcode >> OP_SH_RD) & OP_MASK_RD)
2474 == ((ip->insn_opcode >> OP_SH_RD) & OP_MASK_RD)))
2684 && (EXTRACT_OPERAND (RD, history[0])
2685 == EXTRACT_OPERAND (RD, *ip)))
2475 || ((pinfo & INSN_WRITE_GPR_31)
2686 || ((pinfo & INSN_WRITE_GPR_31)
2476 && (((prev_insn.insn_opcode >> OP_SH_RD)
2477 & OP_MASK_RD)
2478 == RA))))
2687 && EXTRACT_OPERAND (RD, history[0]) == RA)))
2479 || (mips_opts.mips16
2480 && (pinfo & MIPS16_INSN_WRITE_31)
2481 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2482 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2688 || (mips_opts.mips16
2689 && (pinfo & MIPS16_INSN_WRITE_31)
2690 && ((prev_pinfo & MIPS16_INSN_WRITE_31)
2691 || ((prev_pinfo & MIPS16_INSN_WRITE_GPR_Y)
2483 && (MIPS16OP_EXTRACT_REG32R (prev_insn.insn_opcode)
2692 && (MIPS16OP_EXTRACT_REG32R (history[0].insn_opcode)
2484 == RA))))
2485 /* If the branch writes a register that the previous
2486 instruction reads, we can not swap (we know that
2487 branches only write to RD or to $31). */
2488 || (! mips_opts.mips16
2489 && (pinfo & INSN_WRITE_GPR_D)
2693 == RA))))
2694 /* If the branch writes a register that the previous
2695 instruction reads, we can not swap (we know that
2696 branches only write to RD or to $31). */
2697 || (! mips_opts.mips16
2698 && (pinfo & INSN_WRITE_GPR_D)
2490 && insn_uses_reg (&prev_insn,
2491 ((ip->insn_opcode >> OP_SH_RD)
2492 & OP_MASK_RD),
2699 && insn_uses_reg (&history[0],
2700 EXTRACT_OPERAND (RD, *ip),
2493 MIPS_GR_REG))
2494 || (! mips_opts.mips16
2495 && (pinfo & INSN_WRITE_GPR_31)
2701 MIPS_GR_REG))
2702 || (! mips_opts.mips16
2703 && (pinfo & INSN_WRITE_GPR_31)
2496 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2704 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
2497 || (mips_opts.mips16
2498 && (pinfo & MIPS16_INSN_WRITE_31)
2705 || (mips_opts.mips16
2706 && (pinfo & MIPS16_INSN_WRITE_31)
2499 && insn_uses_reg (&prev_insn, RA, MIPS_GR_REG))
2500 /* If we are generating embedded PIC code, the branch
2501 might be expanded into a sequence which uses $at, so
2502 we can't swap with an instruction which reads it. */
2503 || (mips_pic == EMBEDDED_PIC
2504 && insn_uses_reg (&prev_insn, AT, MIPS_GR_REG))
2505 /* If the previous previous instruction has a load
2506 delay, and sets a register that the branch reads, we
2507 can not swap. */
2508 || (! mips_opts.mips16
2509 /* Itbl support may require additional care here. */
2510 && (((prev_prev_insn.insn_mo->pinfo & INSN_LOAD_COPROC_DELAY)
2511 && ! cop_interlocks)
2512 || ((prev_prev_insn.insn_mo->pinfo
2513 & INSN_LOAD_MEMORY_DELAY)
2514 && ! gpr_interlocks))
2515 && insn_uses_reg (ip,
2516 ((prev_prev_insn.insn_opcode >> OP_SH_RT)
2517 & OP_MASK_RT),
2518 MIPS_GR_REG))
2707 && insn_uses_reg (&history[0], RA, MIPS_GR_REG))
2519 /* If one instruction sets a condition code and the
2520 other one uses a condition code, we can not swap. */
2521 || ((pinfo & INSN_READ_COND_CODE)
2522 && (prev_pinfo & INSN_WRITE_COND_CODE))
2523 || ((pinfo & INSN_WRITE_COND_CODE)
2524 && (prev_pinfo & INSN_READ_COND_CODE))
2525 /* If the previous instruction uses the PC, we can not
2526 swap. */
2527 || (mips_opts.mips16
2528 && (prev_pinfo & MIPS16_INSN_READ_PC))
2708 /* If one instruction sets a condition code and the
2709 other one uses a condition code, we can not swap. */
2710 || ((pinfo & INSN_READ_COND_CODE)
2711 && (prev_pinfo & INSN_WRITE_COND_CODE))
2712 || ((pinfo & INSN_WRITE_COND_CODE)
2713 && (prev_pinfo & INSN_READ_COND_CODE))
2714 /* If the previous instruction uses the PC, we can not
2715 swap. */
2716 || (mips_opts.mips16
2717 && (prev_pinfo & MIPS16_INSN_READ_PC))
2529 /* If the previous instruction was extended, we can not
2530 swap. */
2531 || (mips_opts.mips16 && prev_insn_extended)
2532 /* If the previous instruction had a fixup in mips16
2533 mode, we can not swap. This normally means that the
2534 previous instruction was a 4 byte branch anyhow. */
2718 /* If the previous instruction had a fixup in mips16
2719 mode, we can not swap. This normally means that the
2720 previous instruction was a 4 byte branch anyhow. */
2535 || (mips_opts.mips16 && prev_insn_fixp[0])
2721 || (mips_opts.mips16 && history[0].fixp[0])
2536 /* If the previous instruction is a sync, sync.l, or
2537 sync.p, we can not swap. */
2538 || (prev_pinfo & INSN_SYNC))
2539 {
2722 /* If the previous instruction is a sync, sync.l, or
2723 sync.p, we can not swap. */
2724 || (prev_pinfo & INSN_SYNC))
2725 {
2540 /* We could do even better for unconditional branches to
2541 portions of this object file; we could pick up the
2542 instruction at the destination, put it in the delay
2543 slot, and bump the destination address. */
2544 emit_nop ();
2545 /* Update the previous insn information. */
2546 prev_prev_insn = *ip;
2547 prev_insn.insn_mo = &dummy_opcode;
2726 if (mips_opts.mips16
2727 && (pinfo & INSN_UNCOND_BRANCH_DELAY)
2728 && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31))
2729 && (mips_opts.isa == ISA_MIPS32
2730 || mips_opts.isa == ISA_MIPS32R2
2731 || mips_opts.isa == ISA_MIPS64
2732 || mips_opts.isa == ISA_MIPS64R2))
2733 {
2734 /* Convert MIPS16 jr/jalr into a "compact" jump. */
2735 ip->insn_opcode |= 0x0080;
2736 install_insn (ip);
2737 insert_into_history (0, 1, ip);
2738 }
2739 else
2740 {
2741 /* We could do even better for unconditional branches to
2742 portions of this object file; we could pick up the
2743 instruction at the destination, put it in the delay
2744 slot, and bump the destination address. */
2745 insert_into_history (0, 1, ip);
2746 emit_nop ();
2747 }
2748
2749 if (mips_relax.sequence)
2750 mips_relax.sizes[mips_relax.sequence - 1] += 4;
2548 }
2549 else
2550 {
2551 /* It looks like we can actually do the swap. */
2751 }
2752 else
2753 {
2754 /* It looks like we can actually do the swap. */
2552 if (! mips_opts.mips16)
2755 struct mips_cl_insn delay = history[0];
2756 if (mips_opts.mips16)
2553 {
2757 {
2554 char *prev_f;
2555 char temp[4];
2556
2557 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2558 if (!relaxed_branch)
2559 {
2560 /* If this is not a relaxed branch, then just
2561 swap the instructions. */
2562 memcpy (temp, prev_f, 4);
2563 memcpy (prev_f, f, 4);
2564 memcpy (f, temp, 4);
2565 }
2566 else
2567 {
2568 /* If this is a relaxed branch, then we move the
2569 instruction to be placed in the delay slot to
2570 the current frag, shrinking the fixed part of
2571 the originating frag. If the branch occupies
2572 the tail of the latter, we move it backwards,
2573 into the space freed by the moved instruction. */
2574 f = frag_more (4);
2575 memcpy (f, prev_f, 4);
2576 prev_insn_frag->fr_fix -= 4;
2577 if (prev_insn_frag->fr_type == rs_machine_dependent)
2578 memmove (prev_f, prev_f + 4, prev_insn_frag->fr_var);
2579 }
2580
2581 if (prev_insn_fixp[0])
2582 {
2583 prev_insn_fixp[0]->fx_frag = frag_now;
2584 prev_insn_fixp[0]->fx_where = f - frag_now->fr_literal;
2585 }
2586 if (prev_insn_fixp[1])
2587 {
2588 prev_insn_fixp[1]->fx_frag = frag_now;
2589 prev_insn_fixp[1]->fx_where = f - frag_now->fr_literal;
2590 }
2591 if (prev_insn_fixp[2])
2592 {
2593 prev_insn_fixp[2]->fx_frag = frag_now;
2594 prev_insn_fixp[2]->fx_where = f - frag_now->fr_literal;
2595 }
2596 if (prev_insn_fixp[0] && HAVE_NEWABI
2597 && prev_insn_frag != frag_now
2598 && (prev_insn_fixp[0]->fx_r_type
2599 == BFD_RELOC_MIPS_GOT_DISP
2600 || (prev_insn_fixp[0]->fx_r_type
2601 == BFD_RELOC_MIPS_CALL16)))
2602 {
2603 /* To avoid confusion in tc_gen_reloc, we must
2604 ensure that this does not become a variant
2605 frag. */
2606 force_new_frag = TRUE;
2607 }
2608
2609 if (!relaxed_branch)
2610 {
2611 if (fixp[0])
2612 {
2613 fixp[0]->fx_frag = prev_insn_frag;
2614 fixp[0]->fx_where = prev_insn_where;
2615 }
2616 if (fixp[1])
2617 {
2618 fixp[1]->fx_frag = prev_insn_frag;
2619 fixp[1]->fx_where = prev_insn_where;
2620 }
2621 if (fixp[2])
2622 {
2623 fixp[2]->fx_frag = prev_insn_frag;
2624 fixp[2]->fx_where = prev_insn_where;
2625 }
2626 }
2627 else if (prev_insn_frag->fr_type == rs_machine_dependent)
2628 {
2629 if (fixp[0])
2630 fixp[0]->fx_where -= 4;
2631 if (fixp[1])
2632 fixp[1]->fx_where -= 4;
2633 if (fixp[2])
2634 fixp[2]->fx_where -= 4;
2635 }
2758 know (delay.frag == ip->frag);
2759 move_insn (ip, delay.frag, delay.where);
2760 move_insn (&delay, ip->frag, ip->where + insn_length (ip));
2636 }
2761 }
2762 else if (relaxed_branch)
2763 {
2764 /* Add the delay slot instruction to the end of the
2765 current frag and shrink the fixed part of the
2766 original frag. If the branch occupies the tail of
2767 the latter, move it backwards to cover the gap. */
2768 delay.frag->fr_fix -= 4;
2769 if (delay.frag == ip->frag)
2770 move_insn (ip, ip->frag, ip->where - 4);
2771 add_fixed_insn (&delay);
2772 }
2637 else
2638 {
2773 else
2774 {
2639 char *prev_f;
2640 char temp[2];
2641
2642 assert (prev_insn_fixp[0] == NULL);
2643 assert (prev_insn_fixp[1] == NULL);
2644 assert (prev_insn_fixp[2] == NULL);
2645 prev_f = prev_insn_frag->fr_literal + prev_insn_where;
2646 memcpy (temp, prev_f, 2);
2647 memcpy (prev_f, f, 2);
2648 if (*reloc_type != BFD_RELOC_MIPS16_JMP)
2649 {
2650 assert (*reloc_type == BFD_RELOC_UNUSED);
2651 memcpy (f, temp, 2);
2652 }
2653 else
2654 {
2655 memcpy (f, f + 2, 2);
2656 memcpy (f + 2, temp, 2);
2657 }
2658 if (fixp[0])
2659 {
2660 fixp[0]->fx_frag = prev_insn_frag;
2661 fixp[0]->fx_where = prev_insn_where;
2662 }
2663 if (fixp[1])
2664 {
2665 fixp[1]->fx_frag = prev_insn_frag;
2666 fixp[1]->fx_where = prev_insn_where;
2667 }
2668 if (fixp[2])
2669 {
2670 fixp[2]->fx_frag = prev_insn_frag;
2671 fixp[2]->fx_where = prev_insn_where;
2672 }
2775 move_insn (&delay, ip->frag, ip->where);
2776 move_insn (ip, history[0].frag, history[0].where);
2673 }
2777 }
2674
2675 /* Update the previous insn information; leave prev_insn
2676 unchanged. */
2677 prev_prev_insn = *ip;
2778 history[0] = *ip;
2779 delay.fixed_p = 1;
2780 insert_into_history (0, 1, &delay);
2678 }
2781 }
2679 prev_insn_is_delay_slot = 1;
2680
2681 /* If that was an unconditional branch, forget the previous
2682 insn information. */
2683 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2782
2783 /* If that was an unconditional branch, forget the previous
2784 insn information. */
2785 if (pinfo & INSN_UNCOND_BRANCH_DELAY)
2684 {
2685 prev_prev_insn.insn_mo = &dummy_opcode;
2686 prev_insn.insn_mo = &dummy_opcode;
2687 }
2688
2689 prev_insn_fixp[0] = NULL;
2690 prev_insn_fixp[1] = NULL;
2691 prev_insn_fixp[2] = NULL;
2692 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2693 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2694 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2695 prev_insn_extended = 0;
2786 mips_no_prev_insn ();
2696 }
2697 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2698 {
2699 /* We don't yet optimize a branch likely. What we should do
2700 is look at the target, copy the instruction found there
2701 into the delay slot, and increment the branch to jump to
2702 the next instruction. */
2787 }
2788 else if (pinfo & INSN_COND_BRANCH_LIKELY)
2789 {
2790 /* We don't yet optimize a branch likely. What we should do
2791 is look at the target, copy the instruction found there
2792 into the delay slot, and increment the branch to jump to
2793 the next instruction. */
2794 insert_into_history (0, 1, ip);
2703 emit_nop ();
2795 emit_nop ();
2704 /* Update the previous insn information. */
2705 prev_prev_insn = *ip;
2706 prev_insn.insn_mo = &dummy_opcode;
2707 prev_insn_fixp[0] = NULL;
2708 prev_insn_fixp[1] = NULL;
2709 prev_insn_fixp[2] = NULL;
2710 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2711 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2712 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2713 prev_insn_extended = 0;
2714 }
2715 else
2796 }
2797 else
2716 {
2717 /* Update the previous insn information. */
2718 if (nops > 0)
2719 prev_prev_insn.insn_mo = &dummy_opcode;
2720 else
2721 prev_prev_insn = prev_insn;
2722 prev_insn = *ip;
2723
2724 /* Any time we see a branch, we always fill the delay slot
2725 immediately; since this insn is not a branch, we know it
2726 is not in a delay slot. */
2727 prev_insn_is_delay_slot = 0;
2728
2729 prev_insn_fixp[0] = fixp[0];
2730 prev_insn_fixp[1] = fixp[1];
2731 prev_insn_fixp[2] = fixp[2];
2732 prev_insn_reloc_type[0] = reloc_type[0];
2733 prev_insn_reloc_type[1] = reloc_type[1];
2734 prev_insn_reloc_type[2] = reloc_type[2];
2735 if (mips_opts.mips16)
2736 prev_insn_extended = (ip->use_extend
2737 || *reloc_type > BFD_RELOC_UNUSED);
2738 }
2739
2740 prev_prev_insn_unreordered = prev_insn_unreordered;
2741 prev_insn_unreordered = 0;
2742 prev_insn_frag = frag_now;
2743 prev_insn_where = f - frag_now->fr_literal;
2744 prev_insn_valid = 1;
2798 insert_into_history (0, 1, ip);
2745 }
2799 }
2746 else if (mips_relax.sequence != 2)
2747 {
2748 /* We need to record a bit of information even when we are not
2749 reordering, in order to determine the base address for mips16
2750 PC relative relocs. */
2751 prev_prev_insn = prev_insn;
2752 prev_insn = *ip;
2753 prev_insn_reloc_type[0] = reloc_type[0];
2754 prev_insn_reloc_type[1] = reloc_type[1];
2755 prev_insn_reloc_type[2] = reloc_type[2];
2756 prev_prev_insn_unreordered = prev_insn_unreordered;
2757 prev_insn_unreordered = 1;
2758 }
2800 else
2801 insert_into_history (0, 1, ip);
2759
2760 /* We just output an insn, so the next one doesn't have a label. */
2761 mips_clear_insn_labels ();
2762}
2763
2802
2803 /* We just output an insn, so the next one doesn't have a label. */
2804 mips_clear_insn_labels ();
2805}
2806
2764/* This function forgets that there was any previous instruction or
2765 label. If PRESERVE is non-zero, it remembers enough information to
2766 know whether nops are needed before a noreorder section. */
2807/* Forget that there was any previous instruction or label. */
2767
2768static void
2808
2809static void
2769mips_no_prev_insn (int preserve)
2810mips_no_prev_insn (void)
2770{
2811{
2771 if (! preserve)
2772 {
2773 prev_insn.insn_mo = &dummy_opcode;
2774 prev_prev_insn.insn_mo = &dummy_opcode;
2775 prev_nop_frag = NULL;
2776 prev_nop_frag_holds = 0;
2777 prev_nop_frag_required = 0;
2778 prev_nop_frag_since = 0;
2779 }
2780 prev_insn_valid = 0;
2781 prev_insn_is_delay_slot = 0;
2782 prev_insn_unreordered = 0;
2783 prev_insn_extended = 0;
2784 prev_insn_reloc_type[0] = BFD_RELOC_UNUSED;
2785 prev_insn_reloc_type[1] = BFD_RELOC_UNUSED;
2786 prev_insn_reloc_type[2] = BFD_RELOC_UNUSED;
2787 prev_prev_insn_unreordered = 0;
2812 prev_nop_frag = NULL;
2813 insert_into_history (0, ARRAY_SIZE (history), NOP_INSN);
2788 mips_clear_insn_labels ();
2789}
2790
2814 mips_clear_insn_labels ();
2815}
2816
2791/* This function must be called whenever we turn on noreorder or emit
2792 something other than instructions. It inserts any NOPS which might
2793 be needed by the previous instruction, and clears the information
2794 kept for the previous instructions. The INSNS parameter is true if
2795 instructions are to follow. */
2817/* This function must be called before we emit something other than
2818 instructions. It is like mips_no_prev_insn except that it inserts
2819 any NOPS that might be needed by previous instructions. */
2796
2820
2797static void
2798mips_emit_delays (bfd_boolean insns)
2821void
2822mips_emit_delays (void)
2799{
2800 if (! mips_opts.noreorder)
2801 {
2823{
2824 if (! mips_opts.noreorder)
2825 {
2802 int nops;
2803
2804 nops = 0;
2805 if ((! mips_opts.mips16
2806 && ((prev_insn.insn_mo->pinfo
2807 & (INSN_LOAD_COPROC_DELAY
2808 | INSN_COPROC_MOVE_DELAY
2809 | INSN_WRITE_COND_CODE))
2810 && ! cop_interlocks))
2811 || (! hilo_interlocks
2812 && (prev_insn.insn_mo->pinfo
2813 & (INSN_READ_LO
2814 | INSN_READ_HI)))
2815 || (! mips_opts.mips16
2816 && (prev_insn.insn_mo->pinfo & INSN_LOAD_MEMORY_DELAY)
2817 && ! gpr_interlocks)
2818 || (! mips_opts.mips16
2819 && (prev_insn.insn_mo->pinfo & INSN_COPROC_MEMORY_DELAY)
2820 && ! cop_mem_interlocks))
2826 int nops = nops_for_insn (history, NULL);
2827 if (nops > 0)
2821 {
2828 {
2822 /* Itbl support may require additional care here. */
2823 ++nops;
2824 if ((! mips_opts.mips16
2825 && ((prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2826 && ! cop_interlocks))
2827 || (! hilo_interlocks
2828 && ((prev_insn.insn_mo->pinfo & INSN_READ_HI)
2829 || (prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2830 ++nops;
2831
2832 if (prev_insn_unreordered)
2833 nops = 0;
2829 while (nops-- > 0)
2830 add_fixed_insn (NOP_INSN);
2831 mips_move_labels ();
2834 }
2832 }
2835 else if ((! mips_opts.mips16
2836 && ((prev_prev_insn.insn_mo->pinfo & INSN_WRITE_COND_CODE)
2837 && ! cop_interlocks))
2838 || (! hilo_interlocks
2839 && ((prev_prev_insn.insn_mo->pinfo & INSN_READ_HI)
2840 || (prev_prev_insn.insn_mo->pinfo & INSN_READ_LO))))
2841 {
2842 /* Itbl support may require additional care here. */
2843 if (! prev_prev_insn_unreordered)
2844 ++nops;
2845 }
2833 }
2834 mips_no_prev_insn ();
2835}
2846
2836
2847 if (mips_fix_vr4120 && prev_insn.insn_mo->name)
2848 {
2849 int min_nops = 0;
2850 const char *pn = prev_insn.insn_mo->name;
2851 if (strncmp(pn, "macc", 4) == 0
2852 || strncmp(pn, "dmacc", 5) == 0
2853 || strncmp(pn, "dmult", 5) == 0)
2854 {
2855 min_nops = 1;
2856 }
2857 if (nops < min_nops)
2858 nops = min_nops;
2859 }
2837/* Start a (possibly nested) noreorder block. */
2860
2838
2839static void
2840start_noreorder (void)
2841{
2842 if (mips_opts.noreorder == 0)
2843 {
2844 unsigned int i;
2845 int nops;
2846
2847 /* None of the instructions before the .set noreorder can be moved. */
2848 for (i = 0; i < ARRAY_SIZE (history); i++)
2849 history[i].fixed_p = 1;
2850
2851 /* Insert any nops that might be needed between the .set noreorder
2852 block and the previous instructions. We will later remove any
2853 nops that turn out not to be needed. */
2854 nops = nops_for_insn (history, NULL);
2861 if (nops > 0)
2862 {
2855 if (nops > 0)
2856 {
2863 struct insn_label_list *l;
2864
2865 if (insns)
2857 if (mips_optimize != 0)
2866 {
2867 /* Record the frag which holds the nop instructions, so
2868 that we can remove them if we don't need them. */
2869 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2870 prev_nop_frag = frag_now;
2871 prev_nop_frag_holds = nops;
2872 prev_nop_frag_required = 0;
2873 prev_nop_frag_since = 0;
2874 }
2875
2876 for (; nops > 0; --nops)
2858 {
2859 /* Record the frag which holds the nop instructions, so
2860 that we can remove them if we don't need them. */
2861 frag_grow (mips_opts.mips16 ? nops * 2 : nops * 4);
2862 prev_nop_frag = frag_now;
2863 prev_nop_frag_holds = nops;
2864 prev_nop_frag_required = 0;
2865 prev_nop_frag_since = 0;
2866 }
2867
2868 for (; nops > 0; --nops)
2877 emit_nop ();
2869 add_fixed_insn (NOP_INSN);
2878
2870
2879 if (insns)
2880 {
2881 /* Move on to a new frag, so that it is safe to simply
2882 decrease the size of prev_nop_frag. */
2883 frag_wane (frag_now);
2884 frag_new (0);
2885 }
2886
2887 for (l = insn_labels; l != NULL; l = l->next)
2888 {
2889 valueT val;
2890
2891 assert (S_GET_SEGMENT (l->label) == now_seg);
2892 symbol_set_frag (l->label, frag_now);
2893 val = (valueT) frag_now_fix ();
2894 /* mips16 text labels are stored as odd. */
2895 if (mips_opts.mips16)
2896 ++val;
2897 S_SET_VALUE (l->label, val);
2898 }
2871 /* Move on to a new frag, so that it is safe to simply
2872 decrease the size of prev_nop_frag. */
2873 frag_wane (frag_now);
2874 frag_new (0);
2875 mips_move_labels ();
2899 }
2876 }
2877 mips16_mark_labels ();
2878 mips_clear_insn_labels ();
2900 }
2879 }
2880 mips_opts.noreorder++;
2881 mips_any_noreorder = 1;
2882}
2901
2883
2902 /* Mark instruction labels in mips16 mode. */
2903 if (insns)
2904 mips16_mark_labels ();
2884/* End a nested noreorder block. */
2905
2885
2906 mips_no_prev_insn (insns);
2886static void
2887end_noreorder (void)
2888{
2889 mips_opts.noreorder--;
2890 if (mips_opts.noreorder == 0 && prev_nop_frag != NULL)
2891 {
2892 /* Commit to inserting prev_nop_frag_required nops and go back to
2893 handling nop insertion the .set reorder way. */
2894 prev_nop_frag->fr_fix -= ((prev_nop_frag_holds - prev_nop_frag_required)
2895 * (mips_opts.mips16 ? 2 : 4));
2896 insert_into_history (prev_nop_frag_since,
2897 prev_nop_frag_required, NOP_INSN);
2898 prev_nop_frag = NULL;
2899 }
2907}
2908
2909/* Set up global variables for the start of a new macro. */
2910
2911static void
2912macro_start (void)
2913{
2914 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2915 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2900}
2901
2902/* Set up global variables for the start of a new macro. */
2903
2904static void
2905macro_start (void)
2906{
2907 memset (&mips_macro_warning.sizes, 0, sizeof (mips_macro_warning.sizes));
2908 mips_macro_warning.delay_slot_p = (mips_opts.noreorder
2916 && (prev_insn.insn_mo->pinfo
2909 && (history[0].insn_mo->pinfo
2917 & (INSN_UNCOND_BRANCH_DELAY
2918 | INSN_COND_BRANCH_DELAY
2919 | INSN_COND_BRANCH_LIKELY)) != 0);
2920}
2921
2922/* Given that a macro is longer than 4 bytes, return the appropriate warning
2923 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2924 RELAX_DELAY_SLOT and RELAX_NOMACRO. */

--- 41 unchanged lines hidden (view full) ---

2966 {
2967 /* One implementation might need a warning but the other
2968 definitely doesn't. */
2969 mips_macro_warning.first_frag->fr_subtype |= subtype;
2970 }
2971 }
2972}
2973
2910 & (INSN_UNCOND_BRANCH_DELAY
2911 | INSN_COND_BRANCH_DELAY
2912 | INSN_COND_BRANCH_LIKELY)) != 0);
2913}
2914
2915/* Given that a macro is longer than 4 bytes, return the appropriate warning
2916 for it. Return null if no warning is needed. SUBTYPE is a bitmask of
2917 RELAX_DELAY_SLOT and RELAX_NOMACRO. */

--- 41 unchanged lines hidden (view full) ---

2959 {
2960 /* One implementation might need a warning but the other
2961 definitely doesn't. */
2962 mips_macro_warning.first_frag->fr_subtype |= subtype;
2963 }
2964 }
2965}
2966
2967/* Read a macro's relocation codes from *ARGS and store them in *R.
2968 The first argument in *ARGS will be either the code for a single
2969 relocation or -1 followed by the three codes that make up a
2970 composite relocation. */
2971
2972static void
2973macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
2974{
2975 int i, next;
2976
2977 next = va_arg (*args, int);
2978 if (next >= 0)
2979 r[0] = (bfd_reloc_code_real_type) next;
2980 else
2981 for (i = 0; i < 3; i++)
2982 r[i] = (bfd_reloc_code_real_type) va_arg (*args, int);
2983}
2984
2974/* Build an instruction created by a macro expansion. This is passed
2975 a pointer to the count of instructions created so far, an
2976 expression, the name of the instruction to build, an operand format
2977 string, and corresponding arguments. */
2978
2979static void
2980macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2981{
2985/* Build an instruction created by a macro expansion. This is passed
2986 a pointer to the count of instructions created so far, an
2987 expression, the name of the instruction to build, an operand format
2988 string, and corresponding arguments. */
2989
2990static void
2991macro_build (expressionS *ep, const char *name, const char *fmt, ...)
2992{
2993 const struct mips_opcode *mo;
2982 struct mips_cl_insn insn;
2983 bfd_reloc_code_real_type r[3];
2984 va_list args;
2985
2986 va_start (args, fmt);
2987
2988 if (mips_opts.mips16)
2989 {
2990 mips16_macro_build (ep, name, fmt, args);
2991 va_end (args);
2992 return;
2993 }
2994
2995 r[0] = BFD_RELOC_UNUSED;
2996 r[1] = BFD_RELOC_UNUSED;
2997 r[2] = BFD_RELOC_UNUSED;
2994 struct mips_cl_insn insn;
2995 bfd_reloc_code_real_type r[3];
2996 va_list args;
2997
2998 va_start (args, fmt);
2999
3000 if (mips_opts.mips16)
3001 {
3002 mips16_macro_build (ep, name, fmt, args);
3003 va_end (args);
3004 return;
3005 }
3006
3007 r[0] = BFD_RELOC_UNUSED;
3008 r[1] = BFD_RELOC_UNUSED;
3009 r[2] = BFD_RELOC_UNUSED;
2998 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
2999 assert (insn.insn_mo);
3000 assert (strcmp (name, insn.insn_mo->name) == 0);
3010 mo = (struct mips_opcode *) hash_find (op_hash, name);
3011 assert (mo);
3012 assert (strcmp (name, mo->name) == 0);
3001
3013
3002 /* Search until we get a match for NAME. */
3003 while (1)
3004 {
3005 /* It is assumed here that macros will never generate
3006 MDMX or MIPS-3D instructions. */
3007 if (strcmp (fmt, insn.insn_mo->args) == 0
3008 && insn.insn_mo->pinfo != INSN_MACRO
3009 && OPCODE_IS_MEMBER (insn.insn_mo,
3010 (mips_opts.isa
3011 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3014 /* Search until we get a match for NAME. It is assumed here that
3015 macros will never generate MDMX or MIPS-3D instructions. */
3016 while (strcmp (fmt, mo->args) != 0
3017 || mo->pinfo == INSN_MACRO
3018 || !OPCODE_IS_MEMBER (mo,
3019 (mips_opts.isa
3020 | (file_ase_mips16 ? INSN_MIPS16 : 0)),
3012 mips_opts.arch)
3021 mips_opts.arch)
3013 && (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
3014 break;
3015
3016 ++insn.insn_mo;
3017 assert (insn.insn_mo->name);
3018 assert (strcmp (name, insn.insn_mo->name) == 0);
3022 || (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
3023 {
3024 ++mo;
3025 assert (mo->name);
3026 assert (strcmp (name, mo->name) == 0);
3019 }
3020
3027 }
3028
3021 insn.insn_opcode = insn.insn_mo->match;
3029 create_insn (&insn, mo);
3022 for (;;)
3023 {
3024 switch (*fmt++)
3025 {
3026 case '\0':
3027 break;
3028
3029 case ',':
3030 case '(':
3031 case ')':
3032 continue;
3033
3034 case '+':
3035 switch (*fmt++)
3036 {
3037 case 'A':
3038 case 'E':
3030 for (;;)
3031 {
3032 switch (*fmt++)
3033 {
3034 case '\0':
3035 break;
3036
3037 case ',':
3038 case '(':
3039 case ')':
3040 continue;
3041
3042 case '+':
3043 switch (*fmt++)
3044 {
3045 case 'A':
3046 case 'E':
3039 insn.insn_opcode |= (va_arg (args, int)
3040 & OP_MASK_SHAMT) << OP_SH_SHAMT;
3047 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3041 continue;
3042
3043 case 'B':
3044 case 'F':
3045 /* Note that in the macro case, these arguments are already
3046 in MSB form. (When handling the instruction in the
3047 non-macro case, these arguments are sizes from which
3048 MSB values must be calculated.) */
3048 continue;
3049
3050 case 'B':
3051 case 'F':
3052 /* Note that in the macro case, these arguments are already
3053 in MSB form. (When handling the instruction in the
3054 non-macro case, these arguments are sizes from which
3055 MSB values must be calculated.) */
3049 insn.insn_opcode |= (va_arg (args, int)
3050 & OP_MASK_INSMSB) << OP_SH_INSMSB;
3056 INSERT_OPERAND (INSMSB, insn, va_arg (args, int));
3051 continue;
3052
3053 case 'C':
3054 case 'G':
3055 case 'H':
3056 /* Note that in the macro case, these arguments are already
3057 in MSBD form. (When handling the instruction in the
3058 non-macro case, these arguments are sizes from which
3059 MSBD values must be calculated.) */
3057 continue;
3058
3059 case 'C':
3060 case 'G':
3061 case 'H':
3062 /* Note that in the macro case, these arguments are already
3063 in MSBD form. (When handling the instruction in the
3064 non-macro case, these arguments are sizes from which
3065 MSBD values must be calculated.) */
3060 insn.insn_opcode |= (va_arg (args, int)
3061 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
3066 INSERT_OPERAND (EXTMSBD, insn, va_arg (args, int));
3062 continue;
3063
3064 default:
3065 internalError ();
3066 }
3067 continue;
3068
3069 case 't':
3070 case 'w':
3071 case 'E':
3067 continue;
3068
3069 default:
3070 internalError ();
3071 }
3072 continue;
3073
3074 case 't':
3075 case 'w':
3076 case 'E':
3072 insn.insn_opcode |= va_arg (args, int) << OP_SH_RT;
3077 INSERT_OPERAND (RT, insn, va_arg (args, int));
3073 continue;
3074
3075 case 'c':
3078 continue;
3079
3080 case 'c':
3076 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE;
3081 INSERT_OPERAND (CODE, insn, va_arg (args, int));
3077 continue;
3078
3079 case 'T':
3080 case 'W':
3082 continue;
3083
3084 case 'T':
3085 case 'W':
3081 insn.insn_opcode |= va_arg (args, int) << OP_SH_FT;
3086 INSERT_OPERAND (FT, insn, va_arg (args, int));
3082 continue;
3083
3084 case 'd':
3085 case 'G':
3086 case 'K':
3087 continue;
3088
3089 case 'd':
3090 case 'G':
3091 case 'K':
3087 insn.insn_opcode |= va_arg (args, int) << OP_SH_RD;
3092 INSERT_OPERAND (RD, insn, va_arg (args, int));
3088 continue;
3089
3090 case 'U':
3091 {
3092 int tmp = va_arg (args, int);
3093
3093 continue;
3094
3095 case 'U':
3096 {
3097 int tmp = va_arg (args, int);
3098
3094 insn.insn_opcode |= tmp << OP_SH_RT;
3095 insn.insn_opcode |= tmp << OP_SH_RD;
3099 INSERT_OPERAND (RT, insn, tmp);
3100 INSERT_OPERAND (RD, insn, tmp);
3096 continue;
3097 }
3098
3099 case 'V':
3100 case 'S':
3101 continue;
3102 }
3103
3104 case 'V':
3105 case 'S':
3101 insn.insn_opcode |= va_arg (args, int) << OP_SH_FS;
3106 INSERT_OPERAND (FS, insn, va_arg (args, int));
3102 continue;
3103
3104 case 'z':
3105 continue;
3106
3107 case '<':
3107 continue;
3108
3109 case 'z':
3110 continue;
3111
3112 case '<':
3108 insn.insn_opcode |= va_arg (args, int) << OP_SH_SHAMT;
3113 INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
3109 continue;
3110
3111 case 'D':
3114 continue;
3115
3116 case 'D':
3112 insn.insn_opcode |= va_arg (args, int) << OP_SH_FD;
3117 INSERT_OPERAND (FD, insn, va_arg (args, int));
3113 continue;
3114
3115 case 'B':
3118 continue;
3119
3120 case 'B':
3116 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE20;
3121 INSERT_OPERAND (CODE20, insn, va_arg (args, int));
3117 continue;
3118
3119 case 'J':
3122 continue;
3123
3124 case 'J':
3120 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE19;
3125 INSERT_OPERAND (CODE19, insn, va_arg (args, int));
3121 continue;
3122
3123 case 'q':
3126 continue;
3127
3128 case 'q':
3124 insn.insn_opcode |= va_arg (args, int) << OP_SH_CODE2;
3129 INSERT_OPERAND (CODE2, insn, va_arg (args, int));
3125 continue;
3126
3127 case 'b':
3128 case 's':
3129 case 'r':
3130 case 'v':
3130 continue;
3131
3132 case 'b':
3133 case 's':
3134 case 'r':
3135 case 'v':
3131 insn.insn_opcode |= va_arg (args, int) << OP_SH_RS;
3136 INSERT_OPERAND (RS, insn, va_arg (args, int));
3132 continue;
3133
3134 case 'i':
3135 case 'j':
3136 case 'o':
3137 continue;
3138
3139 case 'i':
3140 case 'j':
3141 case 'o':
3137 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3142 macro_read_relocs (&args, r);
3138 assert (*r == BFD_RELOC_GPREL16
3139 || *r == BFD_RELOC_MIPS_LITERAL
3140 || *r == BFD_RELOC_MIPS_HIGHER
3141 || *r == BFD_RELOC_HI16_S
3142 || *r == BFD_RELOC_LO16
3143 || *r == BFD_RELOC_MIPS_GOT16
3144 || *r == BFD_RELOC_MIPS_CALL16
3145 || *r == BFD_RELOC_MIPS_GOT_DISP
3146 || *r == BFD_RELOC_MIPS_GOT_PAGE
3147 || *r == BFD_RELOC_MIPS_GOT_OFST
3148 || *r == BFD_RELOC_MIPS_GOT_LO16
3143 assert (*r == BFD_RELOC_GPREL16
3144 || *r == BFD_RELOC_MIPS_LITERAL
3145 || *r == BFD_RELOC_MIPS_HIGHER
3146 || *r == BFD_RELOC_HI16_S
3147 || *r == BFD_RELOC_LO16
3148 || *r == BFD_RELOC_MIPS_GOT16
3149 || *r == BFD_RELOC_MIPS_CALL16
3150 || *r == BFD_RELOC_MIPS_GOT_DISP
3151 || *r == BFD_RELOC_MIPS_GOT_PAGE
3152 || *r == BFD_RELOC_MIPS_GOT_OFST
3153 || *r == BFD_RELOC_MIPS_GOT_LO16
3149 || *r == BFD_RELOC_MIPS_CALL_LO16
3150 || (ep->X_op == O_subtract
3151 && *r == BFD_RELOC_PCREL_LO16));
3154 || *r == BFD_RELOC_MIPS_CALL_LO16);
3152 continue;
3153
3154 case 'u':
3155 continue;
3156
3157 case 'u':
3155 *r = (bfd_reloc_code_real_type) va_arg (args, int);
3158 macro_read_relocs (&args, r);
3156 assert (ep != NULL
3157 && (ep->X_op == O_constant
3158 || (ep->X_op == O_symbol
3159 && (*r == BFD_RELOC_MIPS_HIGHEST
3160 || *r == BFD_RELOC_HI16_S
3161 || *r == BFD_RELOC_HI16
3162 || *r == BFD_RELOC_GPREL16
3163 || *r == BFD_RELOC_MIPS_GOT_HI16
3159 assert (ep != NULL
3160 && (ep->X_op == O_constant
3161 || (ep->X_op == O_symbol
3162 && (*r == BFD_RELOC_MIPS_HIGHEST
3163 || *r == BFD_RELOC_HI16_S
3164 || *r == BFD_RELOC_HI16
3165 || *r == BFD_RELOC_GPREL16
3166 || *r == BFD_RELOC_MIPS_GOT_HI16
3164 || *r == BFD_RELOC_MIPS_CALL_HI16))
3165 || (ep->X_op == O_subtract
3166 && *r == BFD_RELOC_PCREL_HI16_S)));
3167 || *r == BFD_RELOC_MIPS_CALL_HI16))));
3167 continue;
3168
3169 case 'p':
3170 assert (ep != NULL);
3168 continue;
3169
3170 case 'p':
3171 assert (ep != NULL);
3172
3171 /*
3172 * This allows macro() to pass an immediate expression for
3173 * creating short branches without creating a symbol.
3173 /*
3174 * This allows macro() to pass an immediate expression for
3175 * creating short branches without creating a symbol.
3174 * Note that the expression still might come from the assembly
3175 * input, in which case the value is not checked for range nor
3176 * is a relocation entry generated (yuck).
3176 *
3177 * We don't allow branch relaxation for these branches, as
3178 * they should only appear in ".set nomacro" anyway.
3177 */
3178 if (ep->X_op == O_constant)
3179 {
3179 */
3180 if (ep->X_op == O_constant)
3181 {
3182 if ((ep->X_add_number & 3) != 0)
3183 as_bad (_("branch to misaligned address (0x%lx)"),
3184 (unsigned long) ep->X_add_number);
3185 if ((ep->X_add_number + 0x20000) & ~0x3ffff)
3186 as_bad (_("branch address range overflow (0x%lx)"),
3187 (unsigned long) ep->X_add_number);
3180 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3181 ep = NULL;
3182 }
3183 else
3184 *r = BFD_RELOC_16_PCREL_S2;
3185 continue;
3186
3187 case 'a':

--- 15 unchanged lines hidden (view full) ---

3203
3204 append_insn (&insn, ep, r);
3205}
3206
3207static void
3208mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3209 va_list args)
3210{
3188 insn.insn_opcode |= (ep->X_add_number >> 2) & 0xffff;
3189 ep = NULL;
3190 }
3191 else
3192 *r = BFD_RELOC_16_PCREL_S2;
3193 continue;
3194
3195 case 'a':

--- 15 unchanged lines hidden (view full) ---

3211
3212 append_insn (&insn, ep, r);
3213}
3214
3215static void
3216mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
3217 va_list args)
3218{
3219 struct mips_opcode *mo;
3211 struct mips_cl_insn insn;
3212 bfd_reloc_code_real_type r[3]
3213 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3214
3220 struct mips_cl_insn insn;
3221 bfd_reloc_code_real_type r[3]
3222 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3223
3215 insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3216 assert (insn.insn_mo);
3217 assert (strcmp (name, insn.insn_mo->name) == 0);
3224 mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
3225 assert (mo);
3226 assert (strcmp (name, mo->name) == 0);
3218
3227
3219 while (strcmp (fmt, insn.insn_mo->args) != 0
3220 || insn.insn_mo->pinfo == INSN_MACRO)
3228 while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
3221 {
3229 {
3222 ++insn.insn_mo;
3223 assert (insn.insn_mo->name);
3224 assert (strcmp (name, insn.insn_mo->name) == 0);
3230 ++mo;
3231 assert (mo->name);
3232 assert (strcmp (name, mo->name) == 0);
3225 }
3226
3233 }
3234
3227 insn.insn_opcode = insn.insn_mo->match;
3228 insn.use_extend = FALSE;
3229
3235 create_insn (&insn, mo);
3230 for (;;)
3231 {
3232 int c;
3233
3234 c = *fmt++;
3235 switch (c)
3236 {
3237 case '\0':
3238 break;
3239
3240 case ',':
3241 case '(':
3242 case ')':
3243 continue;
3244
3245 case 'y':
3246 case 'w':
3236 for (;;)
3237 {
3238 int c;
3239
3240 c = *fmt++;
3241 switch (c)
3242 {
3243 case '\0':
3244 break;
3245
3246 case ',':
3247 case '(':
3248 case ')':
3249 continue;
3250
3251 case 'y':
3252 case 'w':
3247 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RY;
3253 MIPS16_INSERT_OPERAND (RY, insn, va_arg (args, int));
3248 continue;
3249
3250 case 'x':
3251 case 'v':
3254 continue;
3255
3256 case 'x':
3257 case 'v':
3252 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RX;
3258 MIPS16_INSERT_OPERAND (RX, insn, va_arg (args, int));
3253 continue;
3254
3255 case 'z':
3259 continue;
3260
3261 case 'z':
3256 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_RZ;
3262 MIPS16_INSERT_OPERAND (RZ, insn, va_arg (args, int));
3257 continue;
3258
3259 case 'Z':
3263 continue;
3264
3265 case 'Z':
3260 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_MOVE32Z;
3266 MIPS16_INSERT_OPERAND (MOVE32Z, insn, va_arg (args, int));
3261 continue;
3262
3263 case '0':
3264 case 'S':
3265 case 'P':
3266 case 'R':
3267 continue;
3268
3269 case 'X':
3267 continue;
3268
3269 case '0':
3270 case 'S':
3271 case 'P':
3272 case 'R':
3273 continue;
3274
3275 case 'X':
3270 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_REGR32;
3276 MIPS16_INSERT_OPERAND (REGR32, insn, va_arg (args, int));
3271 continue;
3272
3273 case 'Y':
3274 {
3275 int regno;
3276
3277 regno = va_arg (args, int);
3278 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);

--- 29 unchanged lines hidden (view full) ---

3308 &insn.extend);
3309 ep = NULL;
3310 *r = BFD_RELOC_UNUSED;
3311 }
3312 }
3313 continue;
3314
3315 case '6':
3277 continue;
3278
3279 case 'Y':
3280 {
3281 int regno;
3282
3283 regno = va_arg (args, int);
3284 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);

--- 29 unchanged lines hidden (view full) ---

3314 &insn.extend);
3315 ep = NULL;
3316 *r = BFD_RELOC_UNUSED;
3317 }
3318 }
3319 continue;
3320
3321 case '6':
3316 insn.insn_opcode |= va_arg (args, int) << MIPS16OP_SH_IMM6;
3322 MIPS16_INSERT_OPERAND (IMM6, insn, va_arg (args, int));
3317 continue;
3318 }
3319
3320 break;
3321 }
3322
3323 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3324
3325 append_insn (&insn, ep, r);
3326}
3327
3328/*
3323 continue;
3324 }
3325
3326 break;
3327 }
3328
3329 assert (*r == BFD_RELOC_UNUSED ? ep == NULL : ep != NULL);
3330
3331 append_insn (&insn, ep, r);
3332}
3333
3334/*
3335 * Sign-extend 32-bit mode constants that have bit 31 set and all
3336 * higher bits unset.
3337 */
3338static void
3339normalize_constant_expr (expressionS *ex)
3340{
3341 if (ex->X_op == O_constant
3342 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3343 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3344 - 0x80000000);
3345}
3346
3347/*
3348 * Sign-extend 32-bit mode address offsets that have bit 31 set and
3349 * all higher bits unset.
3350 */
3351static void
3352normalize_address_expr (expressionS *ex)
3353{
3354 if (((ex->X_op == O_constant && HAVE_32BIT_ADDRESSES)
3355 || (ex->X_op == O_symbol && HAVE_32BIT_SYMBOLS))
3356 && IS_ZEXT_32BIT_NUM (ex->X_add_number))
3357 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3358 - 0x80000000);
3359}
3360
3361/*
3329 * Generate a "jalr" instruction with a relocation hint to the called
3330 * function. This occurs in NewABI PIC code.
3331 */
3332static void
3333macro_build_jalr (expressionS *ep)
3334{
3335 char *f = NULL;
3336

--- 10 unchanged lines hidden (view full) ---

3347
3348/*
3349 * Generate a "lui" instruction.
3350 */
3351static void
3352macro_build_lui (expressionS *ep, int regnum)
3353{
3354 expressionS high_expr;
3362 * Generate a "jalr" instruction with a relocation hint to the called
3363 * function. This occurs in NewABI PIC code.
3364 */
3365static void
3366macro_build_jalr (expressionS *ep)
3367{
3368 char *f = NULL;
3369

--- 10 unchanged lines hidden (view full) ---

3380
3381/*
3382 * Generate a "lui" instruction.
3383 */
3384static void
3385macro_build_lui (expressionS *ep, int regnum)
3386{
3387 expressionS high_expr;
3388 const struct mips_opcode *mo;
3355 struct mips_cl_insn insn;
3356 bfd_reloc_code_real_type r[3]
3357 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3358 const char *name = "lui";
3359 const char *fmt = "t,u";
3360
3361 assert (! mips_opts.mips16);
3362

--- 4 unchanged lines hidden (view full) ---

3367 /* we can compute the instruction now without a relocation entry */
3368 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3369 >> 16) & 0xffff;
3370 *r = BFD_RELOC_UNUSED;
3371 }
3372 else
3373 {
3374 assert (ep->X_op == O_symbol);
3389 struct mips_cl_insn insn;
3390 bfd_reloc_code_real_type r[3]
3391 = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
3392 const char *name = "lui";
3393 const char *fmt = "t,u";
3394
3395 assert (! mips_opts.mips16);
3396

--- 4 unchanged lines hidden (view full) ---

3401 /* we can compute the instruction now without a relocation entry */
3402 high_expr.X_add_number = ((high_expr.X_add_number + 0x8000)
3403 >> 16) & 0xffff;
3404 *r = BFD_RELOC_UNUSED;
3405 }
3406 else
3407 {
3408 assert (ep->X_op == O_symbol);
3375 /* _gp_disp is a special case, used from s_cpload. */
3409 /* _gp_disp is a special case, used from s_cpload.
3410 __gnu_local_gp is used if mips_no_shared. */
3376 assert (mips_pic == NO_PIC
3377 || (! HAVE_NEWABI
3411 assert (mips_pic == NO_PIC
3412 || (! HAVE_NEWABI
3378 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0));
3413 && strcmp (S_GET_NAME (ep->X_add_symbol), "_gp_disp") == 0)
3414 || (! mips_in_shared
3415 && strcmp (S_GET_NAME (ep->X_add_symbol),
3416 "__gnu_local_gp") == 0));
3379 *r = BFD_RELOC_HI16_S;
3380 }
3381
3417 *r = BFD_RELOC_HI16_S;
3418 }
3419
3382 insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
3383 assert (insn.insn_mo);
3384 assert (strcmp (name, insn.insn_mo->name) == 0);
3385 assert (strcmp (fmt, insn.insn_mo->args) == 0);
3420 mo = hash_find (op_hash, name);
3421 assert (strcmp (name, mo->name) == 0);
3422 assert (strcmp (fmt, mo->args) == 0);
3423 create_insn (&insn, mo);
3386
3424
3387 insn.insn_opcode = insn.insn_mo->match | (regnum << OP_SH_RT);
3425 insn.insn_opcode = insn.insn_mo->match;
3426 INSERT_OPERAND (RT, insn, regnum);
3388 if (*r == BFD_RELOC_UNUSED)
3389 {
3390 insn.insn_opcode |= high_expr.X_add_number;
3391 append_insn (&insn, NULL, r);
3392 }
3393 else
3394 append_insn (&insn, &high_expr, r);
3395}
3396
3397/* Generate a sequence of instructions to do a load or store from a constant
3398 offset off of a base register (breg) into/from a target register (treg),
3399 using AT if necessary. */
3400static void
3401macro_build_ldst_constoffset (expressionS *ep, const char *op,
3402 int treg, int breg, int dbl)
3403{
3404 assert (ep->X_op == O_constant);
3405
3406 /* Sign-extending 32-bit constants makes their handling easier. */
3427 if (*r == BFD_RELOC_UNUSED)
3428 {
3429 insn.insn_opcode |= high_expr.X_add_number;
3430 append_insn (&insn, NULL, r);
3431 }
3432 else
3433 append_insn (&insn, &high_expr, r);
3434}
3435
3436/* Generate a sequence of instructions to do a load or store from a constant
3437 offset off of a base register (breg) into/from a target register (treg),
3438 using AT if necessary. */
3439static void
3440macro_build_ldst_constoffset (expressionS *ep, const char *op,
3441 int treg, int breg, int dbl)
3442{
3443 assert (ep->X_op == O_constant);
3444
3445 /* Sign-extending 32-bit constants makes their handling easier. */
3407 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3408 == ~((bfd_vma) 0x7fffffff)))
3409 {
3410 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3411 as_bad (_("constant too large"));
3446 if (!dbl)
3447 normalize_constant_expr (ep);
3412
3448
3413 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3414 - 0x80000000);
3415 }
3416
3417 /* Right now, this routine can only handle signed 32-bit constants. */
3418 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3419 as_warn (_("operand overflow"));
3420
3421 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3422 {
3423 /* Signed 16-bit offset will fit in the op. Easy! */
3424 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);

--- 5 unchanged lines hidden (view full) ---

3430 addu $tempreg,$tempreg,$breg
3431 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3432 to handle the complete offset. */
3433 macro_build_lui (ep, AT);
3434 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3435 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3436
3437 if (mips_opts.noat)
3449 /* Right now, this routine can only handle signed 32-bit constants. */
3450 if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
3451 as_warn (_("operand overflow"));
3452
3453 if (IS_SEXT_16BIT_NUM(ep->X_add_number))
3454 {
3455 /* Signed 16-bit offset will fit in the op. Easy! */
3456 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, breg);

--- 5 unchanged lines hidden (view full) ---

3462 addu $tempreg,$tempreg,$breg
3463 <op> $treg,const_lo($tempreg) (BFD_RELOC_LO16)
3464 to handle the complete offset. */
3465 macro_build_lui (ep, AT);
3466 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
3467 macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
3468
3469 if (mips_opts.noat)
3438 as_warn (_("Macro used $at after \".set noat\""));
3470 as_bad (_("Macro used $at after \".set noat\""));
3439 }
3440}
3441
3442/* set_at()
3443 * Generates code to set the $at register to true (one)
3444 * if reg is less than the immediate expression.
3445 */
3446static void

--- 6 unchanged lines hidden (view full) ---

3453 AT, reg, BFD_RELOC_LO16);
3454 else
3455 {
3456 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3457 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3458 }
3459}
3460
3471 }
3472}
3473
3474/* set_at()
3475 * Generates code to set the $at register to true (one)
3476 * if reg is less than the immediate expression.
3477 */
3478static void

--- 6 unchanged lines hidden (view full) ---

3485 AT, reg, BFD_RELOC_LO16);
3486 else
3487 {
3488 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
3489 macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT);
3490 }
3491}
3492
3461static void
3462normalize_constant_expr (expressionS *ex)
3463{
3464 if (ex->X_op == O_constant && HAVE_32BIT_GPRS)
3465 ex->X_add_number = (((ex->X_add_number & 0xffffffff) ^ 0x80000000)
3466 - 0x80000000);
3467}
3468
3469/* Warn if an expression is not a constant. */
3470
3471static void
3472check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3473{
3474 if (ex->X_op == O_big)
3475 as_bad (_("unsupported large constant"));
3476 else if (ex->X_op != O_constant)
3493/* Warn if an expression is not a constant. */
3494
3495static void
3496check_absolute_expr (struct mips_cl_insn *ip, expressionS *ex)
3497{
3498 if (ex->X_op == O_big)
3499 as_bad (_("unsupported large constant"));
3500 else if (ex->X_op != O_constant)
3477 as_bad (_("Instruction %s requires absolute expression"), ip->insn_mo->name);
3501 as_bad (_("Instruction %s requires absolute expression"),
3502 ip->insn_mo->name);
3478
3503
3479 normalize_constant_expr (ex);
3504 if (HAVE_32BIT_GPRS)
3505 normalize_constant_expr (ex);
3480}
3481
3482/* Count the leading zeroes by performing a binary chop. This is a
3483 bulky bit of source, but performance is a LOT better for the
3484 majority of values than a simple loop to count the bits:
3485 for (lcnt = 0; (lcnt < 32); lcnt++)
3486 if ((v) & (1 << (31 - lcnt)))
3487 break;

--- 77 unchanged lines hidden (view full) ---

3565 int freg;
3566 expressionS hi32, lo32;
3567
3568 if (ep->X_op != O_big)
3569 {
3570 assert (ep->X_op == O_constant);
3571
3572 /* Sign-extending 32-bit constants makes their handling easier. */
3506}
3507
3508/* Count the leading zeroes by performing a binary chop. This is a
3509 bulky bit of source, but performance is a LOT better for the
3510 majority of values than a simple loop to count the bits:
3511 for (lcnt = 0; (lcnt < 32); lcnt++)
3512 if ((v) & (1 << (31 - lcnt)))
3513 break;

--- 77 unchanged lines hidden (view full) ---

3591 int freg;
3592 expressionS hi32, lo32;
3593
3594 if (ep->X_op != O_big)
3595 {
3596 assert (ep->X_op == O_constant);
3597
3598 /* Sign-extending 32-bit constants makes their handling easier. */
3573 if (! dbl && ! ((ep->X_add_number & ~((bfd_vma) 0x7fffffff))
3574 == ~((bfd_vma) 0x7fffffff)))
3575 {
3576 if (ep->X_add_number & ~((bfd_vma) 0xffffffff))
3577 as_bad (_("constant too large"));
3599 if (!dbl)
3600 normalize_constant_expr (ep);
3578
3601
3579 ep->X_add_number = (((ep->X_add_number & 0xffffffff) ^ 0x80000000)
3580 - 0x80000000);
3581 }
3582
3583 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3584 {
3585 /* We can handle 16 bit signed values with an addiu to
3586 $zero. No need to ever use daddiu here, since $zero and
3587 the result are always correct in 32 bit mode. */
3588 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3589 return;
3590 }

--- 11 unchanged lines hidden (view full) ---

3602 if ((ep->X_add_number & 0xffff) != 0)
3603 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3604 return;
3605 }
3606 }
3607
3608 /* The value is larger than 32 bits. */
3609
3602 if (IS_SEXT_16BIT_NUM (ep->X_add_number))
3603 {
3604 /* We can handle 16 bit signed values with an addiu to
3605 $zero. No need to ever use daddiu here, since $zero and
3606 the result are always correct in 32 bit mode. */
3607 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3608 return;
3609 }

--- 11 unchanged lines hidden (view full) ---

3621 if ((ep->X_add_number & 0xffff) != 0)
3622 macro_build (ep, "ori", "t,r,i", reg, reg, BFD_RELOC_LO16);
3623 return;
3624 }
3625 }
3626
3627 /* The value is larger than 32 bits. */
3628
3610 if (HAVE_32BIT_GPRS)
3629 if (!dbl || HAVE_32BIT_GPRS)
3611 {
3630 {
3612 as_bad (_("Number (0x%lx) larger than 32 bits"),
3613 (unsigned long) ep->X_add_number);
3631 char value[32];
3632
3633 sprintf_vma (value, ep->X_add_number);
3634 as_bad (_("Number (0x%s) larger than 32 bits"), value);
3614 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3615 return;
3616 }
3617
3618 if (ep->X_op != O_big)
3619 {
3620 hi32 = *ep;
3621 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;

--- 165 unchanged lines hidden (view full) ---

3787 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3788 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3789 freg = reg;
3790 }
3791 if ((lo32.X_add_number & 0xffff) != 0)
3792 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3793}
3794
3635 macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
3636 return;
3637 }
3638
3639 if (ep->X_op != O_big)
3640 {
3641 hi32 = *ep;
3642 hi32.X_add_number = (valueT) hi32.X_add_number >> 16;

--- 165 unchanged lines hidden (view full) ---

3808 macro_build (&mid16, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3809 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3810 freg = reg;
3811 }
3812 if ((lo32.X_add_number & 0xffff) != 0)
3813 macro_build (&lo32, "ori", "t,r,i", reg, freg, BFD_RELOC_LO16);
3814}
3815
3816static inline void
3817load_delay_nop (void)
3818{
3819 if (!gpr_interlocks)
3820 macro_build (NULL, "nop", "");
3821}
3822
3795/* Load an address into a register. */
3796
3797static void
3798load_address (int reg, expressionS *ep, int *used_at)
3799{
3800 if (ep->X_op != O_constant
3801 && ep->X_op != O_symbol)
3802 {

--- 27 unchanged lines hidden (view full) ---

3830 If $at is already in use, we use a path which is suboptimal
3831 on superscalar processors.
3832 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3833 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3834 dsll $reg,16
3835 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3836 dsll $reg,16
3837 daddiu $reg,<sym> (BFD_RELOC_LO16)
3823/* Load an address into a register. */
3824
3825static void
3826load_address (int reg, expressionS *ep, int *used_at)
3827{
3828 if (ep->X_op != O_constant
3829 && ep->X_op != O_symbol)
3830 {

--- 27 unchanged lines hidden (view full) ---

3858 If $at is already in use, we use a path which is suboptimal
3859 on superscalar processors.
3860 lui $reg,<sym> (BFD_RELOC_MIPS_HIGHEST)
3861 daddiu $reg,<sym> (BFD_RELOC_MIPS_HIGHER)
3862 dsll $reg,16
3863 daddiu $reg,<sym> (BFD_RELOC_HI16_S)
3864 dsll $reg,16
3865 daddiu $reg,<sym> (BFD_RELOC_LO16)
3838 */
3839 if (HAVE_64BIT_ADDRESSES)
3866
3867 For GP relative symbols in 64bit address space we can use
3868 the same sequence as in 32bit address space. */
3869 if (HAVE_64BIT_SYMBOLS)
3840 {
3870 {
3841 /* ??? We don't provide a GP-relative alternative for these macros.
3842 It used not to be possible with the original relaxation code,
3843 but it could be done now. */
3871 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3872 && !nopic_need_relax (ep->X_add_symbol, 1))
3873 {
3874 relax_start (ep->X_add_symbol);
3875 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3876 mips_gp_register, BFD_RELOC_GPREL16);
3877 relax_switch ();
3878 }
3844
3879
3845 if (*used_at == 0 && ! mips_opts.noat)
3880 if (*used_at == 0 && !mips_opts.noat)
3846 {
3847 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3848 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3849 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3850 BFD_RELOC_MIPS_HIGHER);
3851 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3852 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3853 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);

--- 4 unchanged lines hidden (view full) ---

3858 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3859 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3860 BFD_RELOC_MIPS_HIGHER);
3861 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3862 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3863 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3864 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3865 }
3881 {
3882 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3883 macro_build (ep, "lui", "t,u", AT, BFD_RELOC_HI16_S);
3884 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3885 BFD_RELOC_MIPS_HIGHER);
3886 macro_build (ep, "daddiu", "t,r,j", AT, AT, BFD_RELOC_LO16);
3887 macro_build (NULL, "dsll32", "d,w,<", reg, reg, 0);
3888 macro_build (NULL, "daddu", "d,v,t", reg, reg, AT);

--- 4 unchanged lines hidden (view full) ---

3893 macro_build (ep, "lui", "t,u", reg, BFD_RELOC_MIPS_HIGHEST);
3894 macro_build (ep, "daddiu", "t,r,j", reg, reg,
3895 BFD_RELOC_MIPS_HIGHER);
3896 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3897 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_HI16_S);
3898 macro_build (NULL, "dsll", "d,w,<", reg, reg, 16);
3899 macro_build (ep, "daddiu", "t,r,j", reg, reg, BFD_RELOC_LO16);
3900 }
3901
3902 if (mips_relax.sequence)
3903 relax_end ();
3866 }
3867 else
3868 {
3869 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3904 }
3905 else
3906 {
3907 if ((valueT) ep->X_add_number <= MAX_GPREL_OFFSET
3870 && ! nopic_need_relax (ep->X_add_symbol, 1))
3908 && !nopic_need_relax (ep->X_add_symbol, 1))
3871 {
3872 relax_start (ep->X_add_symbol);
3873 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3874 mips_gp_register, BFD_RELOC_GPREL16);
3875 relax_switch ();
3876 }
3877 macro_build_lui (ep, reg);
3878 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3879 reg, reg, BFD_RELOC_LO16);
3880 if (mips_relax.sequence)
3881 relax_end ();
3882 }
3883 }
3909 {
3910 relax_start (ep->X_add_symbol);
3911 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg,
3912 mips_gp_register, BFD_RELOC_GPREL16);
3913 relax_switch ();
3914 }
3915 macro_build_lui (ep, reg);
3916 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
3917 reg, reg, BFD_RELOC_LO16);
3918 if (mips_relax.sequence)
3919 relax_end ();
3920 }
3921 }
3884 else if (mips_pic == SVR4_PIC && ! mips_big_got)
3922 else if (!mips_big_got)
3885 {
3886 expressionS ex;
3887
3888 /* If this is a reference to an external symbol, we want
3889 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3890 Otherwise we want
3891 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3892 nop

--- 27 unchanged lines hidden (view full) ---

3920 relax_end ();
3921 }
3922 else
3923 {
3924 ex.X_add_number = ep->X_add_number;
3925 ep->X_add_number = 0;
3926 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3927 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3923 {
3924 expressionS ex;
3925
3926 /* If this is a reference to an external symbol, we want
3927 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3928 Otherwise we want
3929 lw $reg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
3930 nop

--- 27 unchanged lines hidden (view full) ---

3958 relax_end ();
3959 }
3960 else
3961 {
3962 ex.X_add_number = ep->X_add_number;
3963 ep->X_add_number = 0;
3964 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
3965 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3928 macro_build (NULL, "nop", "");
3966 load_delay_nop ();
3929 relax_start (ep->X_add_symbol);
3930 relax_switch ();
3931 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3932 BFD_RELOC_LO16);
3933 relax_end ();
3934
3935 if (ex.X_add_number != 0)
3936 {
3937 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3938 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3939 ex.X_op = O_constant;
3940 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3941 reg, reg, BFD_RELOC_LO16);
3942 }
3943 }
3944 }
3967 relax_start (ep->X_add_symbol);
3968 relax_switch ();
3969 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
3970 BFD_RELOC_LO16);
3971 relax_end ();
3972
3973 if (ex.X_add_number != 0)
3974 {
3975 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
3976 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
3977 ex.X_op = O_constant;
3978 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j",
3979 reg, reg, BFD_RELOC_LO16);
3980 }
3981 }
3982 }
3945 else if (mips_pic == SVR4_PIC)
3983 else if (mips_big_got)
3946 {
3947 expressionS ex;
3948
3949 /* This is the large GOT case. If this is a reference to an
3950 external symbol, we want
3951 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3952 addu $reg,$reg,$gp
3953 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)

--- 51 unchanged lines hidden (view full) ---

4005 /* We need a nop before loading from $gp. This special
4006 check is required because the lui which starts the main
4007 instruction stream does not refer to $gp, and so will not
4008 insert the nop which may be required. */
4009 macro_build (NULL, "nop", "");
4010 }
4011 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4012 BFD_RELOC_MIPS_GOT16, mips_gp_register);
3984 {
3985 expressionS ex;
3986
3987 /* This is the large GOT case. If this is a reference to an
3988 external symbol, we want
3989 lui $reg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
3990 addu $reg,$reg,$gp
3991 lw $reg,<sym>($reg) (BFD_RELOC_MIPS_GOT_LO16)

--- 51 unchanged lines hidden (view full) ---

4043 /* We need a nop before loading from $gp. This special
4044 check is required because the lui which starts the main
4045 instruction stream does not refer to $gp, and so will not
4046 insert the nop which may be required. */
4047 macro_build (NULL, "nop", "");
4048 }
4049 macro_build (ep, ADDRESS_LOAD_INSN, "t,o(b)", reg,
4050 BFD_RELOC_MIPS_GOT16, mips_gp_register);
4013 macro_build (NULL, "nop", "");
4051 load_delay_nop ();
4014 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4015 BFD_RELOC_LO16);
4016 relax_end ();
4017
4018 if (ex.X_add_number != 0)
4019 {
4020 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4021 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4022 ex.X_op = O_constant;
4023 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4024 BFD_RELOC_LO16);
4025 }
4026 }
4027 }
4052 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4053 BFD_RELOC_LO16);
4054 relax_end ();
4055
4056 if (ex.X_add_number != 0)
4057 {
4058 if (ex.X_add_number < -0x8000 || ex.X_add_number >= 0x8000)
4059 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
4060 ex.X_op = O_constant;
4061 macro_build (&ex, ADDRESS_ADDI_INSN, "t,r,j", reg, reg,
4062 BFD_RELOC_LO16);
4063 }
4064 }
4065 }
4028 else if (mips_pic == EMBEDDED_PIC)
4029 {
4030 /* We always do
4031 addiu $reg,$gp,<sym> (BFD_RELOC_GPREL16)
4032 */
4033 macro_build (ep, ADDRESS_ADDI_INSN, "t,r,j",
4034 reg, mips_gp_register, BFD_RELOC_GPREL16);
4035 }
4036 else
4037 abort ();
4066 else
4067 abort ();
4068
4069 if (mips_opts.noat && *used_at == 1)
4070 as_bad (_("Macro used $at after \".set noat\""));
4038}
4039
4040/* Move the contents of register SOURCE into register DEST. */
4041
4042static void
4043move_register (int dest, int source)
4044{
4045 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",

--- 132 unchanged lines hidden (view full) ---

4178 case M_DABS:
4179 dbl = 1;
4180 case M_ABS:
4181 /* bgez $a0,.+12
4182 move v0,$a0
4183 sub v0,$zero,$a0
4184 */
4185
4071}
4072
4073/* Move the contents of register SOURCE into register DEST. */
4074
4075static void
4076move_register (int dest, int source)
4077{
4078 macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t",

--- 132 unchanged lines hidden (view full) ---

4211 case M_DABS:
4212 dbl = 1;
4213 case M_ABS:
4214 /* bgez $a0,.+12
4215 move v0,$a0
4216 sub v0,$zero,$a0
4217 */
4218
4186 mips_emit_delays (TRUE);
4187 ++mips_opts.noreorder;
4188 mips_any_noreorder = 1;
4219 start_noreorder ();
4189
4190 expr1.X_add_number = 8;
4191 macro_build (&expr1, "bgez", "s,p", sreg);
4192 if (dreg == sreg)
4193 macro_build (NULL, "nop", "", 0);
4194 else
4195 move_register (dreg, sreg);
4196 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4197
4220
4221 expr1.X_add_number = 8;
4222 macro_build (&expr1, "bgez", "s,p", sreg);
4223 if (dreg == sreg)
4224 macro_build (NULL, "nop", "", 0);
4225 else
4226 move_register (dreg, sreg);
4227 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, 0, sreg);
4228
4198 --mips_opts.noreorder;
4199 return;
4229 end_noreorder ();
4230 break;
4200
4201 case M_ADD_I:
4202 s = "addi";
4203 s2 = "add";
4204 goto do_addi;
4205 case M_ADDU_I:
4206 s = "addiu";
4207 s2 = "addu";

--- 8 unchanged lines hidden (view full) ---

4216 s = "daddiu";
4217 s2 = "daddu";
4218 do_addi:
4219 if (imm_expr.X_op == O_constant
4220 && imm_expr.X_add_number >= -0x8000
4221 && imm_expr.X_add_number < 0x8000)
4222 {
4223 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4231
4232 case M_ADD_I:
4233 s = "addi";
4234 s2 = "add";
4235 goto do_addi;
4236 case M_ADDU_I:
4237 s = "addiu";
4238 s2 = "addu";

--- 8 unchanged lines hidden (view full) ---

4247 s = "daddiu";
4248 s2 = "daddu";
4249 do_addi:
4250 if (imm_expr.X_op == O_constant
4251 && imm_expr.X_add_number >= -0x8000
4252 && imm_expr.X_add_number < 0x8000)
4253 {
4254 macro_build (&imm_expr, s, "t,r,j", treg, sreg, BFD_RELOC_LO16);
4224 return;
4255 break;
4225 }
4256 }
4257 used_at = 1;
4226 load_register (AT, &imm_expr, dbl);
4227 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4228 break;
4229
4230 case M_AND_I:
4231 s = "andi";
4232 s2 = "and";
4233 goto do_bit;

--- 16 unchanged lines hidden (view full) ---

4250 if (mask != M_NOR_I)
4251 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4252 else
4253 {
4254 macro_build (&imm_expr, "ori", "t,r,i",
4255 treg, sreg, BFD_RELOC_LO16);
4256 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4257 }
4258 load_register (AT, &imm_expr, dbl);
4259 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4260 break;
4261
4262 case M_AND_I:
4263 s = "andi";
4264 s2 = "and";
4265 goto do_bit;

--- 16 unchanged lines hidden (view full) ---

4282 if (mask != M_NOR_I)
4283 macro_build (&imm_expr, s, "t,r,i", treg, sreg, BFD_RELOC_LO16);
4284 else
4285 {
4286 macro_build (&imm_expr, "ori", "t,r,i",
4287 treg, sreg, BFD_RELOC_LO16);
4288 macro_build (NULL, "nor", "d,v,t", treg, treg, 0);
4289 }
4258 return;
4290 break;
4259 }
4260
4291 }
4292
4293 used_at = 1;
4261 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4262 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4263 break;
4264
4265 case M_BEQ_I:
4266 s = "beq";
4267 goto beq_i;
4268 case M_BEQL_I:

--- 5 unchanged lines hidden (view full) ---

4274 goto beq_i;
4275 case M_BNEL_I:
4276 s = "bnel";
4277 likely = 1;
4278 beq_i:
4279 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4280 {
4281 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4294 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4295 macro_build (NULL, s2, "d,v,t", treg, sreg, AT);
4296 break;
4297
4298 case M_BEQ_I:
4299 s = "beq";
4300 goto beq_i;
4301 case M_BEQL_I:

--- 5 unchanged lines hidden (view full) ---

4307 goto beq_i;
4308 case M_BNEL_I:
4309 s = "bnel";
4310 likely = 1;
4311 beq_i:
4312 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4313 {
4314 macro_build (&offset_expr, s, "s,t,p", sreg, 0);
4282 return;
4315 break;
4283 }
4316 }
4317 used_at = 1;
4284 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4285 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4286 break;
4287
4288 case M_BGEL:
4289 likely = 1;
4290 case M_BGE:
4291 if (treg == 0)
4292 {
4293 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4318 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
4319 macro_build (&offset_expr, s, "s,t,p", sreg, AT);
4320 break;
4321
4322 case M_BGEL:
4323 likely = 1;
4324 case M_BGE:
4325 if (treg == 0)
4326 {
4327 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4294 return;
4328 break;
4295 }
4296 if (sreg == 0)
4297 {
4298 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4329 }
4330 if (sreg == 0)
4331 {
4332 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", treg);
4299 return;
4333 break;
4300 }
4334 }
4335 used_at = 1;
4301 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4302 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4303 break;
4304
4305 case M_BGTL_I:
4306 likely = 1;
4307 case M_BGT_I:
4308 /* check for > max integer */

--- 10 unchanged lines hidden (view full) ---

4319 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4320 {
4321 do_false:
4322 /* result is always false */
4323 if (! likely)
4324 macro_build (NULL, "nop", "", 0);
4325 else
4326 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4336 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4337 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4338 break;
4339
4340 case M_BGTL_I:
4341 likely = 1;
4342 case M_BGT_I:
4343 /* check for > max integer */

--- 10 unchanged lines hidden (view full) ---

4354 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4355 {
4356 do_false:
4357 /* result is always false */
4358 if (! likely)
4359 macro_build (NULL, "nop", "", 0);
4360 else
4361 macro_build (&offset_expr, "bnel", "s,t,p", 0, 0);
4327 return;
4362 break;
4328 }
4329 if (imm_expr.X_op != O_constant)
4330 as_bad (_("Unsupported large constant"));
4331 ++imm_expr.X_add_number;
4332 /* FALLTHROUGH */
4333 case M_BGE_I:
4334 case M_BGEL_I:
4335 if (mask == M_BGEL_I)
4336 likely = 1;
4337 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4338 {
4339 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4363 }
4364 if (imm_expr.X_op != O_constant)
4365 as_bad (_("Unsupported large constant"));
4366 ++imm_expr.X_add_number;
4367 /* FALLTHROUGH */
4368 case M_BGE_I:
4369 case M_BGEL_I:
4370 if (mask == M_BGEL_I)
4371 likely = 1;
4372 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4373 {
4374 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", sreg);
4340 return;
4375 break;
4341 }
4342 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4343 {
4344 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4376 }
4377 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4378 {
4379 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4345 return;
4380 break;
4346 }
4347 maxnum = 0x7fffffff;
4348 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4349 {
4350 maxnum <<= 16;
4351 maxnum |= 0xffff;
4352 maxnum <<= 16;
4353 maxnum |= 0xffff;
4354 }
4355 maxnum = - maxnum - 1;
4356 if (imm_expr.X_op == O_constant
4357 && imm_expr.X_add_number <= maxnum
4358 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4359 {
4360 do_true:
4361 /* result is always true */
4362 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4363 macro_build (&offset_expr, "b", "p");
4381 }
4382 maxnum = 0x7fffffff;
4383 if (HAVE_64BIT_GPRS && sizeof (maxnum) > 4)
4384 {
4385 maxnum <<= 16;
4386 maxnum |= 0xffff;
4387 maxnum <<= 16;
4388 maxnum |= 0xffff;
4389 }
4390 maxnum = - maxnum - 1;
4391 if (imm_expr.X_op == O_constant
4392 && imm_expr.X_add_number <= maxnum
4393 && (HAVE_32BIT_GPRS || sizeof (maxnum) > 4))
4394 {
4395 do_true:
4396 /* result is always true */
4397 as_warn (_("Branch %s is always true"), ip->insn_mo->name);
4398 macro_build (&offset_expr, "b", "p");
4364 return;
4399 break;
4365 }
4400 }
4401 used_at = 1;
4366 set_at (sreg, 0);
4367 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4368 break;
4369
4370 case M_BGEUL:
4371 likely = 1;
4372 case M_BGEU:
4373 if (treg == 0)
4374 goto do_true;
4375 if (sreg == 0)
4376 {
4377 macro_build (&offset_expr, likely ? "beql" : "beq",
4378 "s,t,p", 0, treg);
4402 set_at (sreg, 0);
4403 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4404 break;
4405
4406 case M_BGEUL:
4407 likely = 1;
4408 case M_BGEU:
4409 if (treg == 0)
4410 goto do_true;
4411 if (sreg == 0)
4412 {
4413 macro_build (&offset_expr, likely ? "beql" : "beq",
4414 "s,t,p", 0, treg);
4379 return;
4415 break;
4380 }
4416 }
4417 used_at = 1;
4381 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4382 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4383 break;
4384
4385 case M_BGTUL_I:
4386 likely = 1;
4387 case M_BGTU_I:
4388 if (sreg == 0

--- 10 unchanged lines hidden (view full) ---

4399 if (mask == M_BGEUL_I)
4400 likely = 1;
4401 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4402 goto do_true;
4403 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4404 {
4405 macro_build (&offset_expr, likely ? "bnel" : "bne",
4406 "s,t,p", sreg, 0);
4418 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4419 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4420 break;
4421
4422 case M_BGTUL_I:
4423 likely = 1;
4424 case M_BGTU_I:
4425 if (sreg == 0

--- 10 unchanged lines hidden (view full) ---

4436 if (mask == M_BGEUL_I)
4437 likely = 1;
4438 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4439 goto do_true;
4440 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4441 {
4442 macro_build (&offset_expr, likely ? "bnel" : "bne",
4443 "s,t,p", sreg, 0);
4407 return;
4444 break;
4408 }
4445 }
4446 used_at = 1;
4409 set_at (sreg, 1);
4410 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4411 break;
4412
4413 case M_BGTL:
4414 likely = 1;
4415 case M_BGT:
4416 if (treg == 0)
4417 {
4418 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4447 set_at (sreg, 1);
4448 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4449 break;
4450
4451 case M_BGTL:
4452 likely = 1;
4453 case M_BGT:
4454 if (treg == 0)
4455 {
4456 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", sreg);
4419 return;
4457 break;
4420 }
4421 if (sreg == 0)
4422 {
4423 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4458 }
4459 if (sreg == 0)
4460 {
4461 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", treg);
4424 return;
4462 break;
4425 }
4463 }
4464 used_at = 1;
4426 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4427 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4428 break;
4429
4430 case M_BGTUL:
4431 likely = 1;
4432 case M_BGTU:
4433 if (treg == 0)
4434 {
4435 macro_build (&offset_expr, likely ? "bnel" : "bne",
4436 "s,t,p", sreg, 0);
4465 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4466 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4467 break;
4468
4469 case M_BGTUL:
4470 likely = 1;
4471 case M_BGTU:
4472 if (treg == 0)
4473 {
4474 macro_build (&offset_expr, likely ? "bnel" : "bne",
4475 "s,t,p", sreg, 0);
4437 return;
4476 break;
4438 }
4439 if (sreg == 0)
4440 goto do_false;
4477 }
4478 if (sreg == 0)
4479 goto do_false;
4480 used_at = 1;
4441 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4442 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4443 break;
4444
4445 case M_BLEL:
4446 likely = 1;
4447 case M_BLE:
4448 if (treg == 0)
4449 {
4450 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4481 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4482 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4483 break;
4484
4485 case M_BLEL:
4486 likely = 1;
4487 case M_BLE:
4488 if (treg == 0)
4489 {
4490 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4451 return;
4491 break;
4452 }
4453 if (sreg == 0)
4454 {
4455 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4492 }
4493 if (sreg == 0)
4494 {
4495 macro_build (&offset_expr, likely ? "bgezl" : "bgez", "s,p", treg);
4456 return;
4496 break;
4457 }
4497 }
4498 used_at = 1;
4458 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4459 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4460 break;
4461
4462 case M_BLEL_I:
4463 likely = 1;
4464 case M_BLE_I:
4465 maxnum = 0x7fffffff;

--- 14 unchanged lines hidden (view full) ---

4480 /* FALLTHROUGH */
4481 case M_BLT_I:
4482 case M_BLTL_I:
4483 if (mask == M_BLTL_I)
4484 likely = 1;
4485 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4486 {
4487 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4499 macro_build (NULL, "slt", "d,v,t", AT, treg, sreg);
4500 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4501 break;
4502
4503 case M_BLEL_I:
4504 likely = 1;
4505 case M_BLE_I:
4506 maxnum = 0x7fffffff;

--- 14 unchanged lines hidden (view full) ---

4521 /* FALLTHROUGH */
4522 case M_BLT_I:
4523 case M_BLTL_I:
4524 if (mask == M_BLTL_I)
4525 likely = 1;
4526 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4527 {
4528 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4488 return;
4529 break;
4489 }
4490 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4491 {
4492 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4530 }
4531 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4532 {
4533 macro_build (&offset_expr, likely ? "blezl" : "blez", "s,p", sreg);
4493 return;
4534 break;
4494 }
4535 }
4536 used_at = 1;
4495 set_at (sreg, 0);
4496 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4497 break;
4498
4499 case M_BLEUL:
4500 likely = 1;
4501 case M_BLEU:
4502 if (treg == 0)
4503 {
4504 macro_build (&offset_expr, likely ? "beql" : "beq",
4505 "s,t,p", sreg, 0);
4537 set_at (sreg, 0);
4538 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4539 break;
4540
4541 case M_BLEUL:
4542 likely = 1;
4543 case M_BLEU:
4544 if (treg == 0)
4545 {
4546 macro_build (&offset_expr, likely ? "beql" : "beq",
4547 "s,t,p", sreg, 0);
4506 return;
4548 break;
4507 }
4508 if (sreg == 0)
4509 goto do_true;
4549 }
4550 if (sreg == 0)
4551 goto do_true;
4552 used_at = 1;
4510 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4511 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4512 break;
4513
4514 case M_BLEUL_I:
4515 likely = 1;
4516 case M_BLEU_I:
4517 if (sreg == 0

--- 10 unchanged lines hidden (view full) ---

4528 if (mask == M_BLTUL_I)
4529 likely = 1;
4530 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4531 goto do_false;
4532 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4533 {
4534 macro_build (&offset_expr, likely ? "beql" : "beq",
4535 "s,t,p", sreg, 0);
4553 macro_build (NULL, "sltu", "d,v,t", AT, treg, sreg);
4554 macro_build (&offset_expr, likely ? "beql" : "beq", "s,t,p", AT, 0);
4555 break;
4556
4557 case M_BLEUL_I:
4558 likely = 1;
4559 case M_BLEU_I:
4560 if (sreg == 0

--- 10 unchanged lines hidden (view full) ---

4571 if (mask == M_BLTUL_I)
4572 likely = 1;
4573 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4574 goto do_false;
4575 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4576 {
4577 macro_build (&offset_expr, likely ? "beql" : "beq",
4578 "s,t,p", sreg, 0);
4536 return;
4579 break;
4537 }
4580 }
4581 used_at = 1;
4538 set_at (sreg, 1);
4539 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4540 break;
4541
4542 case M_BLTL:
4543 likely = 1;
4544 case M_BLT:
4545 if (treg == 0)
4546 {
4547 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4582 set_at (sreg, 1);
4583 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4584 break;
4585
4586 case M_BLTL:
4587 likely = 1;
4588 case M_BLT:
4589 if (treg == 0)
4590 {
4591 macro_build (&offset_expr, likely ? "bltzl" : "bltz", "s,p", sreg);
4548 return;
4592 break;
4549 }
4550 if (sreg == 0)
4551 {
4552 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4593 }
4594 if (sreg == 0)
4595 {
4596 macro_build (&offset_expr, likely ? "bgtzl" : "bgtz", "s,p", treg);
4553 return;
4597 break;
4554 }
4598 }
4599 used_at = 1;
4555 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4556 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4557 break;
4558
4559 case M_BLTUL:
4560 likely = 1;
4561 case M_BLTU:
4562 if (treg == 0)
4563 goto do_false;
4564 if (sreg == 0)
4565 {
4566 macro_build (&offset_expr, likely ? "bnel" : "bne",
4567 "s,t,p", 0, treg);
4600 macro_build (NULL, "slt", "d,v,t", AT, sreg, treg);
4601 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4602 break;
4603
4604 case M_BLTUL:
4605 likely = 1;
4606 case M_BLTU:
4607 if (treg == 0)
4608 goto do_false;
4609 if (sreg == 0)
4610 {
4611 macro_build (&offset_expr, likely ? "bnel" : "bne",
4612 "s,t,p", 0, treg);
4568 return;
4613 break;
4569 }
4614 }
4615 used_at = 1;
4570 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4571 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4572 break;
4573
4574 case M_DEXT:
4575 {
4576 unsigned long pos;
4577 unsigned long size;

--- 34 unchanged lines hidden (view full) ---

4612 }
4613 else
4614 {
4615 s = "dextm";
4616 fmt = "t,r,+A,+G";
4617 }
4618 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4619 }
4616 macro_build (NULL, "sltu", "d,v,t", AT, sreg, treg);
4617 macro_build (&offset_expr, likely ? "bnel" : "bne", "s,t,p", AT, 0);
4618 break;
4619
4620 case M_DEXT:
4621 {
4622 unsigned long pos;
4623 unsigned long size;

--- 34 unchanged lines hidden (view full) ---

4658 }
4659 else
4660 {
4661 s = "dextm";
4662 fmt = "t,r,+A,+G";
4663 }
4664 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos, size - 1);
4665 }
4620 return;
4666 break;
4621
4622 case M_DINS:
4623 {
4624 unsigned long pos;
4625 unsigned long size;
4626
4627 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4628 {

--- 32 unchanged lines hidden (view full) ---

4661 else
4662 {
4663 s = "dinsm";
4664 fmt = "t,r,+A,+F";
4665 }
4666 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4667 pos + size - 1);
4668 }
4667
4668 case M_DINS:
4669 {
4670 unsigned long pos;
4671 unsigned long size;
4672
4673 if (imm_expr.X_op != O_constant || imm2_expr.X_op != O_constant)
4674 {

--- 32 unchanged lines hidden (view full) ---

4707 else
4708 {
4709 s = "dinsm";
4710 fmt = "t,r,+A,+F";
4711 }
4712 macro_build ((expressionS *) NULL, s, fmt, treg, sreg, pos,
4713 pos + size - 1);
4714 }
4669 return;
4715 break;
4670
4671 case M_DDIV_3:
4672 dbl = 1;
4673 case M_DIV_3:
4674 s = "mflo";
4675 goto do_div3;
4676 case M_DREM_3:
4677 dbl = 1;
4678 case M_REM_3:
4679 s = "mfhi";
4680 do_div3:
4681 if (treg == 0)
4682 {
4683 as_warn (_("Divide by zero."));
4684 if (mips_trap)
4685 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4686 else
4687 macro_build (NULL, "break", "c", 7);
4716
4717 case M_DDIV_3:
4718 dbl = 1;
4719 case M_DIV_3:
4720 s = "mflo";
4721 goto do_div3;
4722 case M_DREM_3:
4723 dbl = 1;
4724 case M_REM_3:
4725 s = "mfhi";
4726 do_div3:
4727 if (treg == 0)
4728 {
4729 as_warn (_("Divide by zero."));
4730 if (mips_trap)
4731 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4732 else
4733 macro_build (NULL, "break", "c", 7);
4688 return;
4734 break;
4689 }
4690
4735 }
4736
4691 mips_emit_delays (TRUE);
4692 ++mips_opts.noreorder;
4693 mips_any_noreorder = 1;
4737 start_noreorder ();
4694 if (mips_trap)
4695 {
4696 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4697 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4698 }
4699 else
4700 {
4701 expr1.X_add_number = 8;
4702 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4703 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4704 macro_build (NULL, "break", "c", 7);
4705 }
4706 expr1.X_add_number = -1;
4738 if (mips_trap)
4739 {
4740 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4741 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4742 }
4743 else
4744 {
4745 expr1.X_add_number = 8;
4746 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4747 macro_build (NULL, dbl ? "ddiv" : "div", "z,s,t", sreg, treg);
4748 macro_build (NULL, "break", "c", 7);
4749 }
4750 expr1.X_add_number = -1;
4751 used_at = 1;
4707 load_register (AT, &expr1, dbl);
4708 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4709 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4710 if (dbl)
4711 {
4712 expr1.X_add_number = 1;
4713 load_register (AT, &expr1, dbl);
4714 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4715 }
4716 else
4717 {
4718 expr1.X_add_number = 0x80000000;
4719 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4720 }
4721 if (mips_trap)
4722 {
4723 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4724 /* We want to close the noreorder block as soon as possible, so
4725 that later insns are available for delay slot filling. */
4752 load_register (AT, &expr1, dbl);
4753 expr1.X_add_number = mips_trap ? (dbl ? 12 : 8) : (dbl ? 20 : 16);
4754 macro_build (&expr1, "bne", "s,t,p", treg, AT);
4755 if (dbl)
4756 {
4757 expr1.X_add_number = 1;
4758 load_register (AT, &expr1, dbl);
4759 macro_build (NULL, "dsll32", "d,w,<", AT, AT, 31);
4760 }
4761 else
4762 {
4763 expr1.X_add_number = 0x80000000;
4764 macro_build (&expr1, "lui", "t,u", AT, BFD_RELOC_HI16);
4765 }
4766 if (mips_trap)
4767 {
4768 macro_build (NULL, "teq", "s,t,q", sreg, AT, 6);
4769 /* We want to close the noreorder block as soon as possible, so
4770 that later insns are available for delay slot filling. */
4726 --mips_opts.noreorder;
4771 end_noreorder ();
4727 }
4728 else
4729 {
4730 expr1.X_add_number = 8;
4731 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4732 macro_build (NULL, "nop", "", 0);
4733
4734 /* We want to close the noreorder block as soon as possible, so
4735 that later insns are available for delay slot filling. */
4772 }
4773 else
4774 {
4775 expr1.X_add_number = 8;
4776 macro_build (&expr1, "bne", "s,t,p", sreg, AT);
4777 macro_build (NULL, "nop", "", 0);
4778
4779 /* We want to close the noreorder block as soon as possible, so
4780 that later insns are available for delay slot filling. */
4736 --mips_opts.noreorder;
4781 end_noreorder ();
4737
4738 macro_build (NULL, "break", "c", 6);
4739 }
4740 macro_build (NULL, s, "d", dreg);
4741 break;
4742
4743 case M_DIV_3I:
4744 s = "div";

--- 33 unchanged lines hidden (view full) ---

4778 do_divi:
4779 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4780 {
4781 as_warn (_("Divide by zero."));
4782 if (mips_trap)
4783 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4784 else
4785 macro_build (NULL, "break", "c", 7);
4782
4783 macro_build (NULL, "break", "c", 6);
4784 }
4785 macro_build (NULL, s, "d", dreg);
4786 break;
4787
4788 case M_DIV_3I:
4789 s = "div";

--- 33 unchanged lines hidden (view full) ---

4823 do_divi:
4824 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
4825 {
4826 as_warn (_("Divide by zero."));
4827 if (mips_trap)
4828 macro_build (NULL, "teq", "s,t,q", 0, 0, 7);
4829 else
4830 macro_build (NULL, "break", "c", 7);
4786 return;
4831 break;
4787 }
4788 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4789 {
4790 if (strcmp (s2, "mflo") == 0)
4791 move_register (dreg, sreg);
4792 else
4793 move_register (dreg, 0);
4832 }
4833 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 1)
4834 {
4835 if (strcmp (s2, "mflo") == 0)
4836 move_register (dreg, sreg);
4837 else
4838 move_register (dreg, 0);
4794 return;
4839 break;
4795 }
4796 if (imm_expr.X_op == O_constant
4797 && imm_expr.X_add_number == -1
4798 && s[strlen (s) - 1] != 'u')
4799 {
4800 if (strcmp (s2, "mflo") == 0)
4801 {
4802 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4803 }
4804 else
4805 move_register (dreg, 0);
4840 }
4841 if (imm_expr.X_op == O_constant
4842 && imm_expr.X_add_number == -1
4843 && s[strlen (s) - 1] != 'u')
4844 {
4845 if (strcmp (s2, "mflo") == 0)
4846 {
4847 macro_build (NULL, dbl ? "dneg" : "neg", "d,w", dreg, sreg);
4848 }
4849 else
4850 move_register (dreg, 0);
4806 return;
4851 break;
4807 }
4808
4852 }
4853
4854 used_at = 1;
4809 load_register (AT, &imm_expr, dbl);
4810 macro_build (NULL, s, "z,s,t", sreg, AT);
4811 macro_build (NULL, s2, "d", dreg);
4812 break;
4813
4814 case M_DIVU_3:
4815 s = "divu";
4816 s2 = "mflo";

--- 5 unchanged lines hidden (view full) ---

4822 case M_DDIVU_3:
4823 s = "ddivu";
4824 s2 = "mflo";
4825 goto do_divu3;
4826 case M_DREMU_3:
4827 s = "ddivu";
4828 s2 = "mfhi";
4829 do_divu3:
4855 load_register (AT, &imm_expr, dbl);
4856 macro_build (NULL, s, "z,s,t", sreg, AT);
4857 macro_build (NULL, s2, "d", dreg);
4858 break;
4859
4860 case M_DIVU_3:
4861 s = "divu";
4862 s2 = "mflo";

--- 5 unchanged lines hidden (view full) ---

4868 case M_DDIVU_3:
4869 s = "ddivu";
4870 s2 = "mflo";
4871 goto do_divu3;
4872 case M_DREMU_3:
4873 s = "ddivu";
4874 s2 = "mfhi";
4875 do_divu3:
4830 mips_emit_delays (TRUE);
4831 ++mips_opts.noreorder;
4832 mips_any_noreorder = 1;
4876 start_noreorder ();
4833 if (mips_trap)
4834 {
4835 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4836 macro_build (NULL, s, "z,s,t", sreg, treg);
4837 /* We want to close the noreorder block as soon as possible, so
4838 that later insns are available for delay slot filling. */
4877 if (mips_trap)
4878 {
4879 macro_build (NULL, "teq", "s,t,q", treg, 0, 7);
4880 macro_build (NULL, s, "z,s,t", sreg, treg);
4881 /* We want to close the noreorder block as soon as possible, so
4882 that later insns are available for delay slot filling. */
4839 --mips_opts.noreorder;
4883 end_noreorder ();
4840 }
4841 else
4842 {
4843 expr1.X_add_number = 8;
4844 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4845 macro_build (NULL, s, "z,s,t", sreg, treg);
4846
4847 /* We want to close the noreorder block as soon as possible, so
4848 that later insns are available for delay slot filling. */
4884 }
4885 else
4886 {
4887 expr1.X_add_number = 8;
4888 macro_build (&expr1, "bne", "s,t,p", treg, 0);
4889 macro_build (NULL, s, "z,s,t", sreg, treg);
4890
4891 /* We want to close the noreorder block as soon as possible, so
4892 that later insns are available for delay slot filling. */
4849 --mips_opts.noreorder;
4893 end_noreorder ();
4850 macro_build (NULL, "break", "c", 7);
4851 }
4852 macro_build (NULL, s2, "d", dreg);
4894 macro_build (NULL, "break", "c", 7);
4895 }
4896 macro_build (NULL, s2, "d", dreg);
4853 return;
4897 break;
4854
4855 case M_DLCA_AB:
4856 dbl = 1;
4857 case M_LCA_AB:
4858 call = 1;
4859 goto do_la;
4860 case M_DLA_AB:
4861 dbl = 1;

--- 7 unchanged lines hidden (view full) ---

4869
4870 if (! dbl && HAVE_64BIT_OBJECTS)
4871 as_warn (_("la used to load 64-bit address"));
4872
4873 if (offset_expr.X_op == O_constant
4874 && offset_expr.X_add_number >= -0x8000
4875 && offset_expr.X_add_number < 0x8000)
4876 {
4898
4899 case M_DLCA_AB:
4900 dbl = 1;
4901 case M_LCA_AB:
4902 call = 1;
4903 goto do_la;
4904 case M_DLA_AB:
4905 dbl = 1;

--- 7 unchanged lines hidden (view full) ---

4913
4914 if (! dbl && HAVE_64BIT_OBJECTS)
4915 as_warn (_("la used to load 64-bit address"));
4916
4917 if (offset_expr.X_op == O_constant
4918 && offset_expr.X_add_number >= -0x8000
4919 && offset_expr.X_add_number < 0x8000)
4920 {
4877 macro_build (&offset_expr,
4878 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4921 macro_build (&offset_expr, ADDRESS_ADDI_INSN,
4879 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4922 "t,r,j", treg, sreg, BFD_RELOC_LO16);
4880 return;
4923 break;
4881 }
4882
4924 }
4925
4883 if (treg == breg)
4926 if (!mips_opts.noat && (treg == breg))
4884 {
4885 tempreg = AT;
4886 used_at = 1;
4887 }
4888 else
4889 {
4890 tempreg = treg;
4927 {
4928 tempreg = AT;
4929 used_at = 1;
4930 }
4931 else
4932 {
4933 tempreg = treg;
4891 used_at = 0;
4892 }
4893
4934 }
4935
4894 /* When generating embedded PIC code, we permit expressions of
4895 the form
4896 la $treg,foo-bar
4897 la $treg,foo-bar($breg)
4898 where bar is an address in the current section. These are used
4899 when getting the addresses of functions. We don't permit
4900 X_add_number to be non-zero, because if the symbol is
4901 external the relaxing code needs to know that any addend is
4902 purely the offset to X_op_symbol. */
4903 if (mips_pic == EMBEDDED_PIC
4904 && offset_expr.X_op == O_subtract
4905 && (symbol_constant_p (offset_expr.X_op_symbol)
4906 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
4907 : (symbol_equated_p (offset_expr.X_op_symbol)
4908 && (S_GET_SEGMENT
4909 (symbol_get_value_expression (offset_expr.X_op_symbol)
4910 ->X_add_symbol)
4911 == now_seg)))
4912 && (offset_expr.X_add_number == 0
4913 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
4914 {
4915 if (breg == 0)
4916 {
4917 tempreg = treg;
4918 used_at = 0;
4919 macro_build (&offset_expr, "lui", "t,u",
4920 tempreg, BFD_RELOC_PCREL_HI16_S);
4921 }
4922 else
4923 {
4924 macro_build (&offset_expr, "lui", "t,u",
4925 tempreg, BFD_RELOC_PCREL_HI16_S);
4926 macro_build (NULL,
4927 (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu",
4928 "d,v,t", tempreg, tempreg, breg);
4929 }
4930 macro_build (&offset_expr,
4931 (dbl || HAVE_64BIT_ADDRESSES) ? "daddiu" : "addiu",
4932 "t,r,j", treg, tempreg, BFD_RELOC_PCREL_LO16);
4933 if (! used_at)
4934 return;
4935 break;
4936 }
4937
4938 if (offset_expr.X_op != O_symbol
4939 && offset_expr.X_op != O_constant)
4940 {
4941 as_bad (_("expression too complex"));
4942 offset_expr.X_op = O_constant;
4943 }
4944
4945 if (offset_expr.X_op == O_constant)
4936 if (offset_expr.X_op != O_symbol
4937 && offset_expr.X_op != O_constant)
4938 {
4939 as_bad (_("expression too complex"));
4940 offset_expr.X_op = O_constant;
4941 }
4942
4943 if (offset_expr.X_op == O_constant)
4946 load_register (tempreg, &offset_expr,
4947 ((mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
4948 ? (dbl || HAVE_64BIT_ADDRESSES)
4949 : HAVE_64BIT_ADDRESSES));
4944 load_register (tempreg, &offset_expr, HAVE_64BIT_ADDRESSES);
4950 else if (mips_pic == NO_PIC)
4951 {
4952 /* If this is a reference to a GP relative symbol, we want
4953 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4954 Otherwise we want
4955 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4956 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4957 If we have a constant, we need two instructions anyhow,
4958 so we may as well always use the latter form.
4959
4945 else if (mips_pic == NO_PIC)
4946 {
4947 /* If this is a reference to a GP relative symbol, we want
4948 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
4949 Otherwise we want
4950 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
4951 addiu $tempreg,$tempreg,<sym> (BFD_RELOC_LO16)
4952 If we have a constant, we need two instructions anyhow,
4953 so we may as well always use the latter form.
4954
4960 With 64bit address space and a usable $at we want
4961 lui $tempreg, (BFD_RELOC_MIPS_HIGHEST)
4962 lui $at, (BFD_RELOC_HI16_S)
4963 daddiu $tempreg, (BFD_RELOC_MIPS_HIGHER)
4964 daddiu $at, (BFD_RELOC_LO16)
4965 dsll32 $tempreg,0
4966 daddu $tempreg,$tempreg,$at
4955 With 64bit address space and a usable $at we want
4956 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4957 lui $at,<sym> (BFD_RELOC_HI16_S)
4958 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4959 daddiu $at,<sym> (BFD_RELOC_LO16)
4960 dsll32 $tempreg,0
4961 daddu $tempreg,$tempreg,$at
4967
4962
4968 If $at is already in use, we use a path which is suboptimal
4969 on superscalar processors.
4970 lui $tempreg, (BFD_RELOC_MIPS_HIGHEST)
4971 daddiu $tempreg, (BFD_RELOC_MIPS_HIGHER)
4972 dsll $tempreg,16
4973 daddiu $tempreg, (BFD_RELOC_HI16_S)
4974 dsll $tempreg,16
4975 daddiu $tempreg, (BFD_RELOC_LO16)
4976 */
4977 if (HAVE_64BIT_ADDRESSES)
4963 If $at is already in use, we use a path which is suboptimal
4964 on superscalar processors.
4965 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
4966 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
4967 dsll $tempreg,16
4968 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
4969 dsll $tempreg,16
4970 daddiu $tempreg,<sym> (BFD_RELOC_LO16)
4971
4972 For GP relative symbols in 64bit address space we can use
4973 the same sequence as in 32bit address space. */
4974 if (HAVE_64BIT_SYMBOLS)
4978 {
4975 {
4979 /* ??? We don't provide a GP-relative alternative for
4980 these macros. It used not to be possible with the
4981 original relaxation code, but it could be done now. */
4976 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
4977 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
4978 {
4979 relax_start (offset_expr.X_add_symbol);
4980 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
4981 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
4982 relax_switch ();
4983 }
4982
4984
4983 if (used_at == 0 && ! mips_opts.noat)
4985 if (used_at == 0 && !mips_opts.noat)
4984 {
4985 macro_build (&offset_expr, "lui", "t,u",
4986 tempreg, BFD_RELOC_MIPS_HIGHEST);
4987 macro_build (&offset_expr, "lui", "t,u",
4988 AT, BFD_RELOC_HI16_S);
4989 macro_build (&offset_expr, "daddiu", "t,r,j",
4990 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4991 macro_build (&offset_expr, "daddiu", "t,r,j",

--- 10 unchanged lines hidden (view full) ---

5002 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5003 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5004 macro_build (&offset_expr, "daddiu", "t,r,j",
5005 tempreg, tempreg, BFD_RELOC_HI16_S);
5006 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5007 macro_build (&offset_expr, "daddiu", "t,r,j",
5008 tempreg, tempreg, BFD_RELOC_LO16);
5009 }
4986 {
4987 macro_build (&offset_expr, "lui", "t,u",
4988 tempreg, BFD_RELOC_MIPS_HIGHEST);
4989 macro_build (&offset_expr, "lui", "t,u",
4990 AT, BFD_RELOC_HI16_S);
4991 macro_build (&offset_expr, "daddiu", "t,r,j",
4992 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
4993 macro_build (&offset_expr, "daddiu", "t,r,j",

--- 10 unchanged lines hidden (view full) ---

5004 tempreg, tempreg, BFD_RELOC_MIPS_HIGHER);
5005 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5006 macro_build (&offset_expr, "daddiu", "t,r,j",
5007 tempreg, tempreg, BFD_RELOC_HI16_S);
5008 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
5009 macro_build (&offset_expr, "daddiu", "t,r,j",
5010 tempreg, tempreg, BFD_RELOC_LO16);
5011 }
5012
5013 if (mips_relax.sequence)
5014 relax_end ();
5010 }
5011 else
5012 {
5013 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5015 }
5016 else
5017 {
5018 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5014 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
5019 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5015 {
5016 relax_start (offset_expr.X_add_symbol);
5017 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5018 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5019 relax_switch ();
5020 }
5020 {
5021 relax_start (offset_expr.X_add_symbol);
5022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5023 tempreg, mips_gp_register, BFD_RELOC_GPREL16);
5024 relax_switch ();
5025 }
5026 if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5027 as_bad (_("offset too large"));
5021 macro_build_lui (&offset_expr, tempreg);
5022 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5023 tempreg, tempreg, BFD_RELOC_LO16);
5024 if (mips_relax.sequence)
5025 relax_end ();
5026 }
5027 }
5028 macro_build_lui (&offset_expr, tempreg);
5029 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5030 tempreg, tempreg, BFD_RELOC_LO16);
5031 if (mips_relax.sequence)
5032 relax_end ();
5033 }
5034 }
5028 else if (mips_pic == SVR4_PIC && ! mips_big_got && ! HAVE_NEWABI)
5035 else if (!mips_big_got && !HAVE_NEWABI)
5029 {
5030 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5031
5032 /* If this is a reference to an external symbol, and there
5033 is no constant, we want
5034 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5035 or for lca or if tempreg is PIC_CALL_REG
5036 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)

--- 19 unchanged lines hidden (view full) ---

5056 addu $tempreg,$tempreg,$at
5057 For a local symbol, we want the same instruction
5058 sequence, but we output a BFD_RELOC_LO16 reloc on the
5059 addiu instruction.
5060 */
5061
5062 if (offset_expr.X_add_number == 0)
5063 {
5036 {
5037 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5038
5039 /* If this is a reference to an external symbol, and there
5040 is no constant, we want
5041 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
5042 or for lca or if tempreg is PIC_CALL_REG
5043 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_CALL16)

--- 19 unchanged lines hidden (view full) ---

5063 addu $tempreg,$tempreg,$at
5064 For a local symbol, we want the same instruction
5065 sequence, but we output a BFD_RELOC_LO16 reloc on the
5066 addiu instruction.
5067 */
5068
5069 if (offset_expr.X_add_number == 0)
5070 {
5064 if (breg == 0 && (call || tempreg == PIC_CALL_REG))
5071 if (mips_pic == SVR4_PIC
5072 && breg == 0
5073 && (call || tempreg == PIC_CALL_REG))
5065 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5066
5067 relax_start (offset_expr.X_add_symbol);
5068 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5069 lw_reloc_type, mips_gp_register);
5070 if (breg != 0)
5071 {
5072 /* We're going to put in an addu instruction using
5073 tempreg, so we may as well insert the nop right
5074 now. */
5074 lw_reloc_type = (int) BFD_RELOC_MIPS_CALL16;
5075
5076 relax_start (offset_expr.X_add_symbol);
5077 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5078 lw_reloc_type, mips_gp_register);
5079 if (breg != 0)
5080 {
5081 /* We're going to put in an addu instruction using
5082 tempreg, so we may as well insert the nop right
5083 now. */
5075 macro_build (NULL, "nop", "");
5084 load_delay_nop ();
5076 }
5077 relax_switch ();
5078 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5079 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5085 }
5086 relax_switch ();
5087 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5088 tempreg, BFD_RELOC_MIPS_GOT16, mips_gp_register);
5080 macro_build (NULL, "nop", "");
5089 load_delay_nop ();
5081 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5082 tempreg, tempreg, BFD_RELOC_LO16);
5083 relax_end ();
5084 /* FIXME: If breg == 0, and the next instruction uses
5085 $tempreg, then if this variant case is used an extra
5086 nop will be generated. */
5087 }
5088 else if (offset_expr.X_add_number >= -0x8000
5089 && offset_expr.X_add_number < 0x8000)
5090 {
5091 load_got_offset (tempreg, &offset_expr);
5090 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5091 tempreg, tempreg, BFD_RELOC_LO16);
5092 relax_end ();
5093 /* FIXME: If breg == 0, and the next instruction uses
5094 $tempreg, then if this variant case is used an extra
5095 nop will be generated. */
5096 }
5097 else if (offset_expr.X_add_number >= -0x8000
5098 && offset_expr.X_add_number < 0x8000)
5099 {
5100 load_got_offset (tempreg, &offset_expr);
5092 macro_build (NULL, "nop", "");
5101 load_delay_nop ();
5093 add_got_offset (tempreg, &offset_expr);
5094 }
5095 else
5096 {
5097 expr1.X_add_number = offset_expr.X_add_number;
5098 offset_expr.X_add_number =
5099 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5100 load_got_offset (tempreg, &offset_expr);
5101 offset_expr.X_add_number = expr1.X_add_number;
5102 /* If we are going to add in a base register, and the
5103 target register and the base register are the same,
5104 then we are using AT as a temporary register. Since
5105 we want to load the constant into AT, we add our
5106 current AT (from the global offset table) and the
5107 register into the register now, and pretend we were
5108 not using a base register. */
5109 if (breg == treg)
5110 {
5102 add_got_offset (tempreg, &offset_expr);
5103 }
5104 else
5105 {
5106 expr1.X_add_number = offset_expr.X_add_number;
5107 offset_expr.X_add_number =
5108 ((offset_expr.X_add_number + 0x8000) & 0xffff) - 0x8000;
5109 load_got_offset (tempreg, &offset_expr);
5110 offset_expr.X_add_number = expr1.X_add_number;
5111 /* If we are going to add in a base register, and the
5112 target register and the base register are the same,
5113 then we are using AT as a temporary register. Since
5114 we want to load the constant into AT, we add our
5115 current AT (from the global offset table) and the
5116 register into the register now, and pretend we were
5117 not using a base register. */
5118 if (breg == treg)
5119 {
5111 macro_build (NULL, "nop", "");
5120 load_delay_nop ();
5112 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5113 treg, AT, breg);
5114 breg = 0;
5115 tempreg = treg;
5116 }
5117 add_got_offset_hilo (tempreg, &offset_expr, AT);
5118 used_at = 1;
5119 }
5120 }
5121 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5122 treg, AT, breg);
5123 breg = 0;
5124 tempreg = treg;
5125 }
5126 add_got_offset_hilo (tempreg, &offset_expr, AT);
5127 used_at = 1;
5128 }
5129 }
5121 else if (mips_pic == SVR4_PIC && ! mips_big_got && HAVE_NEWABI)
5130 else if (!mips_big_got && HAVE_NEWABI)
5122 {
5123 int add_breg_early = 0;
5124
5125 /* If this is a reference to an external, and there is no
5126 constant, or local symbol (*), with or without a
5127 constant, we want
5128 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5129 or for lca or if tempreg is PIC_CALL_REG

--- 86 unchanged lines hidden (view full) ---

5216 relax_end ();
5217 }
5218 else
5219 {
5220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5221 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5222 }
5223 }
5131 {
5132 int add_breg_early = 0;
5133
5134 /* If this is a reference to an external, and there is no
5135 constant, or local symbol (*), with or without a
5136 constant, we want
5137 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_DISP)
5138 or for lca or if tempreg is PIC_CALL_REG

--- 86 unchanged lines hidden (view full) ---

5225 relax_end ();
5226 }
5227 else
5228 {
5229 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5230 BFD_RELOC_MIPS_GOT_DISP, mips_gp_register);
5231 }
5232 }
5224 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
5233 else if (mips_big_got && !HAVE_NEWABI)
5225 {
5226 int gpdelay;
5227 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5228 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5229 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5230
5231 /* This is the large GOT case. If this is a reference to an
5232 external symbol, and there is no constant, we want

--- 53 unchanged lines hidden (view full) ---

5286 tempreg, lw_reloc_type, tempreg);
5287 if (expr1.X_add_number == 0)
5288 {
5289 if (breg != 0)
5290 {
5291 /* We're going to put in an addu instruction using
5292 tempreg, so we may as well insert the nop right
5293 now. */
5234 {
5235 int gpdelay;
5236 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5237 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5238 int local_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
5239
5240 /* This is the large GOT case. If this is a reference to an
5241 external symbol, and there is no constant, we want

--- 53 unchanged lines hidden (view full) ---

5295 tempreg, lw_reloc_type, tempreg);
5296 if (expr1.X_add_number == 0)
5297 {
5298 if (breg != 0)
5299 {
5300 /* We're going to put in an addu instruction using
5301 tempreg, so we may as well insert the nop right
5302 now. */
5294 macro_build (NULL, "nop", "");
5303 load_delay_nop ();
5295 }
5296 }
5297 else if (expr1.X_add_number >= -0x8000
5298 && expr1.X_add_number < 0x8000)
5299 {
5304 }
5305 }
5306 else if (expr1.X_add_number >= -0x8000
5307 && expr1.X_add_number < 0x8000)
5308 {
5300 macro_build (NULL, "nop", "");
5309 load_delay_nop ();
5301 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5302 tempreg, tempreg, BFD_RELOC_LO16);
5303 }
5304 else
5305 {
5306 int dreg;
5307
5308 /* If we are going to add in a base register, and the
5309 target register and the base register are the same,
5310 then we are using AT as a temporary register. Since
5311 we want to load the constant into AT, we add our
5312 current AT (from the global offset table) and the
5313 register into the register now, and pretend we were
5314 not using a base register. */
5315 if (breg != treg)
5316 dreg = tempreg;
5317 else
5318 {
5319 assert (tempreg == AT);
5310 macro_build (&expr1, ADDRESS_ADDI_INSN, "t,r,j",
5311 tempreg, tempreg, BFD_RELOC_LO16);
5312 }
5313 else
5314 {
5315 int dreg;
5316
5317 /* If we are going to add in a base register, and the
5318 target register and the base register are the same,
5319 then we are using AT as a temporary register. Since
5320 we want to load the constant into AT, we add our
5321 current AT (from the global offset table) and the
5322 register into the register now, and pretend we were
5323 not using a base register. */
5324 if (breg != treg)
5325 dreg = tempreg;
5326 else
5327 {
5328 assert (tempreg == AT);
5320 macro_build (NULL, "nop", "");
5329 load_delay_nop ();
5321 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5322 treg, AT, breg);
5323 dreg = treg;
5324 }
5325
5326 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5327 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5328

--- 10 unchanged lines hidden (view full) ---

5339 macro_build (NULL, "nop", "");
5340 }
5341
5342 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5343 local_reloc_type, mips_gp_register);
5344 if (expr1.X_add_number >= -0x8000
5345 && expr1.X_add_number < 0x8000)
5346 {
5330 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5331 treg, AT, breg);
5332 dreg = treg;
5333 }
5334
5335 load_register (AT, &expr1, HAVE_64BIT_ADDRESSES);
5336 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", dreg, dreg, AT);
5337

--- 10 unchanged lines hidden (view full) ---

5348 macro_build (NULL, "nop", "");
5349 }
5350
5351 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
5352 local_reloc_type, mips_gp_register);
5353 if (expr1.X_add_number >= -0x8000
5354 && expr1.X_add_number < 0x8000)
5355 {
5347 macro_build (NULL, "nop", "");
5356 load_delay_nop ();
5348 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5349 tempreg, tempreg, BFD_RELOC_LO16);
5350 /* FIXME: If add_number is 0, and there was no base
5351 register, the external symbol case ended with a load,
5352 so if the symbol turns out to not be external, and
5353 the next instruction uses tempreg, an unnecessary nop
5354 will be inserted. */
5355 }
5356 else
5357 {
5358 if (breg == treg)
5359 {
5360 /* We must add in the base register now, as in the
5361 external symbol case. */
5362 assert (tempreg == AT);
5357 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5358 tempreg, tempreg, BFD_RELOC_LO16);
5359 /* FIXME: If add_number is 0, and there was no base
5360 register, the external symbol case ended with a load,
5361 so if the symbol turns out to not be external, and
5362 the next instruction uses tempreg, an unnecessary nop
5363 will be inserted. */
5364 }
5365 else
5366 {
5367 if (breg == treg)
5368 {
5369 /* We must add in the base register now, as in the
5370 external symbol case. */
5371 assert (tempreg == AT);
5363 macro_build (NULL, "nop", "");
5372 load_delay_nop ();
5364 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5365 treg, AT, breg);
5366 tempreg = treg;
5367 /* We set breg to 0 because we have arranged to add
5368 it in in both cases. */
5369 breg = 0;
5370 }
5371
5372 macro_build_lui (&expr1, AT);
5373 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5374 AT, AT, BFD_RELOC_LO16);
5375 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5376 tempreg, tempreg, AT);
5373 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5374 treg, AT, breg);
5375 tempreg = treg;
5376 /* We set breg to 0 because we have arranged to add
5377 it in in both cases. */
5378 breg = 0;
5379 }
5380
5381 macro_build_lui (&expr1, AT);
5382 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5383 AT, AT, BFD_RELOC_LO16);
5384 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5385 tempreg, tempreg, AT);
5386 used_at = 1;
5377 }
5378 relax_end ();
5379 }
5387 }
5388 relax_end ();
5389 }
5380 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
5390 else if (mips_big_got && HAVE_NEWABI)
5381 {
5382 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5383 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5384 int add_breg_early = 0;
5385
5386 /* This is the large GOT case. If this is a reference to an
5387 external symbol, and there is no constant, we want
5388 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)

--- 90 unchanged lines hidden (view full) ---

5479 {
5480 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5481 treg, tempreg, breg);
5482 breg = 0;
5483 tempreg = treg;
5484 }
5485 relax_end ();
5486 }
5391 {
5392 int lui_reloc_type = (int) BFD_RELOC_MIPS_GOT_HI16;
5393 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT_LO16;
5394 int add_breg_early = 0;
5395
5396 /* This is the large GOT case. If this is a reference to an
5397 external symbol, and there is no constant, we want
5398 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)

--- 90 unchanged lines hidden (view full) ---

5489 {
5490 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5491 treg, tempreg, breg);
5492 breg = 0;
5493 tempreg = treg;
5494 }
5495 relax_end ();
5496 }
5487 else if (mips_pic == EMBEDDED_PIC)
5488 {
5489 /* We use
5490 addiu $tempreg,$gp,<sym> (BFD_RELOC_GPREL16)
5491 */
5492 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
5493 mips_gp_register, BFD_RELOC_GPREL16);
5494 }
5495 else
5496 abort ();
5497
5498 if (breg != 0)
5497 else
5498 abort ();
5499
5500 if (breg != 0)
5499 {
5500 char *s;
5501
5502 if (mips_pic == EMBEDDED_PIC || mips_pic == NO_PIC)
5503 s = (dbl || HAVE_64BIT_ADDRESSES) ? "daddu" : "addu";
5504 else
5505 s = ADDRESS_ADD_INSN;
5506
5507 macro_build (NULL, s, "d,v,t", treg, tempreg, breg);
5508 }
5509
5510 if (! used_at)
5511 return;
5512
5501 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
5513 break;
5514
5515 case M_J_A:
5516 /* The j instruction may not be used in PIC code, since it
5517 requires an absolute address. We convert it to a b
5518 instruction. */
5519 if (mips_pic == NO_PIC)
5520 macro_build (&offset_expr, "j", "a");
5521 else
5522 macro_build (&offset_expr, "b", "p");
5502 break;
5503
5504 case M_J_A:
5505 /* The j instruction may not be used in PIC code, since it
5506 requires an absolute address. We convert it to a b
5507 instruction. */
5508 if (mips_pic == NO_PIC)
5509 macro_build (&offset_expr, "j", "a");
5510 else
5511 macro_build (&offset_expr, "b", "p");
5523 return;
5512 break;
5524
5525 /* The jal instructions must be handled as macros because when
5526 generating PIC code they expand to multi-instruction
5527 sequences. Normally they are simple instructions. */
5528 case M_JAL_1:
5529 dreg = RA;
5530 /* Fall through. */
5531 case M_JAL_2:
5513
5514 /* The jal instructions must be handled as macros because when
5515 generating PIC code they expand to multi-instruction
5516 sequences. Normally they are simple instructions. */
5517 case M_JAL_1:
5518 dreg = RA;
5519 /* Fall through. */
5520 case M_JAL_2:
5532 if (mips_pic == NO_PIC
5533 || mips_pic == EMBEDDED_PIC)
5521 if (mips_pic == NO_PIC)
5534 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5522 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5535 else if (mips_pic == SVR4_PIC)
5523 else
5536 {
5537 if (sreg != PIC_CALL_REG)
5538 as_warn (_("MIPS PIC call to register other than $25"));
5539
5540 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5524 {
5525 if (sreg != PIC_CALL_REG)
5526 as_warn (_("MIPS PIC call to register other than $25"));
5527
5528 macro_build (NULL, "jalr", "d,s", dreg, sreg);
5541 if (! HAVE_NEWABI)
5529 if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
5542 {
5543 if (mips_cprestore_offset < 0)
5544 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5545 else
5546 {
5547 if (! mips_frame_reg_valid)
5548 {
5549 as_warn (_("No .frame pseudo-op used in PIC code"));

--- 9 unchanged lines hidden (view full) ---

5559 expr1.X_add_number = mips_cprestore_offset;
5560 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5561 mips_gp_register,
5562 mips_frame_reg,
5563 HAVE_64BIT_ADDRESSES);
5564 }
5565 }
5566 }
5530 {
5531 if (mips_cprestore_offset < 0)
5532 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5533 else
5534 {
5535 if (! mips_frame_reg_valid)
5536 {
5537 as_warn (_("No .frame pseudo-op used in PIC code"));

--- 9 unchanged lines hidden (view full) ---

5547 expr1.X_add_number = mips_cprestore_offset;
5548 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5549 mips_gp_register,
5550 mips_frame_reg,
5551 HAVE_64BIT_ADDRESSES);
5552 }
5553 }
5554 }
5567 else
5568 abort ();
5569
5555
5570 return;
5556 break;
5571
5572 case M_JAL_A:
5573 if (mips_pic == NO_PIC)
5574 macro_build (&offset_expr, "jal", "a");
5575 else if (mips_pic == SVR4_PIC)
5576 {
5577 /* If this is a reference to an external symbol, and we are
5578 using a small GOT, we want

--- 62 unchanged lines hidden (view full) ---

5641 else
5642 {
5643 relax_start (offset_expr.X_add_symbol);
5644 if (! mips_big_got)
5645 {
5646 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5647 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5648 mips_gp_register);
5557
5558 case M_JAL_A:
5559 if (mips_pic == NO_PIC)
5560 macro_build (&offset_expr, "jal", "a");
5561 else if (mips_pic == SVR4_PIC)
5562 {
5563 /* If this is a reference to an external symbol, and we are
5564 using a small GOT, we want

--- 62 unchanged lines hidden (view full) ---

5627 else
5628 {
5629 relax_start (offset_expr.X_add_symbol);
5630 if (! mips_big_got)
5631 {
5632 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5633 PIC_CALL_REG, BFD_RELOC_MIPS_CALL16,
5634 mips_gp_register);
5649 macro_build (NULL, "nop", "");
5635 load_delay_nop ();
5650 relax_switch ();
5651 }
5652 else
5653 {
5654 int gpdelay;
5655
5656 gpdelay = reg_needs_delay (mips_gp_register);
5657 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5658 BFD_RELOC_MIPS_CALL_HI16);
5659 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5660 PIC_CALL_REG, mips_gp_register);
5661 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5662 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5663 PIC_CALL_REG);
5636 relax_switch ();
5637 }
5638 else
5639 {
5640 int gpdelay;
5641
5642 gpdelay = reg_needs_delay (mips_gp_register);
5643 macro_build (&offset_expr, "lui", "t,u", PIC_CALL_REG,
5644 BFD_RELOC_MIPS_CALL_HI16);
5645 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", PIC_CALL_REG,
5646 PIC_CALL_REG, mips_gp_register);
5647 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5648 PIC_CALL_REG, BFD_RELOC_MIPS_CALL_LO16,
5649 PIC_CALL_REG);
5664 macro_build (NULL, "nop", "");
5650 load_delay_nop ();
5665 relax_switch ();
5666 if (gpdelay)
5667 macro_build (NULL, "nop", "");
5668 }
5669 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5670 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5671 mips_gp_register);
5651 relax_switch ();
5652 if (gpdelay)
5653 macro_build (NULL, "nop", "");
5654 }
5655 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
5656 PIC_CALL_REG, BFD_RELOC_MIPS_GOT16,
5657 mips_gp_register);
5672 macro_build (NULL, "nop", "");
5658 load_delay_nop ();
5673 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5674 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5675 relax_end ();
5676 macro_build_jalr (&offset_expr);
5677
5678 if (mips_cprestore_offset < 0)
5679 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5680 else

--- 15 unchanged lines hidden (view full) ---

5696 expr1.X_add_number = mips_cprestore_offset;
5697 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5698 mips_gp_register,
5699 mips_frame_reg,
5700 HAVE_64BIT_ADDRESSES);
5701 }
5702 }
5703 }
5659 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
5660 PIC_CALL_REG, PIC_CALL_REG, BFD_RELOC_LO16);
5661 relax_end ();
5662 macro_build_jalr (&offset_expr);
5663
5664 if (mips_cprestore_offset < 0)
5665 as_warn (_("No .cprestore pseudo-op used in PIC code"));
5666 else

--- 15 unchanged lines hidden (view full) ---

5682 expr1.X_add_number = mips_cprestore_offset;
5683 macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN,
5684 mips_gp_register,
5685 mips_frame_reg,
5686 HAVE_64BIT_ADDRESSES);
5687 }
5688 }
5689 }
5704 else if (mips_pic == EMBEDDED_PIC)
5705 {
5706 macro_build (&offset_expr, "bal", "p");
5707 /* The linker may expand the call to a longer sequence which
5708 uses $at, so we must break rather than return. */
5709 break;
5710 }
5711 else
5712 abort ();
5713
5690 else
5691 abort ();
5692
5714 return;
5693 break;
5715
5716 case M_LB_AB:
5717 s = "lb";
5718 goto ld;
5719 case M_LBU_AB:
5720 s = "lbu";
5721 goto ld;
5722 case M_LH_AB:

--- 32 unchanged lines hidden (view full) ---

5755 case M_LWR_AB:
5756 s = "lwr";
5757 lr = 1;
5758 goto ld;
5759 case M_LDC1_AB:
5760 if (mips_opts.arch == CPU_R4650)
5761 {
5762 as_bad (_("opcode not supported on this processor"));
5694
5695 case M_LB_AB:
5696 s = "lb";
5697 goto ld;
5698 case M_LBU_AB:
5699 s = "lbu";
5700 goto ld;
5701 case M_LH_AB:

--- 32 unchanged lines hidden (view full) ---

5734 case M_LWR_AB:
5735 s = "lwr";
5736 lr = 1;
5737 goto ld;
5738 case M_LDC1_AB:
5739 if (mips_opts.arch == CPU_R4650)
5740 {
5741 as_bad (_("opcode not supported on this processor"));
5763 return;
5742 break;
5764 }
5765 s = "ldc1";
5766 /* Itbl support may require additional care here. */
5767 coproc = 1;
5768 goto ld;
5769 case M_LDC2_AB:
5770 s = "ldc2";
5771 /* Itbl support may require additional care here. */

--- 16 unchanged lines hidden (view full) ---

5788 s = "ll";
5789 goto ld;
5790 case M_LLD_AB:
5791 s = "lld";
5792 goto ld;
5793 case M_LWU_AB:
5794 s = "lwu";
5795 ld:
5743 }
5744 s = "ldc1";
5745 /* Itbl support may require additional care here. */
5746 coproc = 1;
5747 goto ld;
5748 case M_LDC2_AB:
5749 s = "ldc2";
5750 /* Itbl support may require additional care here. */

--- 16 unchanged lines hidden (view full) ---

5767 s = "ll";
5768 goto ld;
5769 case M_LLD_AB:
5770 s = "lld";
5771 goto ld;
5772 case M_LWU_AB:
5773 s = "lwu";
5774 ld:
5775 if (mips_opts.arch == CPU_OCTEON
5776 && octeon_error_on_unsupported
5777 && (mask == M_LDC1_AB || mask == M_LDC2_AB || mask == M_LDC3_AB
5778 || mask == M_L_DOB || mask == M_L_DAB
5779 || mask == M_LI_D || mask == M_LI_DD
5780 || mask == M_LI_S || mask == M_LI_SS))
5781 {
5782 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name);
5783 return;
5784 }
5796 if (breg == treg || coproc || lr)
5797 {
5798 tempreg = AT;
5799 used_at = 1;
5800 }
5801 else
5802 {
5803 tempreg = treg;
5785 if (breg == treg || coproc || lr)
5786 {
5787 tempreg = AT;
5788 used_at = 1;
5789 }
5790 else
5791 {
5792 tempreg = treg;
5804 used_at = 0;
5805 }
5806 goto ld_st;
5807 case M_SB_AB:
5808 s = "sb";
5809 goto st;
5810 case M_SH_AB:
5811 s = "sh";
5812 goto st;

--- 31 unchanged lines hidden (view full) ---

5844 goto st;
5845 case M_SCD_AB:
5846 s = "scd";
5847 goto st;
5848 case M_SDC1_AB:
5849 if (mips_opts.arch == CPU_R4650)
5850 {
5851 as_bad (_("opcode not supported on this processor"));
5793 }
5794 goto ld_st;
5795 case M_SB_AB:
5796 s = "sb";
5797 goto st;
5798 case M_SH_AB:
5799 s = "sh";
5800 goto st;

--- 31 unchanged lines hidden (view full) ---

5832 goto st;
5833 case M_SCD_AB:
5834 s = "scd";
5835 goto st;
5836 case M_SDC1_AB:
5837 if (mips_opts.arch == CPU_R4650)
5838 {
5839 as_bad (_("opcode not supported on this processor"));
5852 return;
5840 break;
5853 }
5854 s = "sdc1";
5855 coproc = 1;
5856 /* Itbl support may require additional care here. */
5857 goto st;
5858 case M_SDC2_AB:
5859 s = "sdc2";
5860 /* Itbl support may require additional care here. */

--- 5 unchanged lines hidden (view full) ---

5866 coproc = 1;
5867 goto st;
5868 case M_SDL_AB:
5869 s = "sdl";
5870 goto st;
5871 case M_SDR_AB:
5872 s = "sdr";
5873 st:
5841 }
5842 s = "sdc1";
5843 coproc = 1;
5844 /* Itbl support may require additional care here. */
5845 goto st;
5846 case M_SDC2_AB:
5847 s = "sdc2";
5848 /* Itbl support may require additional care here. */

--- 5 unchanged lines hidden (view full) ---

5854 coproc = 1;
5855 goto st;
5856 case M_SDL_AB:
5857 s = "sdl";
5858 goto st;
5859 case M_SDR_AB:
5860 s = "sdr";
5861 st:
5862 if (mips_opts.arch == CPU_OCTEON
5863 && octeon_error_on_unsupported
5864 && (mask == M_SWC0_AB || mask == M_SWC1_AB || mask == M_SWC2_AB
5865 || mask == M_SDC1_AB || mask == M_SDC2_AB || mask == M_SDC3_AB
5866 || mask == M_S_DAB || mask == M_S_DOB))
5867 {
5868 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name);
5869 return;
5870 }
5874 tempreg = AT;
5875 used_at = 1;
5876 ld_st:
5877 /* Itbl support may require additional care here. */
5878 if (mask == M_LWC1_AB
5879 || mask == M_SWC1_AB
5880 || mask == M_LDC1_AB
5881 || mask == M_SDC1_AB
5882 || mask == M_L_DAB
5883 || mask == M_S_DAB)
5884 fmt = "T,o(b)";
5885 else if (coproc)
5886 fmt = "E,o(b)";
5887 else
5888 fmt = "t,o(b)";
5889
5871 tempreg = AT;
5872 used_at = 1;
5873 ld_st:
5874 /* Itbl support may require additional care here. */
5875 if (mask == M_LWC1_AB
5876 || mask == M_SWC1_AB
5877 || mask == M_LDC1_AB
5878 || mask == M_SDC1_AB
5879 || mask == M_L_DAB
5880 || mask == M_S_DAB)
5881 fmt = "T,o(b)";
5882 else if (coproc)
5883 fmt = "E,o(b)";
5884 else
5885 fmt = "t,o(b)";
5886
5890 /* Sign-extending 32-bit constants makes their handling easier.
5891 The HAVE_64BIT_GPRS... part is due to the linux kernel hack
5892 described below. */
5893 if ((! HAVE_64BIT_ADDRESSES
5894 && (! HAVE_64BIT_GPRS && offset_expr.X_op == O_constant))
5895 && (offset_expr.X_op == O_constant)
5896 && ! ((offset_expr.X_add_number & ~((bfd_vma) 0x7fffffff))
5897 == ~((bfd_vma) 0x7fffffff)))
5898 {
5899 if (offset_expr.X_add_number & ~((bfd_vma) 0xffffffff))
5900 as_bad (_("constant too large"));
5901
5902 offset_expr.X_add_number = (((offset_expr.X_add_number & 0xffffffff)
5903 ^ 0x80000000) - 0x80000000);
5904 }
5905
5906 /* For embedded PIC, we allow loads where the offset is calculated
5907 by subtracting a symbol in the current segment from an unknown
5908 symbol, relative to a base register, e.g.:
5909 <op> $treg, <sym>-<localsym>($breg)
5910 This is used by the compiler for switch statements. */
5911 if (mips_pic == EMBEDDED_PIC
5912 && offset_expr.X_op == O_subtract
5913 && (symbol_constant_p (offset_expr.X_op_symbol)
5914 ? S_GET_SEGMENT (offset_expr.X_op_symbol) == now_seg
5915 : (symbol_equated_p (offset_expr.X_op_symbol)
5916 && (S_GET_SEGMENT
5917 (symbol_get_value_expression (offset_expr.X_op_symbol)
5918 ->X_add_symbol)
5919 == now_seg)))
5920 && breg != 0
5921 && (offset_expr.X_add_number == 0
5922 || OUTPUT_FLAVOR == bfd_target_elf_flavour))
5923 {
5924 /* For this case, we output the instructions:
5925 lui $tempreg,<sym> (BFD_RELOC_PCREL_HI16_S)
5926 addiu $tempreg,$tempreg,$breg
5927 <op> $treg,<sym>($tempreg) (BFD_RELOC_PCREL_LO16)
5928 If the relocation would fit entirely in 16 bits, it would be
5929 nice to emit:
5930 <op> $treg,<sym>($breg) (BFD_RELOC_PCREL_LO16)
5931 instead, but that seems quite difficult. */
5932 macro_build (&offset_expr, "lui", "t,u", tempreg,
5933 BFD_RELOC_PCREL_HI16_S);
5934 macro_build (NULL,
5935 ((bfd_arch_bits_per_address (stdoutput) == 32
5936 || ! ISA_HAS_64BIT_REGS (mips_opts.isa))
5937 ? "addu" : "daddu"),
5938 "d,v,t", tempreg, tempreg, breg);
5939 macro_build (&offset_expr, s, fmt, treg,
5940 BFD_RELOC_PCREL_LO16, tempreg);
5941 if (! used_at)
5942 return;
5943 break;
5944 }
5945
5946 if (offset_expr.X_op != O_constant
5947 && offset_expr.X_op != O_symbol)
5948 {
5949 as_bad (_("expression too complex"));
5950 offset_expr.X_op = O_constant;
5951 }
5952
5887 if (offset_expr.X_op != O_constant
5888 && offset_expr.X_op != O_symbol)
5889 {
5890 as_bad (_("expression too complex"));
5891 offset_expr.X_op = O_constant;
5892 }
5893
5894 if (HAVE_32BIT_ADDRESSES
5895 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
5896 {
5897 char value [32];
5898
5899 sprintf_vma (value, offset_expr.X_add_number);
5900 as_bad (_("Number (0x%s) larger than 32 bits"), value);
5901 }
5902
5953 /* A constant expression in PIC code can be handled just as it
5954 is in non PIC code. */
5903 /* A constant expression in PIC code can be handled just as it
5904 is in non PIC code. */
5955 if (mips_pic == NO_PIC
5956 || offset_expr.X_op == O_constant)
5905 if (offset_expr.X_op == O_constant)
5957 {
5906 {
5907 expr1.X_add_number = ((offset_expr.X_add_number + 0x8000)
5908 & ~(bfd_vma) 0xffff);
5909 normalize_address_expr (&expr1);
5910 load_register (tempreg, &expr1, HAVE_64BIT_ADDRESSES);
5911 if (breg != 0)
5912 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5913 tempreg, tempreg, breg);
5914 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_LO16, tempreg);
5915 }
5916 else if (mips_pic == NO_PIC)
5917 {
5958 /* If this is a reference to a GP relative symbol, and there
5959 is no base register, we want
5960 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5961 Otherwise, if there is no base register, we want
5962 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5963 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5964 If we have a constant, we need two instructions anyhow,
5965 so we always use the latter form.

--- 37 unchanged lines hidden (view full) ---

6003 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
6004 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
6005 dsll $tempreg,16
6006 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
6007 dsll $tempreg,16
6008 daddu $tempreg,$tempreg,$breg
6009 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
6010
5918 /* If this is a reference to a GP relative symbol, and there
5919 is no base register, we want
5920 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
5921 Otherwise, if there is no base register, we want
5922 lui $tempreg,<sym> (BFD_RELOC_HI16_S)
5923 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5924 If we have a constant, we need two instructions anyhow,
5925 so we always use the latter form.

--- 37 unchanged lines hidden (view full) ---

5963 lui $tempreg,<sym> (BFD_RELOC_MIPS_HIGHEST)
5964 daddiu $tempreg,<sym> (BFD_RELOC_MIPS_HIGHER)
5965 dsll $tempreg,16
5966 daddiu $tempreg,<sym> (BFD_RELOC_HI16_S)
5967 dsll $tempreg,16
5968 daddu $tempreg,$tempreg,$breg
5969 <op> $treg,<sym>($tempreg) (BFD_RELOC_LO16)
5970
6011 If we have 64-bit addresses, as an optimization, for
6012 addresses which are 32-bit constants (e.g. kseg0/kseg1
6013 addresses) we fall back to the 32-bit address generation
6014 mechanism since it is more efficient. Note that due to
6015 the signed offset used by memory operations, the 32-bit
6016 range is shifted down by 32768 here. This code should
6017 probably attempt to generate 64-bit constants more
6018 efficiently in general.
6019
6020 As an extension for architectures with 64-bit registers,
6021 we don't truncate 64-bit addresses given as literal
6022 constants down to 32 bits, to support existing practice
6023 in the mips64 Linux (the kernel), that compiles source
6024 files with -mabi=64, assembling them as o32 or n32 (with
6025 -Wa,-32 or -Wa,-n32). This is not beautiful, but since
6026 the whole kernel is loaded into a memory region that is
6027 addressable with sign-extended 32-bit addresses, it is
6028 wasteful to compute the upper 32 bits of every
6029 non-literal address, that takes more space and time.
6030 Some day this should probably be implemented as an
6031 assembler option, such that the kernel doesn't have to
6032 use such ugly hacks, even though it will still have to
6033 end up converting the binary to ELF32 for a number of
6034 platforms whose boot loaders don't support ELF64
6035 binaries. */
6036 if ((HAVE_64BIT_ADDRESSES
6037 && ! (offset_expr.X_op == O_constant
6038 && IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
6039 || (HAVE_64BIT_GPRS
6040 && offset_expr.X_op == O_constant
6041 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000)))
5971 For GP relative symbols in 64bit address space we can use
5972 the same sequence as in 32bit address space. */
5973 if (HAVE_64BIT_SYMBOLS)
6042 {
5974 {
6043 /* ??? We don't provide a GP-relative alternative for
6044 these macros. It used not to be possible with the
6045 original relaxation code, but it could be done now. */
5975 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
5976 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
5977 {
5978 relax_start (offset_expr.X_add_symbol);
5979 if (breg == 0)
5980 {
5981 macro_build (&offset_expr, s, fmt, treg,
5982 BFD_RELOC_GPREL16, mips_gp_register);
5983 }
5984 else
5985 {
5986 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
5987 tempreg, breg, mips_gp_register);
5988 macro_build (&offset_expr, s, fmt, treg,
5989 BFD_RELOC_GPREL16, tempreg);
5990 }
5991 relax_switch ();
5992 }
6046
5993
6047 if (used_at == 0 && ! mips_opts.noat)
5994 if (used_at == 0 && !mips_opts.noat)
6048 {
6049 macro_build (&offset_expr, "lui", "t,u", tempreg,
6050 BFD_RELOC_MIPS_HIGHEST);
6051 macro_build (&offset_expr, "lui", "t,u", AT,
6052 BFD_RELOC_HI16_S);
6053 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6054 tempreg, BFD_RELOC_MIPS_HIGHER);
6055 if (breg != 0)

--- 16 unchanged lines hidden (view full) ---

6072 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6073 if (breg != 0)
6074 macro_build (NULL, "daddu", "d,v,t",
6075 tempreg, tempreg, breg);
6076 macro_build (&offset_expr, s, fmt, treg,
6077 BFD_RELOC_LO16, tempreg);
6078 }
6079
5995 {
5996 macro_build (&offset_expr, "lui", "t,u", tempreg,
5997 BFD_RELOC_MIPS_HIGHEST);
5998 macro_build (&offset_expr, "lui", "t,u", AT,
5999 BFD_RELOC_HI16_S);
6000 macro_build (&offset_expr, "daddiu", "t,r,j", tempreg,
6001 tempreg, BFD_RELOC_MIPS_HIGHER);
6002 if (breg != 0)

--- 16 unchanged lines hidden (view full) ---

6019 macro_build (NULL, "dsll", "d,w,<", tempreg, tempreg, 16);
6020 if (breg != 0)
6021 macro_build (NULL, "daddu", "d,v,t",
6022 tempreg, tempreg, breg);
6023 macro_build (&offset_expr, s, fmt, treg,
6024 BFD_RELOC_LO16, tempreg);
6025 }
6026
6080 return;
6027 if (mips_relax.sequence)
6028 relax_end ();
6029 break;
6081 }
6082
6030 }
6031
6083 if (offset_expr.X_op == O_constant
6084 && ! IS_SEXT_32BIT_NUM (offset_expr.X_add_number + 0x8000))
6085 as_bad (_("load/store address overflow (max 32 bits)"));
6086
6087 if (breg == 0)
6088 {
6089 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6032 if (breg == 0)
6033 {
6034 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6090 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6035 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6091 {
6092 relax_start (offset_expr.X_add_symbol);
6093 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6094 mips_gp_register);
6095 relax_switch ();
6036 {
6037 relax_start (offset_expr.X_add_symbol);
6038 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6039 mips_gp_register);
6040 relax_switch ();
6096 used_at = 0;
6097 }
6098 macro_build_lui (&offset_expr, tempreg);
6099 macro_build (&offset_expr, s, fmt, treg,
6100 BFD_RELOC_LO16, tempreg);
6101 if (mips_relax.sequence)
6102 relax_end ();
6103 }
6104 else
6105 {
6106 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6041 }
6042 macro_build_lui (&offset_expr, tempreg);
6043 macro_build (&offset_expr, s, fmt, treg,
6044 BFD_RELOC_LO16, tempreg);
6045 if (mips_relax.sequence)
6046 relax_end ();
6047 }
6048 else
6049 {
6050 if ((valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6107 && ! nopic_need_relax (offset_expr.X_add_symbol, 1))
6051 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6108 {
6109 relax_start (offset_expr.X_add_symbol);
6110 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6111 tempreg, breg, mips_gp_register);
6112 macro_build (&offset_expr, s, fmt, treg,
6113 BFD_RELOC_GPREL16, tempreg);
6114 relax_switch ();
6115 }
6116 macro_build_lui (&offset_expr, tempreg);
6117 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6118 tempreg, tempreg, breg);
6119 macro_build (&offset_expr, s, fmt, treg,
6120 BFD_RELOC_LO16, tempreg);
6121 if (mips_relax.sequence)
6122 relax_end ();
6123 }
6124 }
6052 {
6053 relax_start (offset_expr.X_add_symbol);
6054 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6055 tempreg, breg, mips_gp_register);
6056 macro_build (&offset_expr, s, fmt, treg,
6057 BFD_RELOC_GPREL16, tempreg);
6058 relax_switch ();
6059 }
6060 macro_build_lui (&offset_expr, tempreg);
6061 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6062 tempreg, tempreg, breg);
6063 macro_build (&offset_expr, s, fmt, treg,
6064 BFD_RELOC_LO16, tempreg);
6065 if (mips_relax.sequence)
6066 relax_end ();
6067 }
6068 }
6125 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6069 else if (!mips_big_got)
6126 {
6127 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6128
6129 /* If this is a reference to an external symbol, we want
6130 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6131 nop
6132 <op> $treg,0($tempreg)
6133 Otherwise we want

--- 17 unchanged lines hidden (view full) ---

6151 {
6152 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6153 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6154 if (breg != 0)
6155 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6156 tempreg, tempreg, breg);
6157 macro_build (&offset_expr, s, fmt, treg,
6158 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6070 {
6071 int lw_reloc_type = (int) BFD_RELOC_MIPS_GOT16;
6072
6073 /* If this is a reference to an external symbol, we want
6074 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6075 nop
6076 <op> $treg,0($tempreg)
6077 Otherwise we want

--- 17 unchanged lines hidden (view full) ---

6095 {
6096 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6097 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6098 if (breg != 0)
6099 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6100 tempreg, tempreg, breg);
6101 macro_build (&offset_expr, s, fmt, treg,
6102 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6159
6160 if (! used_at)
6161 return;
6162
6163 break;
6164 }
6165 expr1.X_add_number = offset_expr.X_add_number;
6166 offset_expr.X_add_number = 0;
6167 if (expr1.X_add_number < -0x8000
6168 || expr1.X_add_number >= 0x8000)
6169 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6170 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6171 lw_reloc_type, mips_gp_register);
6103 break;
6104 }
6105 expr1.X_add_number = offset_expr.X_add_number;
6106 offset_expr.X_add_number = 0;
6107 if (expr1.X_add_number < -0x8000
6108 || expr1.X_add_number >= 0x8000)
6109 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6110 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6111 lw_reloc_type, mips_gp_register);
6172 macro_build (NULL, "nop", "");
6112 load_delay_nop ();
6173 relax_start (offset_expr.X_add_symbol);
6174 relax_switch ();
6175 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6176 tempreg, BFD_RELOC_LO16);
6177 relax_end ();
6178 if (breg != 0)
6179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6180 tempreg, tempreg, breg);
6181 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6182 }
6113 relax_start (offset_expr.X_add_symbol);
6114 relax_switch ();
6115 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6116 tempreg, BFD_RELOC_LO16);
6117 relax_end ();
6118 if (breg != 0)
6119 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6120 tempreg, tempreg, breg);
6121 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6122 }
6183 else if (mips_pic == SVR4_PIC && ! HAVE_NEWABI)
6123 else if (mips_big_got && !HAVE_NEWABI)
6184 {
6185 int gpdelay;
6186
6187 /* If this is a reference to an external symbol, we want
6188 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6189 addu $tempreg,$tempreg,$gp
6190 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6191 <op> $treg,0($tempreg)

--- 22 unchanged lines hidden (view full) ---

6214 mips_gp_register);
6215 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6216 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6217 relax_switch ();
6218 if (gpdelay)
6219 macro_build (NULL, "nop", "");
6220 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6221 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6124 {
6125 int gpdelay;
6126
6127 /* If this is a reference to an external symbol, we want
6128 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6129 addu $tempreg,$tempreg,$gp
6130 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6131 <op> $treg,0($tempreg)

--- 22 unchanged lines hidden (view full) ---

6154 mips_gp_register);
6155 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6156 BFD_RELOC_MIPS_GOT_LO16, tempreg);
6157 relax_switch ();
6158 if (gpdelay)
6159 macro_build (NULL, "nop", "");
6160 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", tempreg,
6161 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6222 macro_build (NULL, "nop", "");
6162 load_delay_nop ();
6223 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6224 tempreg, BFD_RELOC_LO16);
6225 relax_end ();
6226
6227 if (breg != 0)
6228 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6229 tempreg, tempreg, breg);
6230 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6231 }
6163 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", tempreg,
6164 tempreg, BFD_RELOC_LO16);
6165 relax_end ();
6166
6167 if (breg != 0)
6168 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6169 tempreg, tempreg, breg);
6170 macro_build (&expr1, s, fmt, treg, BFD_RELOC_LO16, tempreg);
6171 }
6232 else if (mips_pic == SVR4_PIC && HAVE_NEWABI)
6172 else if (mips_big_got && HAVE_NEWABI)
6233 {
6234 /* If this is a reference to an external symbol, we want
6235 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6236 add $tempreg,$tempreg,$gp
6237 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6238 <op> $treg,<ofst>($tempreg)
6239 Otherwise, for local symbols, we want:
6240 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)

--- 22 unchanged lines hidden (view full) ---

6263 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6264 if (breg != 0)
6265 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6266 tempreg, tempreg, breg);
6267 macro_build (&offset_expr, s, fmt, treg,
6268 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6269 relax_end ();
6270 }
6173 {
6174 /* If this is a reference to an external symbol, we want
6175 lui $tempreg,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6176 add $tempreg,$tempreg,$gp
6177 lw $tempreg,<sym>($tempreg) (BFD_RELOC_MIPS_GOT_LO16)
6178 <op> $treg,<ofst>($tempreg)
6179 Otherwise, for local symbols, we want:
6180 lw $tempreg,<sym>($gp) (BFD_RELOC_MIPS_GOT_PAGE)

--- 22 unchanged lines hidden (view full) ---

6203 BFD_RELOC_MIPS_GOT_PAGE, mips_gp_register);
6204 if (breg != 0)
6205 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6206 tempreg, tempreg, breg);
6207 macro_build (&offset_expr, s, fmt, treg,
6208 BFD_RELOC_MIPS_GOT_OFST, tempreg);
6209 relax_end ();
6210 }
6271 else if (mips_pic == EMBEDDED_PIC)
6272 {
6273 /* If there is no base register, we want
6274 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6275 If there is a base register, we want
6276 addu $tempreg,$breg,$gp
6277 <op> $treg,<sym>($tempreg) (BFD_RELOC_GPREL16)
6278 */
6279 assert (offset_expr.X_op == O_symbol);
6280 if (breg == 0)
6281 {
6282 macro_build (&offset_expr, s, fmt, treg, BFD_RELOC_GPREL16,
6283 mips_gp_register);
6284 used_at = 0;
6285 }
6286 else
6287 {
6288 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6289 tempreg, breg, mips_gp_register);
6290 macro_build (&offset_expr, s, fmt, treg,
6291 BFD_RELOC_GPREL16, tempreg);
6292 }
6293 }
6294 else
6295 abort ();
6296
6211 else
6212 abort ();
6213
6297 if (! used_at)
6298 return;
6299
6300 break;
6301
6302 case M_LI:
6303 case M_LI_S:
6304 load_register (treg, &imm_expr, 0);
6214 break;
6215
6216 case M_LI:
6217 case M_LI_S:
6218 load_register (treg, &imm_expr, 0);
6305 return;
6219 break;
6306
6307 case M_DLI:
6308 load_register (treg, &imm_expr, 1);
6220
6221 case M_DLI:
6222 load_register (treg, &imm_expr, 1);
6309 return;
6223 break;
6310
6311 case M_LI_SS:
6312 if (imm_expr.X_op == O_constant)
6313 {
6224
6225 case M_LI_SS:
6226 if (imm_expr.X_op == O_constant)
6227 {
6228 used_at = 1;
6314 load_register (AT, &imm_expr, 0);
6315 macro_build (NULL, "mtc1", "t,G", AT, treg);
6316 break;
6317 }
6318 else
6319 {
6320 assert (offset_expr.X_op == O_symbol
6321 && strcmp (segment_name (S_GET_SEGMENT
6322 (offset_expr.X_add_symbol)),
6323 ".lit4") == 0
6324 && offset_expr.X_add_number == 0);
6325 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6326 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6229 load_register (AT, &imm_expr, 0);
6230 macro_build (NULL, "mtc1", "t,G", AT, treg);
6231 break;
6232 }
6233 else
6234 {
6235 assert (offset_expr.X_op == O_symbol
6236 && strcmp (segment_name (S_GET_SEGMENT
6237 (offset_expr.X_add_symbol)),
6238 ".lit4") == 0
6239 && offset_expr.X_add_number == 0);
6240 macro_build (&offset_expr, "lwc1", "T,o(b)", treg,
6241 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6327 return;
6242 break;
6328 }
6329
6330 case M_LI_D:
6331 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6332 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6333 order 32 bits of the value and the low order 32 bits are either
6334 zero or in OFFSET_EXPR. */
6335 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)

--- 23 unchanged lines hidden (view full) ---

6359 move_register (lreg, 0);
6360 else
6361 {
6362 assert (offset_expr.X_op == O_constant);
6363 load_register (lreg, &offset_expr, 0);
6364 }
6365 }
6366 }
6243 }
6244
6245 case M_LI_D:
6246 /* Check if we have a constant in IMM_EXPR. If the GPRs are 64 bits
6247 wide, IMM_EXPR is the entire value. Otherwise IMM_EXPR is the high
6248 order 32 bits of the value and the low order 32 bits are either
6249 zero or in OFFSET_EXPR. */
6250 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)

--- 23 unchanged lines hidden (view full) ---

6274 move_register (lreg, 0);
6275 else
6276 {
6277 assert (offset_expr.X_op == O_constant);
6278 load_register (lreg, &offset_expr, 0);
6279 }
6280 }
6281 }
6367 return;
6282 break;
6368 }
6369
6370 /* We know that sym is in the .rdata section. First we get the
6371 upper 16 bits of the address. */
6372 if (mips_pic == NO_PIC)
6373 {
6374 macro_build_lui (&offset_expr, AT);
6283 }
6284
6285 /* We know that sym is in the .rdata section. First we get the
6286 upper 16 bits of the address. */
6287 if (mips_pic == NO_PIC)
6288 {
6289 macro_build_lui (&offset_expr, AT);
6290 used_at = 1;
6375 }
6291 }
6376 else if (mips_pic == SVR4_PIC)
6292 else
6377 {
6378 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6379 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6293 {
6294 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6295 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6296 used_at = 1;
6380 }
6297 }
6381 else if (mips_pic == EMBEDDED_PIC)
6382 {
6383 /* For embedded PIC we pick up the entire address off $gp in
6384 a single instruction. */
6385 macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j", AT,
6386 mips_gp_register, BFD_RELOC_GPREL16);
6387 offset_expr.X_op = O_constant;
6388 offset_expr.X_add_number = 0;
6389 }
6390 else
6391 abort ();
6392
6393 /* Now we load the register(s). */
6394 if (HAVE_64BIT_GPRS)
6298
6299 /* Now we load the register(s). */
6300 if (HAVE_64BIT_GPRS)
6395 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6301 {
6302 used_at = 1;
6303 macro_build (&offset_expr, "ld", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6304 }
6396 else
6397 {
6305 else
6306 {
6307 used_at = 1;
6398 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6399 if (treg != RA)
6400 {
6401 /* FIXME: How in the world do we deal with the possible
6402 overflow here? */
6403 offset_expr.X_add_number += 4;
6404 macro_build (&offset_expr, "lw", "t,o(b)",
6405 treg + 1, BFD_RELOC_LO16, AT);

--- 4 unchanged lines hidden (view full) ---

6410 case M_LI_DD:
6411 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6412 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6413 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6414 the value and the low order 32 bits are either zero or in
6415 OFFSET_EXPR. */
6416 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6417 {
6308 macro_build (&offset_expr, "lw", "t,o(b)", treg, BFD_RELOC_LO16, AT);
6309 if (treg != RA)
6310 {
6311 /* FIXME: How in the world do we deal with the possible
6312 overflow here? */
6313 offset_expr.X_add_number += 4;
6314 macro_build (&offset_expr, "lw", "t,o(b)",
6315 treg + 1, BFD_RELOC_LO16, AT);

--- 4 unchanged lines hidden (view full) ---

6320 case M_LI_DD:
6321 /* Check if we have a constant in IMM_EXPR. If the FPRs are 64 bits
6322 wide, IMM_EXPR is the entire value and the GPRs are known to be 64
6323 bits wide as well. Otherwise IMM_EXPR is the high order 32 bits of
6324 the value and the low order 32 bits are either zero or in
6325 OFFSET_EXPR. */
6326 if (imm_expr.X_op == O_constant || imm_expr.X_op == O_big)
6327 {
6328 used_at = 1;
6418 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6419 if (HAVE_64BIT_FPRS)
6420 {
6421 assert (HAVE_64BIT_GPRS);
6422 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6423 }
6424 else
6425 {

--- 14 unchanged lines hidden (view full) ---

6440 && offset_expr.X_add_number == 0);
6441 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6442 if (strcmp (s, ".lit8") == 0)
6443 {
6444 if (mips_opts.isa != ISA_MIPS1)
6445 {
6446 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6447 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6329 load_register (AT, &imm_expr, HAVE_64BIT_FPRS);
6330 if (HAVE_64BIT_FPRS)
6331 {
6332 assert (HAVE_64BIT_GPRS);
6333 macro_build (NULL, "dmtc1", "t,S", AT, treg);
6334 }
6335 else
6336 {

--- 14 unchanged lines hidden (view full) ---

6351 && offset_expr.X_add_number == 0);
6352 s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol));
6353 if (strcmp (s, ".lit8") == 0)
6354 {
6355 if (mips_opts.isa != ISA_MIPS1)
6356 {
6357 macro_build (&offset_expr, "ldc1", "T,o(b)", treg,
6358 BFD_RELOC_MIPS_LITERAL, mips_gp_register);
6448 return;
6359 break;
6449 }
6450 breg = mips_gp_register;
6451 r = BFD_RELOC_MIPS_LITERAL;
6452 goto dob;
6453 }
6454 else
6455 {
6456 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6360 }
6361 breg = mips_gp_register;
6362 r = BFD_RELOC_MIPS_LITERAL;
6363 goto dob;
6364 }
6365 else
6366 {
6367 assert (strcmp (s, RDATA_SECTION_NAME) == 0);
6457 if (mips_pic == SVR4_PIC)
6368 used_at = 1;
6369 if (mips_pic != NO_PIC)
6458 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6459 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6460 else
6461 {
6462 /* FIXME: This won't work for a 64 bit address. */
6463 macro_build_lui (&offset_expr, AT);
6464 }
6465

--- 7 unchanged lines hidden (view full) ---

6473 r = BFD_RELOC_LO16;
6474 goto dob;
6475 }
6476
6477 case M_L_DOB:
6478 if (mips_opts.arch == CPU_R4650)
6479 {
6480 as_bad (_("opcode not supported on this processor"));
6370 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6371 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6372 else
6373 {
6374 /* FIXME: This won't work for a 64 bit address. */
6375 macro_build_lui (&offset_expr, AT);
6376 }
6377

--- 7 unchanged lines hidden (view full) ---

6385 r = BFD_RELOC_LO16;
6386 goto dob;
6387 }
6388
6389 case M_L_DOB:
6390 if (mips_opts.arch == CPU_R4650)
6391 {
6392 as_bad (_("opcode not supported on this processor"));
6481 return;
6393 break;
6482 }
6483 /* Even on a big endian machine $fn comes before $fn+1. We have
6484 to adjust when loading from memory. */
6485 r = BFD_RELOC_LO16;
6486 dob:
6487 assert (mips_opts.isa == ISA_MIPS1);
6488 macro_build (&offset_expr, "lwc1", "T,o(b)",
6489 target_big_endian ? treg + 1 : treg, r, breg);
6490 /* FIXME: A possible overflow which I don't know how to deal
6491 with. */
6492 offset_expr.X_add_number += 4;
6493 macro_build (&offset_expr, "lwc1", "T,o(b)",
6494 target_big_endian ? treg : treg + 1, r, breg);
6394 }
6395 /* Even on a big endian machine $fn comes before $fn+1. We have
6396 to adjust when loading from memory. */
6397 r = BFD_RELOC_LO16;
6398 dob:
6399 assert (mips_opts.isa == ISA_MIPS1);
6400 macro_build (&offset_expr, "lwc1", "T,o(b)",
6401 target_big_endian ? treg + 1 : treg, r, breg);
6402 /* FIXME: A possible overflow which I don't know how to deal
6403 with. */
6404 offset_expr.X_add_number += 4;
6405 macro_build (&offset_expr, "lwc1", "T,o(b)",
6406 target_big_endian ? treg : treg + 1, r, breg);
6495
6496 if (breg != AT)
6497 return;
6498 break;
6499
6500 case M_L_DAB:
6501 /*
6502 * The MIPS assembler seems to check for X_add_number not
6503 * being double aligned and generating:
6504 * lui at,%hi(foo+1)
6505 * addu at,at,v1
6506 * addiu at,at,%lo(foo+1)
6507 * lwc1 f2,0(at)
6508 * lwc1 f3,4(at)
6509 * But, the resulting address is the same after relocation so why
6510 * generate the extra instruction?
6511 */
6512 if (mips_opts.arch == CPU_R4650)
6513 {
6514 as_bad (_("opcode not supported on this processor"));
6407 break;
6408
6409 case M_L_DAB:
6410 /*
6411 * The MIPS assembler seems to check for X_add_number not
6412 * being double aligned and generating:
6413 * lui at,%hi(foo+1)
6414 * addu at,at,v1
6415 * addiu at,at,%lo(foo+1)
6416 * lwc1 f2,0(at)
6417 * lwc1 f3,4(at)
6418 * But, the resulting address is the same after relocation so why
6419 * generate the extra instruction?
6420 */
6421 if (mips_opts.arch == CPU_R4650)
6422 {
6423 as_bad (_("opcode not supported on this processor"));
6515 return;
6424 break;
6516 }
6517 /* Itbl support may require additional care here. */
6518 coproc = 1;
6519 if (mips_opts.isa != ISA_MIPS1)
6520 {
6521 s = "ldc1";
6522 goto ld;
6523 }
6524
6525 s = "lwc1";
6526 fmt = "T,o(b)";
6527 goto ldd_std;
6528
6529 case M_S_DAB:
6530 if (mips_opts.arch == CPU_R4650)
6531 {
6532 as_bad (_("opcode not supported on this processor"));
6425 }
6426 /* Itbl support may require additional care here. */
6427 coproc = 1;
6428 if (mips_opts.isa != ISA_MIPS1)
6429 {
6430 s = "ldc1";
6431 goto ld;
6432 }
6433
6434 s = "lwc1";
6435 fmt = "T,o(b)";
6436 goto ldd_std;
6437
6438 case M_S_DAB:
6439 if (mips_opts.arch == CPU_R4650)
6440 {
6441 as_bad (_("opcode not supported on this processor"));
6533 return;
6442 break;
6534 }
6535
6536 if (mips_opts.isa != ISA_MIPS1)
6537 {
6538 s = "sdc1";
6539 goto st;
6540 }
6541

--- 20 unchanged lines hidden (view full) ---

6562 s = "sd";
6563 goto st;
6564 }
6565
6566 s = "sw";
6567 fmt = "t,o(b)";
6568
6569 ldd_std:
6443 }
6444
6445 if (mips_opts.isa != ISA_MIPS1)
6446 {
6447 s = "sdc1";
6448 goto st;
6449 }
6450

--- 20 unchanged lines hidden (view full) ---

6471 s = "sd";
6472 goto st;
6473 }
6474
6475 s = "sw";
6476 fmt = "t,o(b)";
6477
6478 ldd_std:
6570 /* We do _not_ bother to allow embedded PIC (symbol-local_symbol)
6571 loads for the case of doing a pair of loads to simulate an 'ld'.
6572 This is not currently done by the compiler, and assembly coders
6573 writing embedded-pic code can cope. */
6574
6575 if (offset_expr.X_op != O_symbol
6576 && offset_expr.X_op != O_constant)
6577 {
6578 as_bad (_("expression too complex"));
6579 offset_expr.X_op = O_constant;
6580 }
6581
6479 if (offset_expr.X_op != O_symbol
6480 && offset_expr.X_op != O_constant)
6481 {
6482 as_bad (_("expression too complex"));
6483 offset_expr.X_op = O_constant;
6484 }
6485
6486 if (HAVE_32BIT_ADDRESSES
6487 && !IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
6488 {
6489 char value [32];
6490
6491 sprintf_vma (value, offset_expr.X_add_number);
6492 as_bad (_("Number (0x%s) larger than 32 bits"), value);
6493 }
6494
6582 /* Even on a big endian machine $fn comes before $fn+1. We have
6583 to adjust when loading from memory. We set coproc if we must
6584 load $fn+1 first. */
6585 /* Itbl support may require additional care here. */
6586 if (! target_big_endian)
6587 coproc = 0;
6588
6589 if (mips_pic == NO_PIC

--- 8 unchanged lines hidden (view full) ---

6598 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6599 If this is not a GP relative symbol, we want
6600 lui $at,<sym> (BFD_RELOC_HI16_S)
6601 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6602 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6603 If there is a base register, we add it to $at after the
6604 lui instruction. If there is a constant, we always use
6605 the last case. */
6495 /* Even on a big endian machine $fn comes before $fn+1. We have
6496 to adjust when loading from memory. We set coproc if we must
6497 load $fn+1 first. */
6498 /* Itbl support may require additional care here. */
6499 if (! target_big_endian)
6500 coproc = 0;
6501
6502 if (mips_pic == NO_PIC

--- 8 unchanged lines hidden (view full) ---

6511 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6512 If this is not a GP relative symbol, we want
6513 lui $at,<sym> (BFD_RELOC_HI16_S)
6514 <op> $treg,<sym>($at) (BFD_RELOC_LO16)
6515 <op> $treg+1,<sym>+4($at) (BFD_RELOC_LO16)
6516 If there is a base register, we add it to $at after the
6517 lui instruction. If there is a constant, we always use
6518 the last case. */
6606 if ((valueT) offset_expr.X_add_number > MAX_GPREL_OFFSET
6607 || nopic_need_relax (offset_expr.X_add_symbol, 1))
6608 used_at = 1;
6609 else
6519 if (offset_expr.X_op == O_symbol
6520 && (valueT) offset_expr.X_add_number <= MAX_GPREL_OFFSET
6521 && !nopic_need_relax (offset_expr.X_add_symbol, 1))
6610 {
6611 relax_start (offset_expr.X_add_symbol);
6612 if (breg == 0)
6613 {
6614 tempreg = mips_gp_register;
6522 {
6523 relax_start (offset_expr.X_add_symbol);
6524 if (breg == 0)
6525 {
6526 tempreg = mips_gp_register;
6615 used_at = 0;
6616 }
6617 else
6618 {
6619 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6620 AT, breg, mips_gp_register);
6621 tempreg = AT;
6622 used_at = 1;
6623 }

--- 30 unchanged lines hidden (view full) ---

6654 if (offset_expr.X_op == O_constant)
6655 offset_expr.X_add_number -= 8;
6656 else
6657 {
6658 offset_expr.X_add_number = -4;
6659 offset_expr.X_op = O_constant;
6660 }
6661 }
6527 }
6528 else
6529 {
6530 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6531 AT, breg, mips_gp_register);
6532 tempreg = AT;
6533 used_at = 1;
6534 }

--- 30 unchanged lines hidden (view full) ---

6565 if (offset_expr.X_op == O_constant)
6566 offset_expr.X_add_number -= 8;
6567 else
6568 {
6569 offset_expr.X_add_number = -4;
6570 offset_expr.X_op = O_constant;
6571 }
6572 }
6573 used_at = 1;
6662 macro_build_lui (&offset_expr, AT);
6663 if (breg != 0)
6664 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6665 /* Itbl support may require additional care here. */
6666 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6667 BFD_RELOC_LO16, AT);
6668 /* FIXME: How do we handle overflow here? */
6669 offset_expr.X_add_number += 4;
6670 /* Itbl support may require additional care here. */
6671 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6672 BFD_RELOC_LO16, AT);
6673 if (mips_relax.sequence)
6674 relax_end ();
6675 }
6574 macro_build_lui (&offset_expr, AT);
6575 if (breg != 0)
6576 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6577 /* Itbl support may require additional care here. */
6578 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6579 BFD_RELOC_LO16, AT);
6580 /* FIXME: How do we handle overflow here? */
6581 offset_expr.X_add_number += 4;
6582 /* Itbl support may require additional care here. */
6583 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6584 BFD_RELOC_LO16, AT);
6585 if (mips_relax.sequence)
6586 relax_end ();
6587 }
6676 else if (mips_pic == SVR4_PIC && ! mips_big_got)
6588 else if (!mips_big_got)
6677 {
6678 /* If this is a reference to an external symbol, we want
6679 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6680 nop
6681 <op> $treg,0($at)
6682 <op> $treg+1,4($at)
6683 Otherwise we want
6684 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)

--- 4 unchanged lines hidden (view full) ---

6689 lwc1 instructions. If there is a constant we include it
6690 in the lwc1 instructions. */
6691 used_at = 1;
6692 expr1.X_add_number = offset_expr.X_add_number;
6693 if (expr1.X_add_number < -0x8000
6694 || expr1.X_add_number >= 0x8000 - 4)
6695 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6696 load_got_offset (AT, &offset_expr);
6589 {
6590 /* If this is a reference to an external symbol, we want
6591 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)
6592 nop
6593 <op> $treg,0($at)
6594 <op> $treg+1,4($at)
6595 Otherwise we want
6596 lw $at,<sym>($gp) (BFD_RELOC_MIPS_GOT16)

--- 4 unchanged lines hidden (view full) ---

6601 lwc1 instructions. If there is a constant we include it
6602 in the lwc1 instructions. */
6603 used_at = 1;
6604 expr1.X_add_number = offset_expr.X_add_number;
6605 if (expr1.X_add_number < -0x8000
6606 || expr1.X_add_number >= 0x8000 - 4)
6607 as_bad (_("PIC code offset overflow (max 16 signed bits)"));
6608 load_got_offset (AT, &offset_expr);
6697 macro_build (NULL, "nop", "");
6609 load_delay_nop ();
6698 if (breg != 0)
6699 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6700
6701 /* Set mips_optimize to 2 to avoid inserting an undesired
6702 nop. */
6703 hold_mips_optimize = mips_optimize;
6704 mips_optimize = 2;
6705

--- 9 unchanged lines hidden (view full) ---

6715 BFD_RELOC_LO16, AT);
6716 offset_expr.X_add_number += 4;
6717 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6718 BFD_RELOC_LO16, AT);
6719 relax_end ();
6720
6721 mips_optimize = hold_mips_optimize;
6722 }
6610 if (breg != 0)
6611 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6612
6613 /* Set mips_optimize to 2 to avoid inserting an undesired
6614 nop. */
6615 hold_mips_optimize = mips_optimize;
6616 mips_optimize = 2;
6617

--- 9 unchanged lines hidden (view full) ---

6627 BFD_RELOC_LO16, AT);
6628 offset_expr.X_add_number += 4;
6629 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6630 BFD_RELOC_LO16, AT);
6631 relax_end ();
6632
6633 mips_optimize = hold_mips_optimize;
6634 }
6723 else if (mips_pic == SVR4_PIC)
6635 else if (mips_big_got)
6724 {
6725 int gpdelay;
6726
6727 /* If this is a reference to an external symbol, we want
6728 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6729 addu $at,$at,$gp
6730 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6731 nop

--- 16 unchanged lines hidden (view full) ---

6748 gpdelay = reg_needs_delay (mips_gp_register);
6749 relax_start (offset_expr.X_add_symbol);
6750 macro_build (&offset_expr, "lui", "t,u",
6751 AT, BFD_RELOC_MIPS_GOT_HI16);
6752 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6753 AT, AT, mips_gp_register);
6754 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6755 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6636 {
6637 int gpdelay;
6638
6639 /* If this is a reference to an external symbol, we want
6640 lui $at,<sym> (BFD_RELOC_MIPS_GOT_HI16)
6641 addu $at,$at,$gp
6642 lw $at,<sym>($at) (BFD_RELOC_MIPS_GOT_LO16)
6643 nop

--- 16 unchanged lines hidden (view full) ---

6660 gpdelay = reg_needs_delay (mips_gp_register);
6661 relax_start (offset_expr.X_add_symbol);
6662 macro_build (&offset_expr, "lui", "t,u",
6663 AT, BFD_RELOC_MIPS_GOT_HI16);
6664 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6665 AT, AT, mips_gp_register);
6666 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)",
6667 AT, BFD_RELOC_MIPS_GOT_LO16, AT);
6756 macro_build (NULL, "nop", "");
6668 load_delay_nop ();
6757 if (breg != 0)
6758 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6759 /* Itbl support may require additional care here. */
6760 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6761 BFD_RELOC_LO16, AT);
6762 expr1.X_add_number += 4;
6763
6764 /* Set mips_optimize to 2 to avoid inserting an undesired

--- 7 unchanged lines hidden (view full) ---

6772 expr1.X_add_number -= 4;
6773
6774 relax_switch ();
6775 offset_expr.X_add_number = expr1.X_add_number;
6776 if (gpdelay)
6777 macro_build (NULL, "nop", "");
6778 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6779 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6669 if (breg != 0)
6670 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6671 /* Itbl support may require additional care here. */
6672 macro_build (&expr1, s, fmt, coproc ? treg + 1 : treg,
6673 BFD_RELOC_LO16, AT);
6674 expr1.X_add_number += 4;
6675
6676 /* Set mips_optimize to 2 to avoid inserting an undesired

--- 7 unchanged lines hidden (view full) ---

6684 expr1.X_add_number -= 4;
6685
6686 relax_switch ();
6687 offset_expr.X_add_number = expr1.X_add_number;
6688 if (gpdelay)
6689 macro_build (NULL, "nop", "");
6690 macro_build (&offset_expr, ADDRESS_LOAD_INSN, "t,o(b)", AT,
6691 BFD_RELOC_MIPS_GOT16, mips_gp_register);
6780 macro_build (NULL, "nop", "");
6692 load_delay_nop ();
6781 if (breg != 0)
6782 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6783 /* Itbl support may require additional care here. */
6784 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6785 BFD_RELOC_LO16, AT);
6786 offset_expr.X_add_number += 4;
6787
6788 /* Set mips_optimize to 2 to avoid inserting an undesired
6789 nop. */
6790 hold_mips_optimize = mips_optimize;
6791 mips_optimize = 2;
6792 /* Itbl support may require additional care here. */
6793 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6794 BFD_RELOC_LO16, AT);
6795 mips_optimize = hold_mips_optimize;
6796 relax_end ();
6797 }
6693 if (breg != 0)
6694 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, breg, AT);
6695 /* Itbl support may require additional care here. */
6696 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6697 BFD_RELOC_LO16, AT);
6698 offset_expr.X_add_number += 4;
6699
6700 /* Set mips_optimize to 2 to avoid inserting an undesired
6701 nop. */
6702 hold_mips_optimize = mips_optimize;
6703 mips_optimize = 2;
6704 /* Itbl support may require additional care here. */
6705 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6706 BFD_RELOC_LO16, AT);
6707 mips_optimize = hold_mips_optimize;
6708 relax_end ();
6709 }
6798 else if (mips_pic == EMBEDDED_PIC)
6799 {
6800 /* If there is no base register, we use
6801 <op> $treg,<sym>($gp) (BFD_RELOC_GPREL16)
6802 <op> $treg+1,<sym>+4($gp) (BFD_RELOC_GPREL16)
6803 If we have a base register, we use
6804 addu $at,$breg,$gp
6805 <op> $treg,<sym>($at) (BFD_RELOC_GPREL16)
6806 <op> $treg+1,<sym>+4($at) (BFD_RELOC_GPREL16)
6807 */
6808 if (breg == 0)
6809 {
6810 tempreg = mips_gp_register;
6811 used_at = 0;
6812 }
6813 else
6814 {
6815 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t",
6816 AT, breg, mips_gp_register);
6817 tempreg = AT;
6818 used_at = 1;
6819 }
6820
6821 /* Itbl support may require additional care here. */
6822 macro_build (&offset_expr, s, fmt, coproc ? treg + 1 : treg,
6823 BFD_RELOC_GPREL16, tempreg);
6824 offset_expr.X_add_number += 4;
6825 /* Itbl support may require additional care here. */
6826 macro_build (&offset_expr, s, fmt, coproc ? treg : treg + 1,
6827 BFD_RELOC_GPREL16, tempreg);
6828 }
6829 else
6830 abort ();
6831
6710 else
6711 abort ();
6712
6832 if (! used_at)
6833 return;
6834
6835 break;
6836
6837 case M_LD_OB:
6838 s = "lw";
6839 goto sd_ob;
6840 case M_SD_OB:
6841 s = "sw";
6842 sd_ob:
6843 assert (HAVE_32BIT_ADDRESSES);
6844 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6845 offset_expr.X_add_number += 4;
6846 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6713 break;
6714
6715 case M_LD_OB:
6716 s = "lw";
6717 goto sd_ob;
6718 case M_SD_OB:
6719 s = "sw";
6720 sd_ob:
6721 assert (HAVE_32BIT_ADDRESSES);
6722 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
6723 offset_expr.X_add_number += 4;
6724 macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
6847 return;
6725 break;
6848
6726
6727 case M_SAA_AB:
6728 s = "saa";
6729 goto saa_saad;
6730
6731 case M_SAAD_AB:
6732 s = "saad";
6733
6734 saa_saad:
6735 /* The "saa/saad" instructions are new in CN58XX. These instructions
6736 do not specify offset. When invoked with address or symbol, then
6737 load the address or value of symbol in a register using the dla macro
6738 into AT, and pass the register for emitting "saa/saad" instruction.
6739 This will get expanded to
6740
6741 dla AT, constant/label
6742 saa/saad $treg,(AT) */
6743 {
6744 char *name = "dla";
6745 char *fmt = "t,A(b)";
6746 const struct mips_opcode *mo;
6747 struct mips_cl_insn insn;
6748
6749 mo = hash_find (op_hash, name);
6750 assert (strcmp (name, mo->name) == 0);
6751 assert (strcmp (fmt, mo->args) == 0);
6752 create_insn (&insn, mo);
6753
6754 insn.insn_opcode = insn.insn_mo->match;
6755
6756 used_at = 1;
6757 INSERT_OPERAND (RT, insn, AT);
6758 if (breg)
6759 INSERT_OPERAND (RS, insn, breg);
6760
6761 /* The address part is forwarded through the global offset_expr. */
6762 macro (&insn);
6763
6764 macro_build (NULL, s, "t,(b)", treg, AT);
6765 break;
6766 }
6767
6849 /* New code added to support COPZ instructions.
6850 This code builds table entries out of the macros in mip_opcodes.
6851 R4000 uses interlocks to handle coproc delays.
6852 Other chips (like the R3000) require nops to be inserted for delays.
6853
6854 FIXME: Currently, we require that the user handle delays.
6855 In order to fill delay slots for non-interlocked chips,
6856 we must have a way to specify delays based on the coprocessor.

--- 13 unchanged lines hidden (view full) ---

6870 s = "c1";
6871 goto copz;
6872 case M_COP2:
6873 s = "c2";
6874 goto copz;
6875 case M_COP3:
6876 s = "c3";
6877 copz:
6768 /* New code added to support COPZ instructions.
6769 This code builds table entries out of the macros in mip_opcodes.
6770 R4000 uses interlocks to handle coproc delays.
6771 Other chips (like the R3000) require nops to be inserted for delays.
6772
6773 FIXME: Currently, we require that the user handle delays.
6774 In order to fill delay slots for non-interlocked chips,
6775 we must have a way to specify delays based on the coprocessor.

--- 13 unchanged lines hidden (view full) ---

6789 s = "c1";
6790 goto copz;
6791 case M_COP2:
6792 s = "c2";
6793 goto copz;
6794 case M_COP3:
6795 s = "c3";
6796 copz:
6797 if (!strcmp (s,"c2") && mips_opts.arch == CPU_OCTEON
6798 && octeon_error_on_unsupported)
6799 {
6800 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name);
6801 return;
6802 }
6878 /* For now we just do C (same as Cz). The parameter will be
6879 stored in insn_opcode by mips_ip. */
6880 macro_build (NULL, s, "C", ip->insn_opcode);
6803 /* For now we just do C (same as Cz). The parameter will be
6804 stored in insn_opcode by mips_ip. */
6805 macro_build (NULL, s, "C", ip->insn_opcode);
6881 return;
6806 break;
6882
6883 case M_MOVE:
6884 move_register (dreg, sreg);
6807
6808 case M_MOVE:
6809 move_register (dreg, sreg);
6885 return;
6810 break;
6886
6887#ifdef LOSING_COMPILER
6888 default:
6889 /* Try and see if this is a new itbl instruction.
6890 This code builds table entries out of the macros in mip_opcodes.
6891 FIXME: For now we just assemble the expression and pass it's
6892 value along as a 32-bit immediate.
6893 We may want to have the assembler assemble this value,
6894 so that we gain the assembler's knowledge of delay slots,
6895 symbols, etc.
6896 Would it be more efficient to use mask (id) here? */
6897 if (itbl_have_entries
6898 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6899 {
6900 s = ip->insn_mo->name;
6901 s2 = "cop3";
6902 coproc = ITBL_DECODE_PNUM (immed_expr);;
6903 macro_build (&immed_expr, s, "C");
6811
6812#ifdef LOSING_COMPILER
6813 default:
6814 /* Try and see if this is a new itbl instruction.
6815 This code builds table entries out of the macros in mip_opcodes.
6816 FIXME: For now we just assemble the expression and pass it's
6817 value along as a 32-bit immediate.
6818 We may want to have the assembler assemble this value,
6819 so that we gain the assembler's knowledge of delay slots,
6820 symbols, etc.
6821 Would it be more efficient to use mask (id) here? */
6822 if (itbl_have_entries
6823 && (immed_expr = itbl_assemble (ip->insn_mo->name, "")))
6824 {
6825 s = ip->insn_mo->name;
6826 s2 = "cop3";
6827 coproc = ITBL_DECODE_PNUM (immed_expr);;
6828 macro_build (&immed_expr, s, "C");
6904 return;
6829 break;
6905 }
6906 macro2 (ip);
6830 }
6831 macro2 (ip);
6907 return;
6832 break;
6908 }
6833 }
6909 if (mips_opts.noat)
6910 as_warn (_("Macro used $at after \".set noat\""));
6834 if (mips_opts.noat && used_at)
6835 as_bad (_("Macro used $at after \".set noat\""));
6911}
6912
6913static void
6914macro2 (struct mips_cl_insn *ip)
6915{
6916 register int treg, sreg, dreg, breg;
6917 int tempreg;
6918 int mask;

--- 25 unchanged lines hidden (view full) ---

6944 {
6945#endif /* LOSING_COMPILER */
6946
6947 case M_DMUL:
6948 dbl = 1;
6949 case M_MUL:
6950 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6951 macro_build (NULL, "mflo", "d", dreg);
6836}
6837
6838static void
6839macro2 (struct mips_cl_insn *ip)
6840{
6841 register int treg, sreg, dreg, breg;
6842 int tempreg;
6843 int mask;

--- 25 unchanged lines hidden (view full) ---

6869 {
6870#endif /* LOSING_COMPILER */
6871
6872 case M_DMUL:
6873 dbl = 1;
6874 case M_MUL:
6875 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t", sreg, treg);
6876 macro_build (NULL, "mflo", "d", dreg);
6952 return;
6877 break;
6953
6954 case M_DMUL_I:
6955 dbl = 1;
6956 case M_MUL_I:
6957 /* The MIPS assembler some times generates shifts and adds. I'm
6958 not trying to be that fancy. GCC should do this for us
6959 anyway. */
6878
6879 case M_DMUL_I:
6880 dbl = 1;
6881 case M_MUL_I:
6882 /* The MIPS assembler some times generates shifts and adds. I'm
6883 not trying to be that fancy. GCC should do this for us
6884 anyway. */
6885 used_at = 1;
6960 load_register (AT, &imm_expr, dbl);
6961 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6962 macro_build (NULL, "mflo", "d", dreg);
6963 break;
6964
6965 case M_DMULO_I:
6966 dbl = 1;
6967 case M_MULO_I:
6968 imm = 1;
6969 goto do_mulo;
6970
6971 case M_DMULO:
6972 dbl = 1;
6973 case M_MULO:
6974 do_mulo:
6886 load_register (AT, &imm_expr, dbl);
6887 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, AT);
6888 macro_build (NULL, "mflo", "d", dreg);
6889 break;
6890
6891 case M_DMULO_I:
6892 dbl = 1;
6893 case M_MULO_I:
6894 imm = 1;
6895 goto do_mulo;
6896
6897 case M_DMULO:
6898 dbl = 1;
6899 case M_MULO:
6900 do_mulo:
6975 mips_emit_delays (TRUE);
6976 ++mips_opts.noreorder;
6977 mips_any_noreorder = 1;
6901 start_noreorder ();
6902 used_at = 1;
6978 if (imm)
6979 load_register (AT, &imm_expr, dbl);
6980 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6981 macro_build (NULL, "mflo", "d", dreg);
6982 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6983 macro_build (NULL, "mfhi", "d", AT);
6984 if (mips_trap)
6985 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6986 else
6987 {
6988 expr1.X_add_number = 8;
6989 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6990 macro_build (NULL, "nop", "", 0);
6991 macro_build (NULL, "break", "c", 6);
6992 }
6903 if (imm)
6904 load_register (AT, &imm_expr, dbl);
6905 macro_build (NULL, dbl ? "dmult" : "mult", "s,t", sreg, imm ? AT : treg);
6906 macro_build (NULL, "mflo", "d", dreg);
6907 macro_build (NULL, dbl ? "dsra32" : "sra", "d,w,<", dreg, dreg, RA);
6908 macro_build (NULL, "mfhi", "d", AT);
6909 if (mips_trap)
6910 macro_build (NULL, "tne", "s,t,q", dreg, AT, 6);
6911 else
6912 {
6913 expr1.X_add_number = 8;
6914 macro_build (&expr1, "beq", "s,t,p", dreg, AT);
6915 macro_build (NULL, "nop", "", 0);
6916 macro_build (NULL, "break", "c", 6);
6917 }
6993 --mips_opts.noreorder;
6918 end_noreorder ();
6994 macro_build (NULL, "mflo", "d", dreg);
6995 break;
6996
6997 case M_DMULOU_I:
6998 dbl = 1;
6999 case M_MULOU_I:
7000 imm = 1;
7001 goto do_mulou;
7002
7003 case M_DMULOU:
7004 dbl = 1;
7005 case M_MULOU:
7006 do_mulou:
6919 macro_build (NULL, "mflo", "d", dreg);
6920 break;
6921
6922 case M_DMULOU_I:
6923 dbl = 1;
6924 case M_MULOU_I:
6925 imm = 1;
6926 goto do_mulou;
6927
6928 case M_DMULOU:
6929 dbl = 1;
6930 case M_MULOU:
6931 do_mulou:
7007 mips_emit_delays (TRUE);
7008 ++mips_opts.noreorder;
7009 mips_any_noreorder = 1;
6932 start_noreorder ();
6933 used_at = 1;
7010 if (imm)
7011 load_register (AT, &imm_expr, dbl);
7012 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
7013 sreg, imm ? AT : treg);
7014 macro_build (NULL, "mfhi", "d", AT);
7015 macro_build (NULL, "mflo", "d", dreg);
7016 if (mips_trap)
7017 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
7018 else
7019 {
7020 expr1.X_add_number = 8;
7021 macro_build (&expr1, "beq", "s,t,p", AT, 0);
7022 macro_build (NULL, "nop", "", 0);
7023 macro_build (NULL, "break", "c", 6);
7024 }
6934 if (imm)
6935 load_register (AT, &imm_expr, dbl);
6936 macro_build (NULL, dbl ? "dmultu" : "multu", "s,t",
6937 sreg, imm ? AT : treg);
6938 macro_build (NULL, "mfhi", "d", AT);
6939 macro_build (NULL, "mflo", "d", dreg);
6940 if (mips_trap)
6941 macro_build (NULL, "tne", "s,t,q", AT, 0, 6);
6942 else
6943 {
6944 expr1.X_add_number = 8;
6945 macro_build (&expr1, "beq", "s,t,p", AT, 0);
6946 macro_build (NULL, "nop", "", 0);
6947 macro_build (NULL, "break", "c", 6);
6948 }
7025 --mips_opts.noreorder;
6949 end_noreorder ();
7026 break;
7027
7028 case M_DROL:
7029 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7030 {
7031 if (dreg == sreg)
7032 {
7033 tempreg = AT;
7034 used_at = 1;
7035 }
7036 else
7037 {
7038 tempreg = dreg;
6950 break;
6951
6952 case M_DROL:
6953 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
6954 {
6955 if (dreg == sreg)
6956 {
6957 tempreg = AT;
6958 used_at = 1;
6959 }
6960 else
6961 {
6962 tempreg = dreg;
7039 used_at = 0;
7040 }
7041 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
7042 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
6963 }
6964 macro_build (NULL, "dnegu", "d,w", tempreg, treg);
6965 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, tempreg);
7043 if (used_at)
7044 break;
7045 return;
6966 break;
7046 }
6967 }
6968 used_at = 1;
7047 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7048 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
7049 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
7050 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7051 break;
7052
7053 case M_ROL:
7054 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7055 {
7056 if (dreg == sreg)
7057 {
7058 tempreg = AT;
7059 used_at = 1;
7060 }
7061 else
7062 {
7063 tempreg = dreg;
6969 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
6970 macro_build (NULL, "dsrlv", "d,t,s", AT, sreg, AT);
6971 macro_build (NULL, "dsllv", "d,t,s", dreg, sreg, treg);
6972 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6973 break;
6974
6975 case M_ROL:
6976 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
6977 {
6978 if (dreg == sreg)
6979 {
6980 tempreg = AT;
6981 used_at = 1;
6982 }
6983 else
6984 {
6985 tempreg = dreg;
7064 used_at = 0;
7065 }
7066 macro_build (NULL, "negu", "d,w", tempreg, treg);
7067 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
6986 }
6987 macro_build (NULL, "negu", "d,w", tempreg, treg);
6988 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, tempreg);
7068 if (used_at)
7069 break;
7070 return;
6989 break;
7071 }
6990 }
6991 used_at = 1;
7072 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7073 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
7074 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
7075 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7076 break;
7077
7078 case M_DROL_I:
7079 {

--- 5 unchanged lines hidden (view full) ---

7085 rot = imm_expr.X_add_number & 0x3f;
7086 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7087 {
7088 rot = (64 - rot) & 0x3f;
7089 if (rot >= 32)
7090 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7091 else
7092 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
6992 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
6993 macro_build (NULL, "srlv", "d,t,s", AT, sreg, AT);
6994 macro_build (NULL, "sllv", "d,t,s", dreg, sreg, treg);
6995 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
6996 break;
6997
6998 case M_DROL_I:
6999 {

--- 5 unchanged lines hidden (view full) ---

7005 rot = imm_expr.X_add_number & 0x3f;
7006 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7007 {
7008 rot = (64 - rot) & 0x3f;
7009 if (rot >= 32)
7010 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7011 else
7012 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7093 return;
7013 break;
7094 }
7095 if (rot == 0)
7096 {
7097 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7014 }
7015 if (rot == 0)
7016 {
7017 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7098 return;
7018 break;
7099 }
7100 l = (rot < 0x20) ? "dsll" : "dsll32";
7101 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7102 rot &= 0x1f;
7019 }
7020 l = (rot < 0x20) ? "dsll" : "dsll32";
7021 r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
7022 rot &= 0x1f;
7023 used_at = 1;
7103 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7104 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7105 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7106 }
7107 break;
7108
7109 case M_ROL_I:
7110 {
7111 unsigned int rot;
7112
7113 if (imm_expr.X_op != O_constant)
7114 as_bad (_("Improper rotate count"));
7115 rot = imm_expr.X_add_number & 0x1f;
7116 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7117 {
7118 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7024 macro_build (NULL, l, "d,w,<", AT, sreg, rot);
7025 macro_build (NULL, r, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7026 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7027 }
7028 break;
7029
7030 case M_ROL_I:
7031 {
7032 unsigned int rot;
7033
7034 if (imm_expr.X_op != O_constant)
7035 as_bad (_("Improper rotate count"));
7036 rot = imm_expr.X_add_number & 0x1f;
7037 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7038 {
7039 macro_build (NULL, "ror", "d,w,<", dreg, sreg, (32 - rot) & 0x1f);
7119 return;
7040 break;
7120 }
7121 if (rot == 0)
7122 {
7123 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7041 }
7042 if (rot == 0)
7043 {
7044 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7124 return;
7045 break;
7125 }
7046 }
7047 used_at = 1;
7126 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7127 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7128 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7129 }
7130 break;
7131
7132 case M_DROR:
7133 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7134 {
7135 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7048 macro_build (NULL, "sll", "d,w,<", AT, sreg, rot);
7049 macro_build (NULL, "srl", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7050 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7051 }
7052 break;
7053
7054 case M_DROR:
7055 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7056 {
7057 macro_build (NULL, "drorv", "d,t,s", dreg, sreg, treg);
7136 return;
7058 break;
7137 }
7059 }
7060 used_at = 1;
7138 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7139 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7140 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7141 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7142 break;
7143
7144 case M_ROR:
7145 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7146 {
7147 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7061 macro_build (NULL, "dsubu", "d,v,t", AT, 0, treg);
7062 macro_build (NULL, "dsllv", "d,t,s", AT, sreg, AT);
7063 macro_build (NULL, "dsrlv", "d,t,s", dreg, sreg, treg);
7064 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7065 break;
7066
7067 case M_ROR:
7068 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7069 {
7070 macro_build (NULL, "rorv", "d,t,s", dreg, sreg, treg);
7148 return;
7071 break;
7149 }
7072 }
7073 used_at = 1;
7150 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7151 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7152 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7153 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7154 break;
7155
7156 case M_DROR_I:
7157 {

--- 4 unchanged lines hidden (view full) ---

7162 as_bad (_("Improper rotate count"));
7163 rot = imm_expr.X_add_number & 0x3f;
7164 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7165 {
7166 if (rot >= 32)
7167 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7168 else
7169 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7074 macro_build (NULL, "subu", "d,v,t", AT, 0, treg);
7075 macro_build (NULL, "sllv", "d,t,s", AT, sreg, AT);
7076 macro_build (NULL, "srlv", "d,t,s", dreg, sreg, treg);
7077 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7078 break;
7079
7080 case M_DROR_I:
7081 {

--- 4 unchanged lines hidden (view full) ---

7086 as_bad (_("Improper rotate count"));
7087 rot = imm_expr.X_add_number & 0x3f;
7088 if (ISA_HAS_DROR (mips_opts.isa) || CPU_HAS_DROR (mips_opts.arch))
7089 {
7090 if (rot >= 32)
7091 macro_build (NULL, "dror32", "d,w,<", dreg, sreg, rot - 32);
7092 else
7093 macro_build (NULL, "dror", "d,w,<", dreg, sreg, rot);
7170 return;
7094 break;
7171 }
7172 if (rot == 0)
7173 {
7174 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7095 }
7096 if (rot == 0)
7097 {
7098 macro_build (NULL, "dsrl", "d,w,<", dreg, sreg, 0);
7175 return;
7099 break;
7176 }
7177 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7178 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7179 rot &= 0x1f;
7100 }
7101 r = (rot < 0x20) ? "dsrl" : "dsrl32";
7102 l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
7103 rot &= 0x1f;
7104 used_at = 1;
7180 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7181 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7182 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7183 }
7184 break;
7185
7186 case M_ROR_I:
7187 {
7188 unsigned int rot;
7189
7190 if (imm_expr.X_op != O_constant)
7191 as_bad (_("Improper rotate count"));
7192 rot = imm_expr.X_add_number & 0x1f;
7193 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7194 {
7195 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7105 macro_build (NULL, r, "d,w,<", AT, sreg, rot);
7106 macro_build (NULL, l, "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7107 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7108 }
7109 break;
7110
7111 case M_ROR_I:
7112 {
7113 unsigned int rot;
7114
7115 if (imm_expr.X_op != O_constant)
7116 as_bad (_("Improper rotate count"));
7117 rot = imm_expr.X_add_number & 0x1f;
7118 if (ISA_HAS_ROR (mips_opts.isa) || CPU_HAS_ROR (mips_opts.arch))
7119 {
7120 macro_build (NULL, "ror", "d,w,<", dreg, sreg, rot);
7196 return;
7121 break;
7197 }
7198 if (rot == 0)
7199 {
7200 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7122 }
7123 if (rot == 0)
7124 {
7125 macro_build (NULL, "srl", "d,w,<", dreg, sreg, 0);
7201 return;
7126 break;
7202 }
7127 }
7128 used_at = 1;
7203 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7204 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7205 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7206 }
7207 break;
7208
7209 case M_S_DOB:
7210 if (mips_opts.arch == CPU_R4650)
7211 {
7212 as_bad (_("opcode not supported on this processor"));
7129 macro_build (NULL, "srl", "d,w,<", AT, sreg, rot);
7130 macro_build (NULL, "sll", "d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
7131 macro_build (NULL, "or", "d,v,t", dreg, dreg, AT);
7132 }
7133 break;
7134
7135 case M_S_DOB:
7136 if (mips_opts.arch == CPU_R4650)
7137 {
7138 as_bad (_("opcode not supported on this processor"));
7213 return;
7139 break;
7214 }
7215 assert (mips_opts.isa == ISA_MIPS1);
7216 /* Even on a big endian machine $fn comes before $fn+1. We have
7217 to adjust when storing to memory. */
7218 macro_build (&offset_expr, "swc1", "T,o(b)",
7219 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7220 offset_expr.X_add_number += 4;
7221 macro_build (&offset_expr, "swc1", "T,o(b)",
7222 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7140 }
7141 assert (mips_opts.isa == ISA_MIPS1);
7142 /* Even on a big endian machine $fn comes before $fn+1. We have
7143 to adjust when storing to memory. */
7144 macro_build (&offset_expr, "swc1", "T,o(b)",
7145 target_big_endian ? treg + 1 : treg, BFD_RELOC_LO16, breg);
7146 offset_expr.X_add_number += 4;
7147 macro_build (&offset_expr, "swc1", "T,o(b)",
7148 target_big_endian ? treg : treg + 1, BFD_RELOC_LO16, breg);
7223 return;
7149 break;
7224
7225 case M_SEQ:
7226 if (sreg == 0)
7227 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7228 else if (treg == 0)
7229 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7230 else
7231 {
7232 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7233 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7234 }
7150
7151 case M_SEQ:
7152 if (sreg == 0)
7153 macro_build (&expr1, "sltiu", "t,r,j", dreg, treg, BFD_RELOC_LO16);
7154 else if (treg == 0)
7155 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7156 else
7157 {
7158 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7159 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7160 }
7235 return;
7161 break;
7236
7237 case M_SEQ_I:
7238 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7239 {
7240 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7162
7163 case M_SEQ_I:
7164 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7165 {
7166 macro_build (&expr1, "sltiu", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7241 return;
7167 break;
7242 }
7243 if (sreg == 0)
7244 {
7245 as_warn (_("Instruction %s: result is always false"),
7246 ip->insn_mo->name);
7247 move_register (dreg, 0);
7168 }
7169 if (sreg == 0)
7170 {
7171 as_warn (_("Instruction %s: result is always false"),
7172 ip->insn_mo->name);
7173 move_register (dreg, 0);
7248 return;
7174 break;
7249 }
7250 if (imm_expr.X_op == O_constant
7251 && imm_expr.X_add_number >= 0
7252 && imm_expr.X_add_number < 0x10000)
7253 {
7254 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7175 }
7176 if (imm_expr.X_op == O_constant
7177 && imm_expr.X_add_number >= 0
7178 && imm_expr.X_add_number < 0x10000)
7179 {
7180 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7255 used_at = 0;
7256 }
7257 else if (imm_expr.X_op == O_constant
7258 && imm_expr.X_add_number > -0x8000
7259 && imm_expr.X_add_number < 0)
7260 {
7261 imm_expr.X_add_number = -imm_expr.X_add_number;
7262 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7263 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7181 }
7182 else if (imm_expr.X_op == O_constant
7183 && imm_expr.X_add_number > -0x8000
7184 && imm_expr.X_add_number < 0)
7185 {
7186 imm_expr.X_add_number = -imm_expr.X_add_number;
7187 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7188 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7264 used_at = 0;
7265 }
7266 else
7267 {
7268 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7269 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7270 used_at = 1;
7271 }
7272 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7189 }
7190 else
7191 {
7192 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7193 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7194 used_at = 1;
7195 }
7196 macro_build (&expr1, "sltiu", "t,r,j", dreg, dreg, BFD_RELOC_LO16);
7273 if (used_at)
7274 break;
7275 return;
7197 break;
7276
7277 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7278 s = "slt";
7279 goto sge;
7280 case M_SGEU:
7281 s = "sltu";
7282 sge:
7283 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7284 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7198
7199 case M_SGE: /* sreg >= treg <==> not (sreg < treg) */
7200 s = "slt";
7201 goto sge;
7202 case M_SGEU:
7203 s = "sltu";
7204 sge:
7205 macro_build (NULL, s, "d,v,t", dreg, sreg, treg);
7206 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7285 return;
7207 break;
7286
7287 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7288 case M_SGEU_I:
7289 if (imm_expr.X_op == O_constant
7290 && imm_expr.X_add_number >= -0x8000
7291 && imm_expr.X_add_number < 0x8000)
7292 {
7293 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7294 dreg, sreg, BFD_RELOC_LO16);
7208
7209 case M_SGE_I: /* sreg >= I <==> not (sreg < I) */
7210 case M_SGEU_I:
7211 if (imm_expr.X_op == O_constant
7212 && imm_expr.X_add_number >= -0x8000
7213 && imm_expr.X_add_number < 0x8000)
7214 {
7215 macro_build (&imm_expr, mask == M_SGE_I ? "slti" : "sltiu", "t,r,j",
7216 dreg, sreg, BFD_RELOC_LO16);
7295 used_at = 0;
7296 }
7297 else
7298 {
7299 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7300 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7301 dreg, sreg, AT);
7302 used_at = 1;
7303 }
7304 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7217 }
7218 else
7219 {
7220 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7221 macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t",
7222 dreg, sreg, AT);
7223 used_at = 1;
7224 }
7225 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7305 if (used_at)
7306 break;
7307 return;
7226 break;
7308
7309 case M_SGT: /* sreg > treg <==> treg < sreg */
7310 s = "slt";
7311 goto sgt;
7312 case M_SGTU:
7313 s = "sltu";
7314 sgt:
7315 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7227
7228 case M_SGT: /* sreg > treg <==> treg < sreg */
7229 s = "slt";
7230 goto sgt;
7231 case M_SGTU:
7232 s = "sltu";
7233 sgt:
7234 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7316 return;
7235 break;
7317
7318 case M_SGT_I: /* sreg > I <==> I < sreg */
7319 s = "slt";
7320 goto sgti;
7321 case M_SGTU_I:
7322 s = "sltu";
7323 sgti:
7236
7237 case M_SGT_I: /* sreg > I <==> I < sreg */
7238 s = "slt";
7239 goto sgti;
7240 case M_SGTU_I:
7241 s = "sltu";
7242 sgti:
7243 used_at = 1;
7324 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7325 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7326 break;
7327
7328 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7329 s = "slt";
7330 goto sle;
7331 case M_SLEU:
7332 s = "sltu";
7333 sle:
7334 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7335 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7244 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7245 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7246 break;
7247
7248 case M_SLE: /* sreg <= treg <==> treg >= sreg <==> not (treg < sreg) */
7249 s = "slt";
7250 goto sle;
7251 case M_SLEU:
7252 s = "sltu";
7253 sle:
7254 macro_build (NULL, s, "d,v,t", dreg, treg, sreg);
7255 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7336 return;
7256 break;
7337
7338 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7339 s = "slt";
7340 goto slei;
7341 case M_SLEU_I:
7342 s = "sltu";
7343 slei:
7257
7258 case M_SLE_I: /* sreg <= I <==> I >= sreg <==> not (I < sreg) */
7259 s = "slt";
7260 goto slei;
7261 case M_SLEU_I:
7262 s = "sltu";
7263 slei:
7264 used_at = 1;
7344 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7345 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7346 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7347 break;
7348
7349 case M_SLT_I:
7350 if (imm_expr.X_op == O_constant
7351 && imm_expr.X_add_number >= -0x8000
7352 && imm_expr.X_add_number < 0x8000)
7353 {
7354 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7265 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7266 macro_build (NULL, s, "d,v,t", dreg, AT, sreg);
7267 macro_build (&expr1, "xori", "t,r,i", dreg, dreg, BFD_RELOC_LO16);
7268 break;
7269
7270 case M_SLT_I:
7271 if (imm_expr.X_op == O_constant
7272 && imm_expr.X_add_number >= -0x8000
7273 && imm_expr.X_add_number < 0x8000)
7274 {
7275 macro_build (&imm_expr, "slti", "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7355 return;
7276 break;
7356 }
7277 }
7278 used_at = 1;
7357 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7358 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7359 break;
7360
7361 case M_SLTU_I:
7362 if (imm_expr.X_op == O_constant
7363 && imm_expr.X_add_number >= -0x8000
7364 && imm_expr.X_add_number < 0x8000)
7365 {
7366 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7367 BFD_RELOC_LO16);
7279 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7280 macro_build (NULL, "slt", "d,v,t", dreg, sreg, AT);
7281 break;
7282
7283 case M_SLTU_I:
7284 if (imm_expr.X_op == O_constant
7285 && imm_expr.X_add_number >= -0x8000
7286 && imm_expr.X_add_number < 0x8000)
7287 {
7288 macro_build (&imm_expr, "sltiu", "t,r,j", dreg, sreg,
7289 BFD_RELOC_LO16);
7368 return;
7290 break;
7369 }
7291 }
7292 used_at = 1;
7370 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7371 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7372 break;
7373
7374 case M_SNE:
7375 if (sreg == 0)
7376 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7377 else if (treg == 0)
7378 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7379 else
7380 {
7381 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7382 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7383 }
7293 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7294 macro_build (NULL, "sltu", "d,v,t", dreg, sreg, AT);
7295 break;
7296
7297 case M_SNE:
7298 if (sreg == 0)
7299 macro_build (NULL, "sltu", "d,v,t", dreg, 0, treg);
7300 else if (treg == 0)
7301 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7302 else
7303 {
7304 macro_build (NULL, "xor", "d,v,t", dreg, sreg, treg);
7305 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7306 }
7384 return;
7307 break;
7385
7386 case M_SNE_I:
7387 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7388 {
7389 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7308
7309 case M_SNE_I:
7310 if (imm_expr.X_op == O_constant && imm_expr.X_add_number == 0)
7311 {
7312 macro_build (NULL, "sltu", "d,v,t", dreg, 0, sreg);
7390 return;
7313 break;
7391 }
7392 if (sreg == 0)
7393 {
7394 as_warn (_("Instruction %s: result is always true"),
7395 ip->insn_mo->name);
7396 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7397 dreg, 0, BFD_RELOC_LO16);
7314 }
7315 if (sreg == 0)
7316 {
7317 as_warn (_("Instruction %s: result is always true"),
7318 ip->insn_mo->name);
7319 macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
7320 dreg, 0, BFD_RELOC_LO16);
7398 return;
7321 break;
7399 }
7400 if (imm_expr.X_op == O_constant
7401 && imm_expr.X_add_number >= 0
7402 && imm_expr.X_add_number < 0x10000)
7403 {
7404 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7322 }
7323 if (imm_expr.X_op == O_constant
7324 && imm_expr.X_add_number >= 0
7325 && imm_expr.X_add_number < 0x10000)
7326 {
7327 macro_build (&imm_expr, "xori", "t,r,i", dreg, sreg, BFD_RELOC_LO16);
7405 used_at = 0;
7406 }
7407 else if (imm_expr.X_op == O_constant
7408 && imm_expr.X_add_number > -0x8000
7409 && imm_expr.X_add_number < 0)
7410 {
7411 imm_expr.X_add_number = -imm_expr.X_add_number;
7412 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7413 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7328 }
7329 else if (imm_expr.X_op == O_constant
7330 && imm_expr.X_add_number > -0x8000
7331 && imm_expr.X_add_number < 0)
7332 {
7333 imm_expr.X_add_number = -imm_expr.X_add_number;
7334 macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu",
7335 "t,r,j", dreg, sreg, BFD_RELOC_LO16);
7414 used_at = 0;
7415 }
7416 else
7417 {
7418 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7419 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7420 used_at = 1;
7421 }
7422 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7336 }
7337 else
7338 {
7339 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7340 macro_build (NULL, "xor", "d,v,t", dreg, sreg, AT);
7341 used_at = 1;
7342 }
7343 macro_build (NULL, "sltu", "d,v,t", dreg, 0, dreg);
7423 if (used_at)
7424 break;
7425 return;
7344 break;
7426
7427 case M_DSUB_I:
7428 dbl = 1;
7429 case M_SUB_I:
7430 if (imm_expr.X_op == O_constant
7431 && imm_expr.X_add_number > -0x8000
7432 && imm_expr.X_add_number <= 0x8000)
7433 {
7434 imm_expr.X_add_number = -imm_expr.X_add_number;
7435 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7436 dreg, sreg, BFD_RELOC_LO16);
7345
7346 case M_DSUB_I:
7347 dbl = 1;
7348 case M_SUB_I:
7349 if (imm_expr.X_op == O_constant
7350 && imm_expr.X_add_number > -0x8000
7351 && imm_expr.X_add_number <= 0x8000)
7352 {
7353 imm_expr.X_add_number = -imm_expr.X_add_number;
7354 macro_build (&imm_expr, dbl ? "daddi" : "addi", "t,r,j",
7355 dreg, sreg, BFD_RELOC_LO16);
7437 return;
7356 break;
7438 }
7357 }
7358 used_at = 1;
7439 load_register (AT, &imm_expr, dbl);
7440 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7441 break;
7442
7443 case M_DSUBU_I:
7444 dbl = 1;
7445 case M_SUBU_I:
7446 if (imm_expr.X_op == O_constant
7447 && imm_expr.X_add_number > -0x8000
7448 && imm_expr.X_add_number <= 0x8000)
7449 {
7450 imm_expr.X_add_number = -imm_expr.X_add_number;
7451 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7452 dreg, sreg, BFD_RELOC_LO16);
7359 load_register (AT, &imm_expr, dbl);
7360 macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", dreg, sreg, AT);
7361 break;
7362
7363 case M_DSUBU_I:
7364 dbl = 1;
7365 case M_SUBU_I:
7366 if (imm_expr.X_op == O_constant
7367 && imm_expr.X_add_number > -0x8000
7368 && imm_expr.X_add_number <= 0x8000)
7369 {
7370 imm_expr.X_add_number = -imm_expr.X_add_number;
7371 macro_build (&imm_expr, dbl ? "daddiu" : "addiu", "t,r,j",
7372 dreg, sreg, BFD_RELOC_LO16);
7453 return;
7373 break;
7454 }
7374 }
7375 used_at = 1;
7455 load_register (AT, &imm_expr, dbl);
7456 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7457 break;
7458
7459 case M_TEQ_I:
7460 s = "teq";
7461 goto trap;
7462 case M_TGE_I:

--- 6 unchanged lines hidden (view full) ---

7469 s = "tlt";
7470 goto trap;
7471 case M_TLTU_I:
7472 s = "tltu";
7473 goto trap;
7474 case M_TNE_I:
7475 s = "tne";
7476 trap:
7376 load_register (AT, &imm_expr, dbl);
7377 macro_build (NULL, dbl ? "dsubu" : "subu", "d,v,t", dreg, sreg, AT);
7378 break;
7379
7380 case M_TEQ_I:
7381 s = "teq";
7382 goto trap;
7383 case M_TGE_I:

--- 6 unchanged lines hidden (view full) ---

7390 s = "tlt";
7391 goto trap;
7392 case M_TLTU_I:
7393 s = "tltu";
7394 goto trap;
7395 case M_TNE_I:
7396 s = "tne";
7397 trap:
7398 used_at = 1;
7477 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7478 macro_build (NULL, s, "s,t", sreg, AT);
7479 break;
7480
7481 case M_TRUNCWS:
7482 case M_TRUNCWD:
7399 load_register (AT, &imm_expr, HAVE_64BIT_GPRS);
7400 macro_build (NULL, s, "s,t", sreg, AT);
7401 break;
7402
7403 case M_TRUNCWS:
7404 case M_TRUNCWD:
7405 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
7406 {
7407 as_bad (_("opcode not implemented in Octeon `%s'"), ip->insn_mo->name);
7408 return;
7409 }
7483 assert (mips_opts.isa == ISA_MIPS1);
7410 assert (mips_opts.isa == ISA_MIPS1);
7411 used_at = 1;
7484 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7485 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7486
7487 /*
7488 * Is the double cfc1 instruction a bug in the mips assembler;
7489 * or is there a reason for it?
7490 */
7412 sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */
7413 dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */
7414
7415 /*
7416 * Is the double cfc1 instruction a bug in the mips assembler;
7417 * or is there a reason for it?
7418 */
7491 mips_emit_delays (TRUE);
7492 ++mips_opts.noreorder;
7493 mips_any_noreorder = 1;
7419 start_noreorder ();
7494 macro_build (NULL, "cfc1", "t,G", treg, RA);
7495 macro_build (NULL, "cfc1", "t,G", treg, RA);
7496 macro_build (NULL, "nop", "");
7497 expr1.X_add_number = 3;
7498 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7499 expr1.X_add_number = 2;
7500 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7501 macro_build (NULL, "ctc1", "t,G", AT, RA);
7502 macro_build (NULL, "nop", "");
7503 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7504 dreg, sreg);
7505 macro_build (NULL, "ctc1", "t,G", treg, RA);
7506 macro_build (NULL, "nop", "");
7420 macro_build (NULL, "cfc1", "t,G", treg, RA);
7421 macro_build (NULL, "cfc1", "t,G", treg, RA);
7422 macro_build (NULL, "nop", "");
7423 expr1.X_add_number = 3;
7424 macro_build (&expr1, "ori", "t,r,i", AT, treg, BFD_RELOC_LO16);
7425 expr1.X_add_number = 2;
7426 macro_build (&expr1, "xori", "t,r,i", AT, AT, BFD_RELOC_LO16);
7427 macro_build (NULL, "ctc1", "t,G", AT, RA);
7428 macro_build (NULL, "nop", "");
7429 macro_build (NULL, mask == M_TRUNCWD ? "cvt.w.d" : "cvt.w.s", "D,S",
7430 dreg, sreg);
7431 macro_build (NULL, "ctc1", "t,G", treg, RA);
7432 macro_build (NULL, "nop", "");
7507 --mips_opts.noreorder;
7433 end_noreorder ();
7508 break;
7509
7510 case M_ULH:
7511 s = "lb";
7512 goto ulh;
7513 case M_ULHU:
7514 s = "lbu";
7515 ulh:
7434 break;
7435
7436 case M_ULH:
7437 s = "lb";
7438 goto ulh;
7439 case M_ULHU:
7440 s = "lbu";
7441 ulh:
7442 used_at = 1;
7516 if (offset_expr.X_add_number >= 0x7fff)
7517 as_bad (_("operand overflow"));
7443 if (offset_expr.X_add_number >= 0x7fff)
7444 as_bad (_("operand overflow"));
7445 /* Expand the ulh to "lb, lbu, ins" instead of "lb, lbu, sll, ori". */
7518 if (! target_big_endian)
7519 ++offset_expr.X_add_number;
7520 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7521 if (! target_big_endian)
7522 --offset_expr.X_add_number;
7523 else
7524 ++offset_expr.X_add_number;
7525 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7446 if (! target_big_endian)
7447 ++offset_expr.X_add_number;
7448 macro_build (&offset_expr, s, "t,o(b)", AT, BFD_RELOC_LO16, breg);
7449 if (! target_big_endian)
7450 --offset_expr.X_add_number;
7451 else
7452 ++offset_expr.X_add_number;
7453 macro_build (&offset_expr, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7526 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7527 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7454 if (ISA_HAS_INS (mips_opts.isa))
7455 macro_build (NULL, "ins", "t,r,+A,+B", treg, AT, 8, 31);
7456 else
7457 {
7458 macro_build (NULL, "sll", "d,w,<", AT, AT, 8);
7459 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7460 }
7528 break;
7529
7530 case M_ULD:
7531 s = "ldl";
7532 s2 = "ldr";
7533 off = 7;
7534 goto ulw;
7535 case M_ULW:
7536 s = "lwl";
7537 s2 = "lwr";
7538 off = 3;
7539 ulw:
7540 if (offset_expr.X_add_number >= 0x8000 - off)
7541 as_bad (_("operand overflow"));
7542 if (treg != breg)
7543 tempreg = treg;
7544 else
7461 break;
7462
7463 case M_ULD:
7464 s = "ldl";
7465 s2 = "ldr";
7466 off = 7;
7467 goto ulw;
7468 case M_ULW:
7469 s = "lwl";
7470 s2 = "lwr";
7471 off = 3;
7472 ulw:
7473 if (offset_expr.X_add_number >= 0x8000 - off)
7474 as_bad (_("operand overflow"));
7475 if (treg != breg)
7476 tempreg = treg;
7477 else
7545 tempreg = AT;
7478 {
7479 used_at = 1;
7480 tempreg = AT;
7481 }
7482
7483 /* For small variables the compiler uses gp_rel to load the value of
7484 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)"
7485 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
7486 type while emitting instructions otherwise use BFD_RELOC_LO16. */
7487 if (offset_reloc[0] == BFD_RELOC_UNUSED)
7488 offset_reloc[0] = BFD_RELOC_LO16;
7489
7490 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON)
7491 {
7492 /* Reset used_at as tempreg is not used while generating Octeon
7493 unaligned load/store. */
7494 used_at = 0;
7495 macro_build (&offset_expr, (mask == M_ULW ? "ulw" : "uld"), "t,o(b)",
7496 treg, offset_reloc[0], breg);
7497 break;
7498 }
7499
7546 if (! target_big_endian)
7547 offset_expr.X_add_number += off;
7500 if (! target_big_endian)
7501 offset_expr.X_add_number += off;
7548 macro_build (&offset_expr, s, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7502 macro_build (&offset_expr, s, "t,o(b)", tempreg, offset_reloc[0], breg);
7549 if (! target_big_endian)
7550 offset_expr.X_add_number -= off;
7551 else
7552 offset_expr.X_add_number += off;
7503 if (! target_big_endian)
7504 offset_expr.X_add_number -= off;
7505 else
7506 offset_expr.X_add_number += off;
7553 macro_build (&offset_expr, s2, "t,o(b)", tempreg, BFD_RELOC_LO16, breg);
7507 macro_build (&offset_expr, s2, "t,o(b)", tempreg, offset_reloc[0], breg);
7554
7555 /* If necessary, move the result in tempreg the final destination. */
7556 if (treg == tempreg)
7508
7509 /* If necessary, move the result in tempreg the final destination. */
7510 if (treg == tempreg)
7557 return;
7511 break;
7558 /* Protect second load's delay slot. */
7512 /* Protect second load's delay slot. */
7559 if (!gpr_interlocks)
7560 macro_build (NULL, "nop", "");
7513 load_delay_nop ();
7561 move_register (treg, tempreg);
7562 break;
7563
7564 case M_ULD_A:
7565 s = "ldl";
7566 s2 = "ldr";
7567 off = 7;
7568 goto ulwa;
7569 case M_ULW_A:
7570 s = "lwl";
7571 s2 = "lwr";
7572 off = 3;
7573 ulwa:
7574 used_at = 1;
7575 load_address (AT, &offset_expr, &used_at);
7576 if (breg != 0)
7577 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7514 move_register (treg, tempreg);
7515 break;
7516
7517 case M_ULD_A:
7518 s = "ldl";
7519 s2 = "ldr";
7520 off = 7;
7521 goto ulwa;
7522 case M_ULW_A:
7523 s = "lwl";
7524 s2 = "lwr";
7525 off = 3;
7526 ulwa:
7527 used_at = 1;
7528 load_address (AT, &offset_expr, &used_at);
7529 if (breg != 0)
7530 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7531
7532 /* For small variables the compiler uses gp_rel to load the value of
7533 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)"
7534 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
7535 type while emitting instructions otherwise use BFD_RELOC_LO16. */
7536 if (offset_reloc[0] == BFD_RELOC_UNUSED)
7537 offset_reloc[0] = BFD_RELOC_LO16;
7538
7539 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON)
7540 {
7541 macro_build (&offset_expr, (mask == M_ULW_A ? "ulw" : "uld"),
7542 "t,o(b)", treg, offset_reloc[0], AT);
7543 break;
7544 }
7545
7578 if (! target_big_endian)
7579 expr1.X_add_number = off;
7580 else
7581 expr1.X_add_number = 0;
7546 if (! target_big_endian)
7547 expr1.X_add_number = off;
7548 else
7549 expr1.X_add_number = 0;
7582 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7550 macro_build (&expr1, s, "t,o(b)", treg, offset_reloc[0], AT);
7583 if (! target_big_endian)
7584 expr1.X_add_number = 0;
7585 else
7586 expr1.X_add_number = off;
7551 if (! target_big_endian)
7552 expr1.X_add_number = 0;
7553 else
7554 expr1.X_add_number = off;
7587 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7555 macro_build (&expr1, s2, "t,o(b)", treg, offset_reloc[0], AT);
7588 break;
7589
7590 case M_ULH_A:
7591 case M_ULHU_A:
7592 used_at = 1;
7593 load_address (AT, &offset_expr, &used_at);
7594 if (breg != 0)
7595 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7556 break;
7557
7558 case M_ULH_A:
7559 case M_ULHU_A:
7560 used_at = 1;
7561 load_address (AT, &offset_expr, &used_at);
7562 if (breg != 0)
7563 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7564
7565 if (ISA_HAS_INS (mips_opts.isa))
7566 {
7567 if (target_big_endian)
7568 expr1.X_add_number = 1;
7569 else
7570 expr1.X_add_number = 0;
7571 macro_build (&expr1, "lbu", "t,o(b)", treg, BFD_RELOC_LO16, AT);
7572 if (target_big_endian)
7573 expr1.X_add_number = 0;
7574 else
7575 expr1.X_add_number = 1;
7576 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7577 AT, BFD_RELOC_LO16, AT);
7578 macro_build (NULL, "ins", "t,r,+A,+B", treg, AT, 8, 31);
7579 break;
7580 }
7596 if (target_big_endian)
7597 expr1.X_add_number = 0;
7598 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7599 treg, BFD_RELOC_LO16, AT);
7600 if (target_big_endian)
7601 expr1.X_add_number = 1;
7602 else
7603 expr1.X_add_number = 0;
7604 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7605 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7606 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7607 break;
7608
7609 case M_USH:
7581 if (target_big_endian)
7582 expr1.X_add_number = 0;
7583 macro_build (&expr1, mask == M_ULH_A ? "lb" : "lbu", "t,o(b)",
7584 treg, BFD_RELOC_LO16, AT);
7585 if (target_big_endian)
7586 expr1.X_add_number = 1;
7587 else
7588 expr1.X_add_number = 0;
7589 macro_build (&expr1, "lbu", "t,o(b)", AT, BFD_RELOC_LO16, AT);
7590 macro_build (NULL, "sll", "d,w,<", treg, treg, 8);
7591 macro_build (NULL, "or", "d,v,t", treg, treg, AT);
7592 break;
7593
7594 case M_USH:
7595 used_at = 1;
7610 if (offset_expr.X_add_number >= 0x7fff)
7611 as_bad (_("operand overflow"));
7612 if (target_big_endian)
7613 ++offset_expr.X_add_number;
7614 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7615 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7616 if (target_big_endian)
7617 --offset_expr.X_add_number;

--- 9 unchanged lines hidden (view full) ---

7627 goto usw;
7628 case M_USW:
7629 s = "swl";
7630 s2 = "swr";
7631 off = 3;
7632 usw:
7633 if (offset_expr.X_add_number >= 0x8000 - off)
7634 as_bad (_("operand overflow"));
7596 if (offset_expr.X_add_number >= 0x7fff)
7597 as_bad (_("operand overflow"));
7598 if (target_big_endian)
7599 ++offset_expr.X_add_number;
7600 macro_build (&offset_expr, "sb", "t,o(b)", treg, BFD_RELOC_LO16, breg);
7601 macro_build (NULL, "srl", "d,w,<", AT, treg, 8);
7602 if (target_big_endian)
7603 --offset_expr.X_add_number;

--- 9 unchanged lines hidden (view full) ---

7613 goto usw;
7614 case M_USW:
7615 s = "swl";
7616 s2 = "swr";
7617 off = 3;
7618 usw:
7619 if (offset_expr.X_add_number >= 0x8000 - off)
7620 as_bad (_("operand overflow"));
7621
7622 /* For small variables the compiler uses gp_rel to load the value of
7623 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)"
7624 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
7625 type while emitting instructions otherwise use BFD_RELOC_LO16. */
7626 if (offset_reloc[0] == BFD_RELOC_UNUSED)
7627 offset_reloc[0] = BFD_RELOC_LO16;
7628
7629 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON)
7630 {
7631 macro_build (&offset_expr, (mask == M_USD ? "usd" : "usw"),
7632 "t,o(b)", treg, offset_reloc[0], breg);
7633 break;
7634 }
7635 if (! target_big_endian)
7636 offset_expr.X_add_number += off;
7635 if (! target_big_endian)
7636 offset_expr.X_add_number += off;
7637 macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7637 macro_build (&offset_expr, s, "t,o(b)", treg, offset_reloc[0], breg);
7638 if (! target_big_endian)
7639 offset_expr.X_add_number -= off;
7640 else
7641 offset_expr.X_add_number += off;
7638 if (! target_big_endian)
7639 offset_expr.X_add_number -= off;
7640 else
7641 offset_expr.X_add_number += off;
7642 macro_build (&offset_expr, s2, "t,o(b)", treg, BFD_RELOC_LO16, breg);
7643 return;
7642 macro_build (&offset_expr, s2, "t,o(b)", treg, offset_reloc[0], breg);
7643 break;
7644
7645 case M_USD_A:
7646 s = "sdl";
7647 s2 = "sdr";
7648 off = 7;
7649 goto uswa;
7650 case M_USW_A:
7651 s = "swl";
7652 s2 = "swr";
7653 off = 3;
7654 uswa:
7655 used_at = 1;
7656 load_address (AT, &offset_expr, &used_at);
7657 if (breg != 0)
7658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7644
7645 case M_USD_A:
7646 s = "sdl";
7647 s2 = "sdr";
7648 off = 7;
7649 goto uswa;
7650 case M_USW_A:
7651 s = "swl";
7652 s2 = "swr";
7653 off = 3;
7654 uswa:
7655 used_at = 1;
7656 load_address (AT, &offset_expr, &used_at);
7657 if (breg != 0)
7658 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7659
7660 /* For small variables the compiler uses gp_rel to load the value of
7661 the variables. While parsing instructions "uld $2,%gp_rel(var)($28)"
7662 the offset_reloc[0] is set to BFD_RELOC_GPREL16. Use this relocation
7663 type while emitting instructions otherwise use BFD_RELOC_LO16. */
7664 if (offset_reloc[0] == BFD_RELOC_UNUSED)
7665 offset_reloc[0] = BFD_RELOC_LO16;
7666
7667 if (octeon_use_unalign && mips_opts.arch == CPU_OCTEON)
7668 {
7669 macro_build (&offset_expr, (mask == M_USW_A ? "usw" : "usd"),
7670 "t,o(b)", treg, offset_reloc[0], AT);
7671 break;
7672 }
7659 if (! target_big_endian)
7660 expr1.X_add_number = off;
7661 else
7662 expr1.X_add_number = 0;
7673 if (! target_big_endian)
7674 expr1.X_add_number = off;
7675 else
7676 expr1.X_add_number = 0;
7663 macro_build (&expr1, s, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7677 macro_build (&expr1, s, "t,o(b)", treg, offset_reloc[0], AT);
7664 if (! target_big_endian)
7665 expr1.X_add_number = 0;
7666 else
7667 expr1.X_add_number = off;
7678 if (! target_big_endian)
7679 expr1.X_add_number = 0;
7680 else
7681 expr1.X_add_number = off;
7668 macro_build (&expr1, s2, "t,o(b)", treg, BFD_RELOC_LO16, AT);
7682 macro_build (&expr1, s2, "t,o(b)", treg, offset_reloc[0], AT);
7669 break;
7670
7671 case M_USH_A:
7672 used_at = 1;
7673 load_address (AT, &offset_expr, &used_at);
7674 if (breg != 0)
7675 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7676 if (! target_big_endian)

--- 15 unchanged lines hidden (view full) ---

7692 break;
7693
7694 default:
7695 /* FIXME: Check if this is one of the itbl macros, since they
7696 are added dynamically. */
7697 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7698 break;
7699 }
7683 break;
7684
7685 case M_USH_A:
7686 used_at = 1;
7687 load_address (AT, &offset_expr, &used_at);
7688 if (breg != 0)
7689 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", AT, AT, breg);
7690 if (! target_big_endian)

--- 15 unchanged lines hidden (view full) ---

7706 break;
7707
7708 default:
7709 /* FIXME: Check if this is one of the itbl macros, since they
7710 are added dynamically. */
7711 as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
7712 break;
7713 }
7700 if (mips_opts.noat)
7701 as_warn (_("Macro used $at after \".set noat\""));
7714 if (mips_opts.noat && used_at)
7715 as_bad (_("Macro used $at after \".set noat\""));
7702}
7703
7704/* Implement macros in mips16 mode. */
7705
7706static void
7707mips16_macro (struct mips_cl_insn *ip)
7708{
7709 int mask;
7710 int xreg, yreg, zreg, tmp;
7711 expressionS expr1;
7712 int dbl;
7713 const char *s, *s2, *s3;
7714
7715 mask = ip->insn_mo->mask;
7716
7716}
7717
7718/* Implement macros in mips16 mode. */
7719
7720static void
7721mips16_macro (struct mips_cl_insn *ip)
7722{
7723 int mask;
7724 int xreg, yreg, zreg, tmp;
7725 expressionS expr1;
7726 int dbl;
7727 const char *s, *s2, *s3;
7728
7729 mask = ip->insn_mo->mask;
7730
7717 xreg = (ip->insn_opcode >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
7718 yreg = (ip->insn_opcode >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY;
7719 zreg = (ip->insn_opcode >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
7731 xreg = MIPS16_EXTRACT_OPERAND (RX, *ip);
7732 yreg = MIPS16_EXTRACT_OPERAND (RY, *ip);
7733 zreg = MIPS16_EXTRACT_OPERAND (RZ, *ip);
7720
7721 expr1.X_op = O_constant;
7722 expr1.X_op_symbol = NULL;
7723 expr1.X_add_symbol = NULL;
7724 expr1.X_add_number = 1;
7725
7726 dbl = 0;
7727

--- 7 unchanged lines hidden (view full) ---

7735 case M_DIV_3:
7736 s = "mflo";
7737 goto do_div3;
7738 case M_DREM_3:
7739 dbl = 1;
7740 case M_REM_3:
7741 s = "mfhi";
7742 do_div3:
7734
7735 expr1.X_op = O_constant;
7736 expr1.X_op_symbol = NULL;
7737 expr1.X_add_symbol = NULL;
7738 expr1.X_add_number = 1;
7739
7740 dbl = 0;
7741

--- 7 unchanged lines hidden (view full) ---

7749 case M_DIV_3:
7750 s = "mflo";
7751 goto do_div3;
7752 case M_DREM_3:
7753 dbl = 1;
7754 case M_REM_3:
7755 s = "mfhi";
7756 do_div3:
7743 mips_emit_delays (TRUE);
7744 ++mips_opts.noreorder;
7745 mips_any_noreorder = 1;
7757 start_noreorder ();
7746 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7747 expr1.X_add_number = 2;
7748 macro_build (&expr1, "bnez", "x,p", yreg);
7749 macro_build (NULL, "break", "6", 7);
7750
7751 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7752 since that causes an overflow. We should do that as well,
7753 but I don't see how to do the comparisons without a temporary
7754 register. */
7758 macro_build (NULL, dbl ? "ddiv" : "div", "0,x,y", xreg, yreg);
7759 expr1.X_add_number = 2;
7760 macro_build (&expr1, "bnez", "x,p", yreg);
7761 macro_build (NULL, "break", "6", 7);
7762
7763 /* FIXME: The normal code checks for of -1 / -0x80000000 here,
7764 since that causes an overflow. We should do that as well,
7765 but I don't see how to do the comparisons without a temporary
7766 register. */
7755 --mips_opts.noreorder;
7767 end_noreorder ();
7756 macro_build (NULL, s, "x", zreg);
7757 break;
7758
7759 case M_DIVU_3:
7760 s = "divu";
7761 s2 = "mflo";
7762 goto do_divu3;
7763 case M_REMU_3:
7764 s = "divu";
7765 s2 = "mfhi";
7766 goto do_divu3;
7767 case M_DDIVU_3:
7768 s = "ddivu";
7769 s2 = "mflo";
7770 goto do_divu3;
7771 case M_DREMU_3:
7772 s = "ddivu";
7773 s2 = "mfhi";
7774 do_divu3:
7768 macro_build (NULL, s, "x", zreg);
7769 break;
7770
7771 case M_DIVU_3:
7772 s = "divu";
7773 s2 = "mflo";
7774 goto do_divu3;
7775 case M_REMU_3:
7776 s = "divu";
7777 s2 = "mfhi";
7778 goto do_divu3;
7779 case M_DDIVU_3:
7780 s = "ddivu";
7781 s2 = "mflo";
7782 goto do_divu3;
7783 case M_DREMU_3:
7784 s = "ddivu";
7785 s2 = "mfhi";
7786 do_divu3:
7775 mips_emit_delays (TRUE);
7776 ++mips_opts.noreorder;
7777 mips_any_noreorder = 1;
7787 start_noreorder ();
7778 macro_build (NULL, s, "0,x,y", xreg, yreg);
7779 expr1.X_add_number = 2;
7780 macro_build (&expr1, "bnez", "x,p", yreg);
7781 macro_build (NULL, "break", "6", 7);
7788 macro_build (NULL, s, "0,x,y", xreg, yreg);
7789 expr1.X_add_number = 2;
7790 macro_build (&expr1, "bnez", "x,p", yreg);
7791 macro_build (NULL, "break", "6", 7);
7782 --mips_opts.noreorder;
7792 end_noreorder ();
7783 macro_build (NULL, s2, "x", zreg);
7784 break;
7785
7786 case M_DMUL:
7787 dbl = 1;
7788 case M_MUL:
7789 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7790 macro_build (NULL, "mflo", "x", zreg);
7793 macro_build (NULL, s2, "x", zreg);
7794 break;
7795
7796 case M_DMUL:
7797 dbl = 1;
7798 case M_MUL:
7799 macro_build (NULL, dbl ? "dmultu" : "multu", "x,y", xreg, yreg);
7800 macro_build (NULL, "mflo", "x", zreg);
7791 return;
7801 break;
7792
7793 case M_DSUBU_I:
7794 dbl = 1;
7795 goto do_subu;
7796 case M_SUBU_I:
7797 do_subu:
7798 if (imm_expr.X_op != O_constant)
7799 as_bad (_("Unsupported large constant"));

--- 154 unchanged lines hidden (view full) ---

7954 }
7955#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7956 while (*p)
7957 switch (c = *p++)
7958 {
7959 case ',': break;
7960 case '(': break;
7961 case ')': break;
7802
7803 case M_DSUBU_I:
7804 dbl = 1;
7805 goto do_subu;
7806 case M_SUBU_I:
7807 do_subu:
7808 if (imm_expr.X_op != O_constant)
7809 as_bad (_("Unsupported large constant"));

--- 154 unchanged lines hidden (view full) ---

7964 }
7965#define USE_BITS(mask,shift) (used_bits |= ((mask) << (shift)))
7966 while (*p)
7967 switch (c = *p++)
7968 {
7969 case ',': break;
7970 case '(': break;
7971 case ')': break;
7972 case '^': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
7973 case '~': USE_BITS (OP_MASK_BITIND, OP_SH_BITIND); break;
7962 case '+':
7963 switch (c = *p++)
7964 {
7965 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7966 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7967 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7968 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7969 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7970 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7971 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7972 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7973 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7974 case 'I': break;
7974 case '+':
7975 switch (c = *p++)
7976 {
7977 case 'A': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7978 case 'B': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7979 case 'C': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7980 case 'D': USE_BITS (OP_MASK_RD, OP_SH_RD);
7981 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7982 case 'E': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7983 case 'F': USE_BITS (OP_MASK_INSMSB, OP_SH_INSMSB); break;
7984 case 'G': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7985 case 'H': USE_BITS (OP_MASK_EXTMSBD, OP_SH_EXTMSBD); break;
7986 case 'I': break;
7987 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
7988 case 'T': USE_BITS (OP_MASK_RT, OP_SH_RT);
7989 USE_BITS (OP_MASK_SEL, OP_SH_SEL); break;
7975 default:
7976 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7977 c, opc->name, opc->args);
7978 return 0;
7979 }
7980 break;
7981 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7982 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;

--- 37 unchanged lines hidden (view full) ---

8020 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8021 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8022 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8023 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8024 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8025 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8026 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8027 case 'x': break;
7990 default:
7991 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
7992 c, opc->name, opc->args);
7993 return 0;
7994 }
7995 break;
7996 case '<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;
7997 case '>': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break;

--- 37 unchanged lines hidden (view full) ---

8035 case 'q': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8036 case 'r': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8037 case 's': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8038 case 't': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8039 case 'u': USE_BITS (OP_MASK_IMMEDIATE, OP_SH_IMMEDIATE); break;
8040 case 'v': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8041 case 'w': USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8042 case 'x': break;
8043 case 'y': USE_BITS (OP_MASK_CODE2, OP_SH_CODE2); break;
8028 case 'z': break;
8029 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8030 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8031 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8032 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8033 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8034 case '[': break;
8035 case ']': break;
8044 case 'z': break;
8045 case 'P': USE_BITS (OP_MASK_PERFREG, OP_SH_PERFREG); break;
8046 case 'U': USE_BITS (OP_MASK_RD, OP_SH_RD);
8047 USE_BITS (OP_MASK_RT, OP_SH_RT); break;
8048 case 'e': USE_BITS (OP_MASK_VECBYTE, OP_SH_VECBYTE); break;
8049 case '%': USE_BITS (OP_MASK_VECALIGN, OP_SH_VECALIGN); break;
8050 case '[': break;
8051 case ']': break;
8052 case '3': USE_BITS (OP_MASK_SA3, OP_SH_SA3); break;
8053 case '4': USE_BITS (OP_MASK_SA4, OP_SH_SA4); break;
8054 case '5': USE_BITS (OP_MASK_IMM8, OP_SH_IMM8); break;
8055 case '6': USE_BITS (OP_MASK_RS, OP_SH_RS); break;
8056 case '7': USE_BITS (OP_MASK_DSPACC, OP_SH_DSPACC); break;
8057 case '8': USE_BITS (OP_MASK_WRDSP, OP_SH_WRDSP); break;
8058 case '9': USE_BITS (OP_MASK_DSPACC_S, OP_SH_DSPACC_S);break;
8059 case '0': USE_BITS (OP_MASK_DSPSFT, OP_SH_DSPSFT); break;
8060 case '\'': USE_BITS (OP_MASK_RDDSP, OP_SH_RDDSP); break;
8061 case ':': USE_BITS (OP_MASK_DSPSFT_7, OP_SH_DSPSFT_7);break;
8062 case '@': USE_BITS (OP_MASK_IMM10, OP_SH_IMM10); break;
8063 case '!': USE_BITS (OP_MASK_MT_U, OP_SH_MT_U); break;
8064 case '$': USE_BITS (OP_MASK_MT_H, OP_SH_MT_H); break;
8065 case '*': USE_BITS (OP_MASK_MTACC_T, OP_SH_MTACC_T); break;
8066 case '&': USE_BITS (OP_MASK_MTACC_D, OP_SH_MTACC_D); break;
8067 case 'g': USE_BITS (OP_MASK_RD, OP_SH_RD); break;
8036 default:
8037 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8038 c, opc->name, opc->args);
8039 return 0;
8040 }
8041#undef USE_BITS
8042 if (used_bits != 0xffffffff)
8043 {

--- 18 unchanged lines hidden (view full) ---

8062 struct mips_opcode *insn;
8063 char *argsStart;
8064 unsigned int regno;
8065 unsigned int lastregno = 0;
8066 unsigned int lastpos = 0;
8067 unsigned int limlo, limhi;
8068 char *s_reset;
8069 char save_c = 0;
8068 default:
8069 as_bad (_("internal: bad mips opcode (unknown operand type `%c'): %s %s"),
8070 c, opc->name, opc->args);
8071 return 0;
8072 }
8073#undef USE_BITS
8074 if (used_bits != 0xffffffff)
8075 {

--- 18 unchanged lines hidden (view full) ---

8094 struct mips_opcode *insn;
8095 char *argsStart;
8096 unsigned int regno;
8097 unsigned int lastregno = 0;
8098 unsigned int lastpos = 0;
8099 unsigned int limlo, limhi;
8100 char *s_reset;
8101 char save_c = 0;
8102 offsetT min_range, max_range;
8070
8071 insn_error = NULL;
8072
8073 /* If the instruction contains a '.', we first try to match an instruction
8074 including the '.'. Then we try again without the '.'. */
8075 insn = NULL;
8076 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8077 continue;

--- 46 unchanged lines hidden (view full) ---

8124 bfd_boolean ok;
8125
8126 assert (strcmp (insn->name, str) == 0);
8127
8128 if (OPCODE_IS_MEMBER (insn,
8129 (mips_opts.isa
8130 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8131 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8103
8104 insn_error = NULL;
8105
8106 /* If the instruction contains a '.', we first try to match an instruction
8107 including the '.'. Then we try again without the '.'. */
8108 insn = NULL;
8109 for (s = str; *s != '\0' && !ISSPACE (*s); ++s)
8110 continue;

--- 46 unchanged lines hidden (view full) ---

8157 bfd_boolean ok;
8158
8159 assert (strcmp (insn->name, str) == 0);
8160
8161 if (OPCODE_IS_MEMBER (insn,
8162 (mips_opts.isa
8163 | (file_ase_mips16 ? INSN_MIPS16 : 0)
8164 | (mips_opts.ase_mdmx ? INSN_MDMX : 0)
8165 | (mips_opts.ase_dsp ? INSN_DSP : 0)
8166 | (mips_opts.ase_mt ? INSN_MT : 0)
8132 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8133 mips_opts.arch))
8134 ok = TRUE;
8135 else
8136 ok = FALSE;
8137
8138 if (insn->pinfo != INSN_MACRO)
8139 {
8140 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8141 ok = FALSE;
8167 | (mips_opts.ase_mips3d ? INSN_MIPS3D : 0)),
8168 mips_opts.arch))
8169 ok = TRUE;
8170 else
8171 ok = FALSE;
8172
8173 if (insn->pinfo != INSN_MACRO)
8174 {
8175 if (mips_opts.arch == CPU_R4650 && (insn->pinfo & FP_D) != 0)
8176 ok = FALSE;
8177
8178 if (mips_opts.arch == CPU_OCTEON
8179 && octeon_error_on_unsupported
8180 && ((insn->pinfo & FP_D) != 0
8181 || (insn->pinfo & FP_S) !=0
8182 || strcmp (insn->name, "prefx") == 0))
8183 {
8184 insn_error = "opcode not implemented in Octeon";
8185 return;
8186 }
8187
8188 if (mips_opts.arch == CPU_OCTEON
8189 && octeon_error_on_unsupported
8190 && (strcmp (insn->name, "swc2") == 0
8191 || strcmp (insn->name, "lwc2") == 0
8192 || strcmp (insn->name, "sdc2") == 0
8193 || strcmp (insn->name, "ldc2") == 0
8194 || strcmp (insn->name, "bc2f") == 0
8195 || strcmp (insn->name, "bc2t") == 0
8196 || strcmp (insn->name, "mfc2") == 0
8197 || strcmp (insn->name, "mtc2") == 0
8198 || strcmp (insn->name, "ctc2") == 0
8199 || strcmp (insn->name, "cfc2") == 0
8200 || strcmp (insn->name, "mfhc2") == 0
8201 || strcmp (insn->name, "mthc2") == 0))
8202 {
8203 insn_error = "opcode not implemented in Octeon";
8204 return;
8205 }
8206
8207 /* Issue a warning message for Octeon unaligned load/store
8208 instructions used when octeon_use_unalign is not set. */
8209 if (mips_opts.arch == CPU_OCTEON && ! octeon_use_unalign
8210 && (strcmp (insn->name, "ulw") == 0
8211 || strcmp (insn->name, "uld") == 0
8212 || strcmp (insn->name, "usw") == 0
8213 || strcmp (insn->name, "usd") == 0))
8214 {
8215 static char buf[120];
8216 sprintf (buf, _("Octeon specific unaligned load/store instructions are not allowed with -mno-octeon-useun"));
8217 insn_error = buf;
8218 return;
8219 }
8220
8221 /* Issue a warning message for MIPS unaligned load/store
8222 instructions used when octeon_use_unalign is set. */
8223 if (mips_opts.arch == CPU_OCTEON && octeon_use_unalign
8224 && (strcmp (insn->name, "lwl") == 0
8225 || strcmp (insn->name, "lwr") == 0
8226 || strcmp (insn->name, "ldl") == 0
8227 || strcmp (insn->name, "ldr") == 0
8228 || strcmp (insn->name, "sdl") == 0
8229 || strcmp (insn->name, "sdr") == 0
8230 || strcmp (insn->name, "swr") == 0
8231 || strcmp (insn->name, "swl") == 0))
8232 {
8233 static char buf[100];
8234 sprintf (buf, _("Unaligned load/store instructions are not allowed with -mocteon-useun"));
8235 insn_error = buf;
8236 return;
8237 }
8142 }
8143
8238 }
8239
8240 /* Octeon has its own version of dmtc2/dmfc2 instructions, error on
8241 other formats. */
8242 if (mips_opts.arch == CPU_OCTEON
8243 && (strcmp (insn->name, "dmtc2") == 0
8244 || strcmp (insn->name, "dmfc2") == 0)
8245 && (insn->membership & INSN_OCTEON) != INSN_OCTEON)
8246 {
8247 static char buf[100];
8248 sprintf (buf,
8249 _("opcode not supported in %s"),
8250 mips_cpu_info_from_arch (mips_opts.arch)->name);
8251 insn_error = buf;
8252 ok = FALSE;
8253 }
8254
8144 if (! ok)
8145 {
8146 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8147 && strcmp (insn->name, insn[1].name) == 0)
8148 {
8149 ++insn;
8150 continue;
8151 }

--- 9 unchanged lines hidden (view full) ---

8161 insn_error = buf;
8162 }
8163 if (save_c)
8164 *(--s) = save_c;
8165 return;
8166 }
8167 }
8168
8255 if (! ok)
8256 {
8257 if (insn + 1 < &mips_opcodes[NUMOPCODES]
8258 && strcmp (insn->name, insn[1].name) == 0)
8259 {
8260 ++insn;
8261 continue;
8262 }

--- 9 unchanged lines hidden (view full) ---

8272 insn_error = buf;
8273 }
8274 if (save_c)
8275 *(--s) = save_c;
8276 return;
8277 }
8278 }
8279
8169 ip->insn_mo = insn;
8170 ip->insn_opcode = insn->match;
8280 create_insn (ip, insn);
8171 insn_error = NULL;
8172 for (args = insn->args;; ++args)
8173 {
8174 int is_mdmx;
8175
8176 s += strspn (s, " \t");
8177 is_mdmx = 0;
8178 switch (*args)
8179 {
8180 case '\0': /* end of args */
8181 if (*s == '\0')
8182 return;
8183 break;
8184
8281 insn_error = NULL;
8282 for (args = insn->args;; ++args)
8283 {
8284 int is_mdmx;
8285
8286 s += strspn (s, " \t");
8287 is_mdmx = 0;
8288 switch (*args)
8289 {
8290 case '\0': /* end of args */
8291 if (*s == '\0')
8292 return;
8293 break;
8294
8295 case '3': /* dsp 3-bit unsigned immediate in bit 21 */
8296 my_getExpression (&imm_expr, s);
8297 check_absolute_expr (ip, &imm_expr);
8298 if (imm_expr.X_add_number & ~OP_MASK_SA3)
8299 {
8300 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8301 OP_MASK_SA3, (unsigned long) imm_expr.X_add_number);
8302 imm_expr.X_add_number &= OP_MASK_SA3;
8303 }
8304 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA3;
8305 imm_expr.X_op = O_absent;
8306 s = expr_end;
8307 continue;
8308
8309 case '4': /* dsp 4-bit unsigned immediate in bit 21 */
8310 my_getExpression (&imm_expr, s);
8311 check_absolute_expr (ip, &imm_expr);
8312 if (imm_expr.X_add_number & ~OP_MASK_SA4)
8313 {
8314 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8315 OP_MASK_SA4, (unsigned long) imm_expr.X_add_number);
8316 imm_expr.X_add_number &= OP_MASK_SA4;
8317 }
8318 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SA4;
8319 imm_expr.X_op = O_absent;
8320 s = expr_end;
8321 continue;
8322
8323 case '5': /* dsp 8-bit unsigned immediate in bit 16 */
8324 my_getExpression (&imm_expr, s);
8325 check_absolute_expr (ip, &imm_expr);
8326 if (imm_expr.X_add_number & ~OP_MASK_IMM8)
8327 {
8328 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8329 OP_MASK_IMM8, (unsigned long) imm_expr.X_add_number);
8330 imm_expr.X_add_number &= OP_MASK_IMM8;
8331 }
8332 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_IMM8;
8333 imm_expr.X_op = O_absent;
8334 s = expr_end;
8335 continue;
8336
8337 case '6': /* dsp 5-bit unsigned immediate in bit 21 */
8338 my_getExpression (&imm_expr, s);
8339 check_absolute_expr (ip, &imm_expr);
8340 if (imm_expr.X_add_number & ~OP_MASK_RS)
8341 {
8342 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8343 OP_MASK_RS, (unsigned long) imm_expr.X_add_number);
8344 imm_expr.X_add_number &= OP_MASK_RS;
8345 }
8346 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RS;
8347 imm_expr.X_op = O_absent;
8348 s = expr_end;
8349 continue;
8350
8351 case '7': /* four dsp accumulators in bits 11,12 */
8352 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8353 s[3] >= '0' && s[3] <= '3')
8354 {
8355 regno = s[3] - '0';
8356 s += 4;
8357 ip->insn_opcode |= regno << OP_SH_DSPACC;
8358 continue;
8359 }
8360 else
8361 as_bad (_("Invalid dsp acc register"));
8362 break;
8363
8364 case '8': /* dsp 6-bit unsigned immediate in bit 11 */
8365 my_getExpression (&imm_expr, s);
8366 check_absolute_expr (ip, &imm_expr);
8367 if (imm_expr.X_add_number & ~OP_MASK_WRDSP)
8368 {
8369 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8370 OP_MASK_WRDSP,
8371 (unsigned long) imm_expr.X_add_number);
8372 imm_expr.X_add_number &= OP_MASK_WRDSP;
8373 }
8374 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_WRDSP;
8375 imm_expr.X_op = O_absent;
8376 s = expr_end;
8377 continue;
8378
8379 case '9': /* four dsp accumulators in bits 21,22 */
8380 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8381 s[3] >= '0' && s[3] <= '3')
8382 {
8383 regno = s[3] - '0';
8384 s += 4;
8385 ip->insn_opcode |= regno << OP_SH_DSPACC_S;
8386 continue;
8387 }
8388 else
8389 as_bad (_("Invalid dsp acc register"));
8390 break;
8391
8392 case '0': /* dsp 6-bit signed immediate in bit 20 */
8393 my_getExpression (&imm_expr, s);
8394 check_absolute_expr (ip, &imm_expr);
8395 min_range = -((OP_MASK_DSPSFT + 1) >> 1);
8396 max_range = ((OP_MASK_DSPSFT + 1) >> 1) - 1;
8397 if (imm_expr.X_add_number < min_range ||
8398 imm_expr.X_add_number > max_range)
8399 {
8400 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8401 (long) min_range, (long) max_range,
8402 (long) imm_expr.X_add_number);
8403 }
8404 imm_expr.X_add_number &= OP_MASK_DSPSFT;
8405 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8406 << OP_SH_DSPSFT);
8407 imm_expr.X_op = O_absent;
8408 s = expr_end;
8409 continue;
8410
8411 case '\'': /* dsp 6-bit unsigned immediate in bit 16 */
8412 my_getExpression (&imm_expr, s);
8413 check_absolute_expr (ip, &imm_expr);
8414 if (imm_expr.X_add_number & ~OP_MASK_RDDSP)
8415 {
8416 as_warn (_("DSP immediate not in range 0..%d (%lu)"),
8417 OP_MASK_RDDSP,
8418 (unsigned long) imm_expr.X_add_number);
8419 imm_expr.X_add_number &= OP_MASK_RDDSP;
8420 }
8421 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_RDDSP;
8422 imm_expr.X_op = O_absent;
8423 s = expr_end;
8424 continue;
8425
8426 case ':': /* dsp 7-bit signed immediate in bit 19 */
8427 my_getExpression (&imm_expr, s);
8428 check_absolute_expr (ip, &imm_expr);
8429 min_range = -((OP_MASK_DSPSFT_7 + 1) >> 1);
8430 max_range = ((OP_MASK_DSPSFT_7 + 1) >> 1) - 1;
8431 if (imm_expr.X_add_number < min_range ||
8432 imm_expr.X_add_number > max_range)
8433 {
8434 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8435 (long) min_range, (long) max_range,
8436 (long) imm_expr.X_add_number);
8437 }
8438 imm_expr.X_add_number &= OP_MASK_DSPSFT_7;
8439 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8440 << OP_SH_DSPSFT_7);
8441 imm_expr.X_op = O_absent;
8442 s = expr_end;
8443 continue;
8444
8445 case '@': /* dsp 10-bit signed immediate in bit 16 */
8446 my_getExpression (&imm_expr, s);
8447 check_absolute_expr (ip, &imm_expr);
8448 min_range = -((OP_MASK_IMM10 + 1) >> 1);
8449 max_range = ((OP_MASK_IMM10 + 1) >> 1) - 1;
8450 if (imm_expr.X_add_number < min_range ||
8451 imm_expr.X_add_number > max_range)
8452 {
8453 as_warn (_("DSP immediate not in range %ld..%ld (%ld)"),
8454 (long) min_range, (long) max_range,
8455 (long) imm_expr.X_add_number);
8456 }
8457 imm_expr.X_add_number &= OP_MASK_IMM10;
8458 ip->insn_opcode |= ((unsigned long) imm_expr.X_add_number
8459 << OP_SH_IMM10);
8460 imm_expr.X_op = O_absent;
8461 s = expr_end;
8462 continue;
8463
8464 case '!': /* mt 1-bit unsigned immediate in bit 5 */
8465 my_getExpression (&imm_expr, s);
8466 check_absolute_expr (ip, &imm_expr);
8467 if (imm_expr.X_add_number & ~OP_MASK_MT_U)
8468 {
8469 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8470 OP_MASK_MT_U, (unsigned long) imm_expr.X_add_number);
8471 imm_expr.X_add_number &= OP_MASK_MT_U;
8472 }
8473 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_U;
8474 imm_expr.X_op = O_absent;
8475 s = expr_end;
8476 continue;
8477
8478 case '$': /* mt 1-bit unsigned immediate in bit 4 */
8479 my_getExpression (&imm_expr, s);
8480 check_absolute_expr (ip, &imm_expr);
8481 if (imm_expr.X_add_number & ~OP_MASK_MT_H)
8482 {
8483 as_warn (_("MT immediate not in range 0..%d (%lu)"),
8484 OP_MASK_MT_H, (unsigned long) imm_expr.X_add_number);
8485 imm_expr.X_add_number &= OP_MASK_MT_H;
8486 }
8487 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_MT_H;
8488 imm_expr.X_op = O_absent;
8489 s = expr_end;
8490 continue;
8491
8492 case '*': /* four dsp accumulators in bits 18,19 */
8493 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8494 s[3] >= '0' && s[3] <= '3')
8495 {
8496 regno = s[3] - '0';
8497 s += 4;
8498 ip->insn_opcode |= regno << OP_SH_MTACC_T;
8499 continue;
8500 }
8501 else
8502 as_bad (_("Invalid dsp/smartmips acc register"));
8503 break;
8504
8505 case '&': /* four dsp accumulators in bits 13,14 */
8506 if (s[0] == '$' && s[1] == 'a' && s[2] == 'c' &&
8507 s[3] >= '0' && s[3] <= '3')
8508 {
8509 regno = s[3] - '0';
8510 s += 4;
8511 ip->insn_opcode |= regno << OP_SH_MTACC_D;
8512 continue;
8513 }
8514 else
8515 as_bad (_("Invalid dsp/smartmips acc register"));
8516 break;
8517
8185 case ',':
8186 if (*s++ == *args)
8187 continue;
8188 s--;
8189 switch (*++args)
8190 {
8191 case 'r':
8192 case 'v':
8518 case ',':
8519 if (*s++ == *args)
8520 continue;
8521 s--;
8522 switch (*++args)
8523 {
8524 case 'r':
8525 case 'v':
8193 ip->insn_opcode |= lastregno << OP_SH_RS;
8526 INSERT_OPERAND (RS, *ip, lastregno);
8194 continue;
8195
8196 case 'w':
8527 continue;
8528
8529 case 'w':
8197 ip->insn_opcode |= lastregno << OP_SH_RT;
8530 INSERT_OPERAND (RT, *ip, lastregno);
8198 continue;
8199
8200 case 'W':
8531 continue;
8532
8533 case 'W':
8201 ip->insn_opcode |= lastregno << OP_SH_FT;
8534 INSERT_OPERAND (FT, *ip, lastregno);
8202 continue;
8203
8204 case 'V':
8535 continue;
8536
8537 case 'V':
8205 ip->insn_opcode |= lastregno << OP_SH_FS;
8538 INSERT_OPERAND (FS, *ip, lastregno);
8206 continue;
8207 }
8208 break;
8209
8210 case '(':
8211 /* Handle optional base register.
8212 Either the base register is omitted or
8213 we must have a left paren. */

--- 28 unchanged lines hidden (view full) ---

8242 if ((unsigned long) imm_expr.X_add_number < limlo
8243 || (unsigned long) imm_expr.X_add_number > limhi)
8244 {
8245 as_bad (_("Improper position (%lu)"),
8246 (unsigned long) imm_expr.X_add_number);
8247 imm_expr.X_add_number = limlo;
8248 }
8249 lastpos = imm_expr.X_add_number;
8539 continue;
8540 }
8541 break;
8542
8543 case '(':
8544 /* Handle optional base register.
8545 Either the base register is omitted or
8546 we must have a left paren. */

--- 28 unchanged lines hidden (view full) ---

8575 if ((unsigned long) imm_expr.X_add_number < limlo
8576 || (unsigned long) imm_expr.X_add_number > limhi)
8577 {
8578 as_bad (_("Improper position (%lu)"),
8579 (unsigned long) imm_expr.X_add_number);
8580 imm_expr.X_add_number = limlo;
8581 }
8582 lastpos = imm_expr.X_add_number;
8250 ip->insn_opcode |= (imm_expr.X_add_number
8251 & OP_MASK_SHAMT) << OP_SH_SHAMT;
8583 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8252 imm_expr.X_op = O_absent;
8253 s = expr_end;
8254 continue;
8255
8256 case 'B': /* ins size, becomes MSB. */
8257 limlo = 1;
8258 limhi = 32;
8259 goto do_msb;

--- 14 unchanged lines hidden (view full) ---

8274 || ((unsigned long) imm_expr.X_add_number
8275 + lastpos) > limhi)
8276 {
8277 as_bad (_("Improper insert size (%lu, position %lu)"),
8278 (unsigned long) imm_expr.X_add_number,
8279 (unsigned long) lastpos);
8280 imm_expr.X_add_number = limlo - lastpos;
8281 }
8584 imm_expr.X_op = O_absent;
8585 s = expr_end;
8586 continue;
8587
8588 case 'B': /* ins size, becomes MSB. */
8589 limlo = 1;
8590 limhi = 32;
8591 goto do_msb;

--- 14 unchanged lines hidden (view full) ---

8606 || ((unsigned long) imm_expr.X_add_number
8607 + lastpos) > limhi)
8608 {
8609 as_bad (_("Improper insert size (%lu, position %lu)"),
8610 (unsigned long) imm_expr.X_add_number,
8611 (unsigned long) lastpos);
8612 imm_expr.X_add_number = limlo - lastpos;
8613 }
8282 ip->insn_opcode |= ((lastpos + imm_expr.X_add_number - 1)
8283 & OP_MASK_INSMSB) << OP_SH_INSMSB;
8614 INSERT_OPERAND (INSMSB, *ip,
8615 lastpos + imm_expr.X_add_number - 1);
8284 imm_expr.X_op = O_absent;
8285 s = expr_end;
8286 continue;
8287
8288 case 'C': /* ext size, becomes MSBD. */
8289 limlo = 1;
8290 limhi = 32;
8291 goto do_msbd;

--- 18 unchanged lines hidden (view full) ---

8310 || ((unsigned long) imm_expr.X_add_number
8311 + lastpos) > limhi)
8312 {
8313 as_bad (_("Improper extract size (%lu, position %lu)"),
8314 (unsigned long) imm_expr.X_add_number,
8315 (unsigned long) lastpos);
8316 imm_expr.X_add_number = limlo - lastpos;
8317 }
8616 imm_expr.X_op = O_absent;
8617 s = expr_end;
8618 continue;
8619
8620 case 'C': /* ext size, becomes MSBD. */
8621 limlo = 1;
8622 limhi = 32;
8623 goto do_msbd;

--- 18 unchanged lines hidden (view full) ---

8642 || ((unsigned long) imm_expr.X_add_number
8643 + lastpos) > limhi)
8644 {
8645 as_bad (_("Improper extract size (%lu, position %lu)"),
8646 (unsigned long) imm_expr.X_add_number,
8647 (unsigned long) lastpos);
8648 imm_expr.X_add_number = limlo - lastpos;
8649 }
8318 ip->insn_opcode |= ((imm_expr.X_add_number - 1)
8319 & OP_MASK_EXTMSBD) << OP_SH_EXTMSBD;
8650 INSERT_OPERAND (EXTMSBD, *ip, imm_expr.X_add_number - 1);
8320 imm_expr.X_op = O_absent;
8321 s = expr_end;
8322 continue;
8323
8324 case 'D':
8325 /* +D is for disassembly only; never match. */
8326 break;
8327
8328 case 'I':
8329 /* "+I" is like "I", except that imm2_expr is used. */
8330 my_getExpression (&imm2_expr, s);
8331 if (imm2_expr.X_op != O_big
8332 && imm2_expr.X_op != O_constant)
8333 insn_error = _("absolute expression required");
8651 imm_expr.X_op = O_absent;
8652 s = expr_end;
8653 continue;
8654
8655 case 'D':
8656 /* +D is for disassembly only; never match. */
8657 break;
8658
8659 case 'I':
8660 /* "+I" is like "I", except that imm2_expr is used. */
8661 my_getExpression (&imm2_expr, s);
8662 if (imm2_expr.X_op != O_big
8663 && imm2_expr.X_op != O_constant)
8664 insn_error = _("absolute expression required");
8334 normalize_constant_expr (&imm2_expr);
8665 if (HAVE_32BIT_GPRS)
8666 normalize_constant_expr (&imm2_expr);
8335 s = expr_end;
8336 continue;
8337
8667 s = expr_end;
8668 continue;
8669
8670 case 'T': /* Coprocessor register */
8671 /* +T is for disassembly only; never match. */
8672 break;
8673
8674 case 't': /* Coprocessor register number */
8675 if (s[0] == '$' && ISDIGIT (s[1]))
8676 {
8677 ++s;
8678 regno = 0;
8679 do
8680 {
8681 regno *= 10;
8682 regno += *s - '0';
8683 ++s;
8684 }
8685 while (ISDIGIT (*s));
8686 if (regno > 31)
8687 as_bad (_("Invalid register number (%d)"), regno);
8688 else
8689 {
8690 ip->insn_opcode |= regno << OP_SH_RT;
8691 continue;
8692 }
8693 }
8694 else
8695 as_bad (_("Invalid coprocessor 0 register number"));
8696 break;
8697
8338 default:
8339 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8340 *args, insn->name, insn->args);
8341 /* Further processing is fruitless. */
8342 return;
8343 }
8344 break;
8345
8346 case '<': /* must be at least one digit */
8347 /*
8348 * According to the manual, if the shift amount is greater
8349 * than 31 or less than 0, then the shift amount should be
8350 * mod 32. In reality the mips assembler issues an error.
8351 * We issue a warning and mask out all but the low 5 bits.
8352 */
8353 my_getExpression (&imm_expr, s);
8354 check_absolute_expr (ip, &imm_expr);
8355 if ((unsigned long) imm_expr.X_add_number > 31)
8698 default:
8699 as_bad (_("internal: bad mips opcode (unknown extension operand type `+%c'): %s %s"),
8700 *args, insn->name, insn->args);
8701 /* Further processing is fruitless. */
8702 return;
8703 }
8704 break;
8705
8706 case '<': /* must be at least one digit */
8707 /*
8708 * According to the manual, if the shift amount is greater
8709 * than 31 or less than 0, then the shift amount should be
8710 * mod 32. In reality the mips assembler issues an error.
8711 * We issue a warning and mask out all but the low 5 bits.
8712 */
8713 my_getExpression (&imm_expr, s);
8714 check_absolute_expr (ip, &imm_expr);
8715 if ((unsigned long) imm_expr.X_add_number > 31)
8356 {
8357 as_warn (_("Improper shift amount (%lu)"),
8358 (unsigned long) imm_expr.X_add_number);
8359 imm_expr.X_add_number &= OP_MASK_SHAMT;
8360 }
8361 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_SHAMT;
8716 as_warn (_("Improper shift amount (%lu)"),
8717 (unsigned long) imm_expr.X_add_number);
8718 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number);
8362 imm_expr.X_op = O_absent;
8363 s = expr_end;
8364 continue;
8365
8366 case '>': /* shift amount minus 32 */
8367 my_getExpression (&imm_expr, s);
8368 check_absolute_expr (ip, &imm_expr);
8369 if ((unsigned long) imm_expr.X_add_number < 32
8370 || (unsigned long) imm_expr.X_add_number > 63)
8371 break;
8719 imm_expr.X_op = O_absent;
8720 s = expr_end;
8721 continue;
8722
8723 case '>': /* shift amount minus 32 */
8724 my_getExpression (&imm_expr, s);
8725 check_absolute_expr (ip, &imm_expr);
8726 if ((unsigned long) imm_expr.X_add_number < 32
8727 || (unsigned long) imm_expr.X_add_number > 63)
8728 break;
8372 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_SHAMT;
8729 INSERT_OPERAND (SHAMT, *ip, imm_expr.X_add_number - 32);
8373 imm_expr.X_op = O_absent;
8374 s = expr_end;
8375 continue;
8376
8730 imm_expr.X_op = O_absent;
8731 s = expr_end;
8732 continue;
8733
8377 case 'k': /* cache code */
8378 case 'h': /* prefx code */
8734 case '^': /* must be at least one digit */
8735 /* Decode 5-bits of bbit0/1's bit index amount. If the value is
8736 greater than 31, issue a warning and mask out all but the low
8737 5 bits. */
8379 my_getExpression (&imm_expr, s);
8380 check_absolute_expr (ip, &imm_expr);
8381 if ((unsigned long) imm_expr.X_add_number > 31)
8382 {
8738 my_getExpression (&imm_expr, s);
8739 check_absolute_expr (ip, &imm_expr);
8740 if ((unsigned long) imm_expr.X_add_number > 31)
8741 {
8383 as_warn (_("Invalid value for `%s' (%lu)"),
8384 ip->insn_mo->name,
8742 as_warn (_("Improper bit index amount (%lu)"),
8385 (unsigned long) imm_expr.X_add_number);
8743 (unsigned long) imm_expr.X_add_number);
8386 imm_expr.X_add_number &= 0x1f;
8744 imm_expr.X_add_number &= OP_MASK_BITIND;
8387 }
8745 }
8746 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_BITIND;
8747 imm_expr.X_op = O_absent;
8748 s = expr_end;
8749 continue;
8750
8751 case '~': /* bit index minus 32 */
8752 my_getExpression (&imm_expr, s);
8753 check_absolute_expr (ip, &imm_expr);
8754 if ((unsigned long) imm_expr.X_add_number < 32
8755 || (unsigned long) imm_expr.X_add_number > 63)
8756 break;
8757 ip->insn_opcode |= (imm_expr.X_add_number - 32) << OP_SH_BITIND;
8758 imm_expr.X_op = O_absent;
8759 s = expr_end;
8760 continue;
8761
8762 case 'k': /* cache code */
8763 case 'h': /* prefx code */
8764 my_getExpression (&imm_expr, s);
8765 check_absolute_expr (ip, &imm_expr);
8766 if ((unsigned long) imm_expr.X_add_number > 31)
8767 as_warn (_("Invalid value for `%s' (%lu)"),
8768 ip->insn_mo->name,
8769 (unsigned long) imm_expr.X_add_number);
8388 if (*args == 'k')
8770 if (*args == 'k')
8389 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CACHE;
8771 INSERT_OPERAND (CACHE, *ip, imm_expr.X_add_number);
8390 else
8772 else
8391 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_PREFX;
8773 INSERT_OPERAND (PREFX, *ip, imm_expr.X_add_number);
8392 imm_expr.X_op = O_absent;
8393 s = expr_end;
8394 continue;
8395
8396 case 'c': /* break code */
8397 my_getExpression (&imm_expr, s);
8398 check_absolute_expr (ip, &imm_expr);
8399 if ((unsigned long) imm_expr.X_add_number > 1023)
8774 imm_expr.X_op = O_absent;
8775 s = expr_end;
8776 continue;
8777
8778 case 'c': /* break code */
8779 my_getExpression (&imm_expr, s);
8780 check_absolute_expr (ip, &imm_expr);
8781 if ((unsigned long) imm_expr.X_add_number > 1023)
8400 {
8401 as_warn (_("Illegal break code (%lu)"),
8402 (unsigned long) imm_expr.X_add_number);
8403 imm_expr.X_add_number &= OP_MASK_CODE;
8404 }
8405 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE;
8782 as_warn (_("Illegal break code (%lu)"),
8783 (unsigned long) imm_expr.X_add_number);
8784 INSERT_OPERAND (CODE, *ip, imm_expr.X_add_number);
8406 imm_expr.X_op = O_absent;
8407 s = expr_end;
8408 continue;
8409
8410 case 'q': /* lower break code */
8411 my_getExpression (&imm_expr, s);
8412 check_absolute_expr (ip, &imm_expr);
8413 if ((unsigned long) imm_expr.X_add_number > 1023)
8785 imm_expr.X_op = O_absent;
8786 s = expr_end;
8787 continue;
8788
8789 case 'q': /* lower break code */
8790 my_getExpression (&imm_expr, s);
8791 check_absolute_expr (ip, &imm_expr);
8792 if ((unsigned long) imm_expr.X_add_number > 1023)
8793 as_warn (_("Illegal lower break code (%lu)"),
8794 (unsigned long) imm_expr.X_add_number);
8795 INSERT_OPERAND (CODE2, *ip, imm_expr.X_add_number);
8796 imm_expr.X_op = O_absent;
8797 s = expr_end;
8798 continue;
8799
8800 case 'y':
8801 /* Decode 10-bits of seqi/snei's signed constant offset. Issue
8802 a warning message if the value is not within the range. */
8803 my_getExpression (&imm_expr, s);
8804 check_absolute_expr (ip, &imm_expr);
8805 if (((unsigned long) imm_expr.X_add_number + 0x200) > 1023)
8414 {
8806 {
8415 as_warn (_("Illegal lower break code (%lu)"),
8807 as_warn (_("Illegal 10-bit signed constant (%lu)"),
8416 (unsigned long) imm_expr.X_add_number);
8808 (unsigned long) imm_expr.X_add_number);
8417 imm_expr.X_add_number &= OP_MASK_CODE2;
8809 imm_expr.X_add_number &= OP_MASK_CODE2;
8418 }
8810 }
8419 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE2;
8811 ip->insn_opcode |= (imm_expr.X_add_number & OP_MASK_CODE2)
8812 << OP_SH_CODE2;
8420 imm_expr.X_op = O_absent;
8421 s = expr_end;
8422 continue;
8423
8424 case 'B': /* 20-bit syscall/break code. */
8425 my_getExpression (&imm_expr, s);
8426 check_absolute_expr (ip, &imm_expr);
8427 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8428 as_warn (_("Illegal 20-bit code (%lu)"),
8429 (unsigned long) imm_expr.X_add_number);
8813 imm_expr.X_op = O_absent;
8814 s = expr_end;
8815 continue;
8816
8817 case 'B': /* 20-bit syscall/break code. */
8818 my_getExpression (&imm_expr, s);
8819 check_absolute_expr (ip, &imm_expr);
8820 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE20)
8821 as_warn (_("Illegal 20-bit code (%lu)"),
8822 (unsigned long) imm_expr.X_add_number);
8430 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE20;
8823 INSERT_OPERAND (CODE20, *ip, imm_expr.X_add_number);
8431 imm_expr.X_op = O_absent;
8432 s = expr_end;
8433 continue;
8434
8435 case 'C': /* Coprocessor code */
8436 my_getExpression (&imm_expr, s);
8437 check_absolute_expr (ip, &imm_expr);
8438 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))

--- 8 unchanged lines hidden (view full) ---

8447 continue;
8448
8449 case 'J': /* 19-bit wait code. */
8450 my_getExpression (&imm_expr, s);
8451 check_absolute_expr (ip, &imm_expr);
8452 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8453 as_warn (_("Illegal 19-bit code (%lu)"),
8454 (unsigned long) imm_expr.X_add_number);
8824 imm_expr.X_op = O_absent;
8825 s = expr_end;
8826 continue;
8827
8828 case 'C': /* Coprocessor code */
8829 my_getExpression (&imm_expr, s);
8830 check_absolute_expr (ip, &imm_expr);
8831 if ((unsigned long) imm_expr.X_add_number >= (1 << 25))

--- 8 unchanged lines hidden (view full) ---

8840 continue;
8841
8842 case 'J': /* 19-bit wait code. */
8843 my_getExpression (&imm_expr, s);
8844 check_absolute_expr (ip, &imm_expr);
8845 if ((unsigned long) imm_expr.X_add_number > OP_MASK_CODE19)
8846 as_warn (_("Illegal 19-bit code (%lu)"),
8847 (unsigned long) imm_expr.X_add_number);
8455 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_CODE19;
8848 INSERT_OPERAND (CODE19, *ip, imm_expr.X_add_number);
8456 imm_expr.X_op = O_absent;
8457 s = expr_end;
8458 continue;
8459
8460 case 'P': /* Performance register */
8461 my_getExpression (&imm_expr, s);
8462 check_absolute_expr (ip, &imm_expr);
8463 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8849 imm_expr.X_op = O_absent;
8850 s = expr_end;
8851 continue;
8852
8853 case 'P': /* Performance register */
8854 my_getExpression (&imm_expr, s);
8855 check_absolute_expr (ip, &imm_expr);
8856 if (imm_expr.X_add_number != 0 && imm_expr.X_add_number != 1)
8464 {
8465 as_warn (_("Invalid performance register (%lu)"),
8466 (unsigned long) imm_expr.X_add_number);
8467 imm_expr.X_add_number &= OP_MASK_PERFREG;
8468 }
8469 ip->insn_opcode |= (imm_expr.X_add_number << OP_SH_PERFREG);
8857 as_warn (_("Invalid performance register (%lu)"),
8858 (unsigned long) imm_expr.X_add_number);
8859 INSERT_OPERAND (PERFREG, *ip, imm_expr.X_add_number);
8470 imm_expr.X_op = O_absent;
8471 s = expr_end;
8472 continue;
8473
8474 case 'b': /* base register */
8475 case 'd': /* destination register */
8476 case 's': /* source register */
8477 case 't': /* target register */
8478 case 'r': /* both target and source */
8479 case 'v': /* both dest and source */
8480 case 'w': /* both dest and target */
8481 case 'E': /* coprocessor target register */
8482 case 'G': /* coprocessor destination register */
8483 case 'K': /* 'rdhwr' destination register */
8484 case 'x': /* ignore register name */
8485 case 'z': /* must be zero register */
8486 case 'U': /* destination register (clo/clz). */
8860 imm_expr.X_op = O_absent;
8861 s = expr_end;
8862 continue;
8863
8864 case 'b': /* base register */
8865 case 'd': /* destination register */
8866 case 's': /* source register */
8867 case 't': /* target register */
8868 case 'r': /* both target and source */
8869 case 'v': /* both dest and source */
8870 case 'w': /* both dest and target */
8871 case 'E': /* coprocessor target register */
8872 case 'G': /* coprocessor destination register */
8873 case 'K': /* 'rdhwr' destination register */
8874 case 'x': /* ignore register name */
8875 case 'z': /* must be zero register */
8876 case 'U': /* destination register (clo/clz). */
8877 case 'g': /* coprocessor destination register */
8487 s_reset = s;
8488 if (s[0] == '$')
8489 {
8878 s_reset = s;
8879 if (s[0] == '$')
8880 {
8490
8491 if (ISDIGIT (s[1]))
8492 {
8493 ++s;
8494 regno = 0;
8495 do
8496 {
8497 regno *= 10;
8498 regno += *s - '0';

--- 99 unchanged lines hidden (view full) ---

8598 /* Now that we have assembled one operand, we use the args string
8599 * to figure out where it goes in the instruction. */
8600 switch (c)
8601 {
8602 case 'r':
8603 case 's':
8604 case 'v':
8605 case 'b':
8881 if (ISDIGIT (s[1]))
8882 {
8883 ++s;
8884 regno = 0;
8885 do
8886 {
8887 regno *= 10;
8888 regno += *s - '0';

--- 99 unchanged lines hidden (view full) ---

8988 /* Now that we have assembled one operand, we use the args string
8989 * to figure out where it goes in the instruction. */
8990 switch (c)
8991 {
8992 case 'r':
8993 case 's':
8994 case 'v':
8995 case 'b':
8606 ip->insn_opcode |= regno << OP_SH_RS;
8996 INSERT_OPERAND (RS, *ip, regno);
8607 break;
8608 case 'd':
8609 case 'G':
8610 case 'K':
8997 break;
8998 case 'd':
8999 case 'G':
9000 case 'K':
8611 ip->insn_opcode |= regno << OP_SH_RD;
9001 case 'g':
9002 INSERT_OPERAND (RD, *ip, regno);
8612 break;
8613 case 'U':
9003 break;
9004 case 'U':
8614 ip->insn_opcode |= regno << OP_SH_RD;
8615 ip->insn_opcode |= regno << OP_SH_RT;
9005 INSERT_OPERAND (RD, *ip, regno);
9006 INSERT_OPERAND (RT, *ip, regno);
8616 break;
8617 case 'w':
8618 case 't':
8619 case 'E':
9007 break;
9008 case 'w':
9009 case 't':
9010 case 'E':
8620 ip->insn_opcode |= regno << OP_SH_RT;
9011 INSERT_OPERAND (RT, *ip, regno);
8621 break;
8622 case 'x':
8623 /* This case exists because on the r3000 trunc
8624 expands into a macro which requires a gp
8625 register. On the r6000 or r4000 it is
8626 assembled into a single instruction which
8627 ignores the register. Thus the insn version
8628 is MIPS_ISA2 and uses 'x', and the macro

--- 14 unchanged lines hidden (view full) ---

8643 lastregno = regno;
8644 continue;
8645 }
8646 notreg:
8647 switch (*args++)
8648 {
8649 case 'r':
8650 case 'v':
9012 break;
9013 case 'x':
9014 /* This case exists because on the r3000 trunc
9015 expands into a macro which requires a gp
9016 register. On the r6000 or r4000 it is
9017 assembled into a single instruction which
9018 ignores the register. Thus the insn version
9019 is MIPS_ISA2 and uses 'x', and the macro

--- 14 unchanged lines hidden (view full) ---

9034 lastregno = regno;
9035 continue;
9036 }
9037 notreg:
9038 switch (*args++)
9039 {
9040 case 'r':
9041 case 'v':
8651 ip->insn_opcode |= lastregno << OP_SH_RS;
9042 INSERT_OPERAND (RS, *ip, lastregno);
8652 continue;
8653 case 'w':
9043 continue;
9044 case 'w':
8654 ip->insn_opcode |= lastregno << OP_SH_RT;
9045 INSERT_OPERAND (RT, *ip, lastregno);
8655 continue;
8656 }
8657 break;
8658
8659 case 'O': /* MDMX alignment immediate constant. */
8660 my_getExpression (&imm_expr, s);
8661 check_absolute_expr (ip, &imm_expr);
8662 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
9046 continue;
9047 }
9048 break;
9049
9050 case 'O': /* MDMX alignment immediate constant. */
9051 my_getExpression (&imm_expr, s);
9052 check_absolute_expr (ip, &imm_expr);
9053 if ((unsigned long) imm_expr.X_add_number > OP_MASK_ALN)
8663 {
8664 as_warn ("Improper align amount (%ld), using low bits",
8665 (long) imm_expr.X_add_number);
8666 imm_expr.X_add_number &= OP_MASK_ALN;
8667 }
8668 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_ALN;
9054 as_warn ("Improper align amount (%ld), using low bits",
9055 (long) imm_expr.X_add_number);
9056 INSERT_OPERAND (ALN, *ip, imm_expr.X_add_number);
8669 imm_expr.X_op = O_absent;
8670 s = expr_end;
8671 continue;
8672
8673 case 'Q': /* MDMX vector, element sel, or const. */
8674 if (s[0] != '$')
8675 {
8676 /* MDMX Immediate. */
8677 my_getExpression (&imm_expr, s);
8678 check_absolute_expr (ip, &imm_expr);
8679 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
9057 imm_expr.X_op = O_absent;
9058 s = expr_end;
9059 continue;
9060
9061 case 'Q': /* MDMX vector, element sel, or const. */
9062 if (s[0] != '$')
9063 {
9064 /* MDMX Immediate. */
9065 my_getExpression (&imm_expr, s);
9066 check_absolute_expr (ip, &imm_expr);
9067 if ((unsigned long) imm_expr.X_add_number > OP_MASK_FT)
8680 {
8681 as_warn (_("Invalid MDMX Immediate (%ld)"),
8682 (long) imm_expr.X_add_number);
8683 imm_expr.X_add_number &= OP_MASK_FT;
8684 }
8685 imm_expr.X_add_number &= OP_MASK_FT;
9068 as_warn (_("Invalid MDMX Immediate (%ld)"),
9069 (long) imm_expr.X_add_number);
9070 INSERT_OPERAND (FT, *ip, imm_expr.X_add_number);
8686 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8687 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
8688 else
8689 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
9071 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9072 ip->insn_opcode |= MDMX_FMTSEL_IMM_QH << OP_SH_VSEL;
9073 else
9074 ip->insn_opcode |= MDMX_FMTSEL_IMM_OB << OP_SH_VSEL;
8690 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_FT;
8691 imm_expr.X_op = O_absent;
8692 s = expr_end;
8693 continue;
8694 }
8695 /* Not MDMX Immediate. Fall through. */
8696 case 'X': /* MDMX destination register. */
8697 case 'Y': /* MDMX source register. */
8698 case 'Z': /* MDMX target register. */
8699 is_mdmx = 1;
8700 case 'D': /* floating point destination register */
8701 case 'S': /* floating point source register */
8702 case 'T': /* floating point target register */
8703 case 'R': /* floating point source register */
8704 case 'V':
8705 case 'W':
8706 s_reset = s;
9075 imm_expr.X_op = O_absent;
9076 s = expr_end;
9077 continue;
9078 }
9079 /* Not MDMX Immediate. Fall through. */
9080 case 'X': /* MDMX destination register. */
9081 case 'Y': /* MDMX source register. */
9082 case 'Z': /* MDMX target register. */
9083 is_mdmx = 1;
9084 case 'D': /* floating point destination register */
9085 case 'S': /* floating point source register */
9086 case 'T': /* floating point target register */
9087 case 'R': /* floating point source register */
9088 case 'V':
9089 case 'W':
9090 s_reset = s;
9091 if (mips_opts.arch == CPU_OCTEON && octeon_error_on_unsupported)
9092 {
9093 insn_error = "opcode not implemented in Octeon";
9094 return;
9095 }
8707 /* Accept $fN for FP and MDMX register numbers, and in
8708 addition accept $vN for MDMX register numbers. */
8709 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
8710 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
8711 && ISDIGIT (s[2])))
8712 {
8713 s += 2;
8714 regno = 0;

--- 10 unchanged lines hidden (view full) ---

8725
8726 if ((regno & 1) != 0
8727 && HAVE_32BIT_FPRS
8728 && ! (strcmp (str, "mtc1") == 0
8729 || strcmp (str, "mfc1") == 0
8730 || strcmp (str, "lwc1") == 0
8731 || strcmp (str, "swc1") == 0
8732 || strcmp (str, "l.s") == 0
9096 /* Accept $fN for FP and MDMX register numbers, and in
9097 addition accept $vN for MDMX register numbers. */
9098 if ((s[0] == '$' && s[1] == 'f' && ISDIGIT (s[2]))
9099 || (is_mdmx != 0 && s[0] == '$' && s[1] == 'v'
9100 && ISDIGIT (s[2])))
9101 {
9102 s += 2;
9103 regno = 0;

--- 10 unchanged lines hidden (view full) ---

9114
9115 if ((regno & 1) != 0
9116 && HAVE_32BIT_FPRS
9117 && ! (strcmp (str, "mtc1") == 0
9118 || strcmp (str, "mfc1") == 0
9119 || strcmp (str, "lwc1") == 0
9120 || strcmp (str, "swc1") == 0
9121 || strcmp (str, "l.s") == 0
8733 || strcmp (str, "s.s") == 0))
9122 || strcmp (str, "s.s") == 0
9123 || strcmp (str, "mftc1") == 0
9124 || strcmp (str, "mfthc1") == 0
9125 || strcmp (str, "cftc1") == 0
9126 || strcmp (str, "mttc1") == 0
9127 || strcmp (str, "mtthc1") == 0
9128 || strcmp (str, "cttc1") == 0))
8734 as_warn (_("Float register should be even, was %d"),
8735 regno);
8736
8737 c = *args;
8738 if (*s == ' ')
8739 ++s;
8740 if (args[1] != *s)
8741 {
8742 if (c == 'V' || c == 'W')
8743 {
8744 regno = lastregno;
8745 s = s_reset;
8746 ++args;
8747 }
8748 }
8749 switch (c)
8750 {
8751 case 'D':
8752 case 'X':
9129 as_warn (_("Float register should be even, was %d"),
9130 regno);
9131
9132 c = *args;
9133 if (*s == ' ')
9134 ++s;
9135 if (args[1] != *s)
9136 {
9137 if (c == 'V' || c == 'W')
9138 {
9139 regno = lastregno;
9140 s = s_reset;
9141 ++args;
9142 }
9143 }
9144 switch (c)
9145 {
9146 case 'D':
9147 case 'X':
8753 ip->insn_opcode |= regno << OP_SH_FD;
9148 INSERT_OPERAND (FD, *ip, regno);
8754 break;
8755 case 'V':
8756 case 'S':
8757 case 'Y':
9149 break;
9150 case 'V':
9151 case 'S':
9152 case 'Y':
8758 ip->insn_opcode |= regno << OP_SH_FS;
9153 INSERT_OPERAND (FS, *ip, regno);
8759 break;
8760 case 'Q':
8761 /* This is like 'Z', but also needs to fix the MDMX
8762 vector/scalar select bits. Note that the
8763 scalar immediate case is handled above. */
8764 if (*s == '[')
8765 {
8766 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));

--- 4 unchanged lines hidden (view full) ---

8771 s = expr_end;
8772 if (imm_expr.X_add_number > max_el)
8773 as_bad(_("Bad element selector %ld"),
8774 (long) imm_expr.X_add_number);
8775 imm_expr.X_add_number &= max_el;
8776 ip->insn_opcode |= (imm_expr.X_add_number
8777 << (OP_SH_VSEL +
8778 (is_qh ? 2 : 1)));
9154 break;
9155 case 'Q':
9156 /* This is like 'Z', but also needs to fix the MDMX
9157 vector/scalar select bits. Note that the
9158 scalar immediate case is handled above. */
9159 if (*s == '[')
9160 {
9161 int is_qh = (ip->insn_opcode & (1 << OP_SH_VSEL));

--- 4 unchanged lines hidden (view full) ---

9166 s = expr_end;
9167 if (imm_expr.X_add_number > max_el)
9168 as_bad(_("Bad element selector %ld"),
9169 (long) imm_expr.X_add_number);
9170 imm_expr.X_add_number &= max_el;
9171 ip->insn_opcode |= (imm_expr.X_add_number
9172 << (OP_SH_VSEL +
9173 (is_qh ? 2 : 1)));
9174 imm_expr.X_op = O_absent;
8779 if (*s != ']')
8780 as_warn(_("Expecting ']' found '%s'"), s);
8781 else
8782 s++;
8783 }
8784 else
8785 {
8786 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
8787 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
8788 << OP_SH_VSEL);
8789 else
8790 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
8791 OP_SH_VSEL);
8792 }
8793 /* Fall through */
8794 case 'W':
8795 case 'T':
8796 case 'Z':
9175 if (*s != ']')
9176 as_warn(_("Expecting ']' found '%s'"), s);
9177 else
9178 s++;
9179 }
9180 else
9181 {
9182 if (ip->insn_opcode & (OP_MASK_VSEL << OP_SH_VSEL))
9183 ip->insn_opcode |= (MDMX_FMTSEL_VEC_QH
9184 << OP_SH_VSEL);
9185 else
9186 ip->insn_opcode |= (MDMX_FMTSEL_VEC_OB <<
9187 OP_SH_VSEL);
9188 }
9189 /* Fall through */
9190 case 'W':
9191 case 'T':
9192 case 'Z':
8797 ip->insn_opcode |= regno << OP_SH_FT;
9193 INSERT_OPERAND (FT, *ip, regno);
8798 break;
8799 case 'R':
9194 break;
9195 case 'R':
8800 ip->insn_opcode |= regno << OP_SH_FR;
9196 INSERT_OPERAND (FR, *ip, regno);
8801 break;
8802 }
8803 lastregno = regno;
8804 continue;
8805 }
8806
8807 switch (*args++)
8808 {
8809 case 'V':
9197 break;
9198 }
9199 lastregno = regno;
9200 continue;
9201 }
9202
9203 switch (*args++)
9204 {
9205 case 'V':
8810 ip->insn_opcode |= lastregno << OP_SH_FS;
9206 INSERT_OPERAND (FS, *ip, lastregno);
8811 continue;
8812 case 'W':
9207 continue;
9208 case 'W':
8813 ip->insn_opcode |= lastregno << OP_SH_FT;
9209 INSERT_OPERAND (FT, *ip, lastregno);
8814 continue;
8815 }
8816 break;
8817
8818 case 'I':
8819 my_getExpression (&imm_expr, s);
8820 if (imm_expr.X_op != O_big
8821 && imm_expr.X_op != O_constant)
8822 insn_error = _("absolute expression required");
9210 continue;
9211 }
9212 break;
9213
9214 case 'I':
9215 my_getExpression (&imm_expr, s);
9216 if (imm_expr.X_op != O_big
9217 && imm_expr.X_op != O_constant)
9218 insn_error = _("absolute expression required");
8823 normalize_constant_expr (&imm_expr);
9219 if (HAVE_32BIT_GPRS)
9220 normalize_constant_expr (&imm_expr);
8824 s = expr_end;
8825 continue;
8826
8827 case 'A':
8828 my_getExpression (&offset_expr, s);
9221 s = expr_end;
9222 continue;
9223
9224 case 'A':
9225 my_getExpression (&offset_expr, s);
9226 normalize_address_expr (&offset_expr);
8829 *imm_reloc = BFD_RELOC_32;
8830 s = expr_end;
8831 continue;
8832
8833 case 'F':
8834 case 'L':
8835 case 'f':
8836 case 'l':

--- 23 unchanged lines hidden (view full) ---

8860 F -- .rdata
8861 L -- .lit8
8862 f -- immediate value
8863 l -- .lit4
8864
8865 The .lit4 and .lit8 sections are only used if
8866 permitted by the -G argument.
8867
9227 *imm_reloc = BFD_RELOC_32;
9228 s = expr_end;
9229 continue;
9230
9231 case 'F':
9232 case 'L':
9233 case 'f':
9234 case 'l':

--- 23 unchanged lines hidden (view full) ---

9258 F -- .rdata
9259 L -- .lit8
9260 f -- immediate value
9261 l -- .lit4
9262
9263 The .lit4 and .lit8 sections are only used if
9264 permitted by the -G argument.
9265
8868 When generating embedded PIC code, we use the
8869 .lit8 section but not the .lit4 section (we can do
8870 .lit4 inline easily; we need to put .lit8
8871 somewhere in the data segment, and using .lit8
8872 permits the linker to eventually combine identical
8873 .lit8 entries).
8874
8875 The code below needs to know whether the target register
8876 is 32 or 64 bits wide. It relies on the fact 'f' and
8877 'F' are used with GPR-based instructions and 'l' and
8878 'L' are used with FPR-based instructions. */
8879
8880 f64 = *args == 'F' || *args == 'L';
8881 using_gprs = *args == 'F' || *args == 'f';
8882

--- 9 unchanged lines hidden (view full) ---

8892 memset (temp, '\0', sizeof temp);
8893 length = f64 ? 8 : 4;
8894 }
8895
8896 assert (length == (unsigned) (f64 ? 8 : 4));
8897
8898 if (*args == 'f'
8899 || (*args == 'l'
9266 The code below needs to know whether the target register
9267 is 32 or 64 bits wide. It relies on the fact 'f' and
9268 'F' are used with GPR-based instructions and 'l' and
9269 'L' are used with FPR-based instructions. */
9270
9271 f64 = *args == 'F' || *args == 'L';
9272 using_gprs = *args == 'F' || *args == 'f';
9273

--- 9 unchanged lines hidden (view full) ---

9283 memset (temp, '\0', sizeof temp);
9284 length = f64 ? 8 : 4;
9285 }
9286
9287 assert (length == (unsigned) (f64 ? 8 : 4));
9288
9289 if (*args == 'f'
9290 || (*args == 'l'
8900 && (! USE_GLOBAL_POINTER_OPT
8901 || mips_pic == EMBEDDED_PIC
8902 || g_switch_value < 4
9291 && (g_switch_value < 4
8903 || (temp[0] == 0 && temp[1] == 0)
8904 || (temp[2] == 0 && temp[3] == 0))))
8905 {
8906 imm_expr.X_op = O_constant;
8907 if (! target_big_endian)
8908 imm_expr.X_add_number = bfd_getl32 (temp);
8909 else
8910 imm_expr.X_add_number = bfd_getb32 (temp);

--- 70 unchanged lines hidden (view full) ---

8981 /* Switch to the right section. */
8982 seg = now_seg;
8983 subseg = now_subseg;
8984 switch (*args)
8985 {
8986 default: /* unused default case avoids warnings. */
8987 case 'L':
8988 newname = RDATA_SECTION_NAME;
9292 || (temp[0] == 0 && temp[1] == 0)
9293 || (temp[2] == 0 && temp[3] == 0))))
9294 {
9295 imm_expr.X_op = O_constant;
9296 if (! target_big_endian)
9297 imm_expr.X_add_number = bfd_getl32 (temp);
9298 else
9299 imm_expr.X_add_number = bfd_getb32 (temp);

--- 70 unchanged lines hidden (view full) ---

9370 /* Switch to the right section. */
9371 seg = now_seg;
9372 subseg = now_subseg;
9373 switch (*args)
9374 {
9375 default: /* unused default case avoids warnings. */
9376 case 'L':
9377 newname = RDATA_SECTION_NAME;
8989 if ((USE_GLOBAL_POINTER_OPT && g_switch_value >= 8)
8990 || mips_pic == EMBEDDED_PIC)
9378 if (g_switch_value >= 8)
8991 newname = ".lit8";
8992 break;
8993 case 'F':
9379 newname = ".lit8";
9380 break;
9381 case 'F':
8994 if (mips_pic == EMBEDDED_PIC)
8995 newname = ".lit8";
8996 else
8997 newname = RDATA_SECTION_NAME;
9382 newname = RDATA_SECTION_NAME;
8998 break;
8999 case 'l':
9383 break;
9384 case 'l':
9000 assert (!USE_GLOBAL_POINTER_OPT
9001 || g_switch_value >= 4);
9385 assert (g_switch_value >= 4);
9002 newname = ".lit4";
9003 break;
9004 }
9005 new_seg = subseg_new (newname, (subsegT) 0);
9006 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9007 bfd_set_section_flags (stdoutput, new_seg,
9008 (SEC_ALLOC
9009 | SEC_LOAD

--- 139 unchanged lines hidden (view full) ---

9149 as_warn(_("Condition code register should be even for %s, was %d"),
9150 str, regno);
9151 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9152 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9153 && (regno & 3) != 0)
9154 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9155 str, regno);
9156 if (*args == 'N')
9386 newname = ".lit4";
9387 break;
9388 }
9389 new_seg = subseg_new (newname, (subsegT) 0);
9390 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
9391 bfd_set_section_flags (stdoutput, new_seg,
9392 (SEC_ALLOC
9393 | SEC_LOAD

--- 139 unchanged lines hidden (view full) ---

9533 as_warn(_("Condition code register should be even for %s, was %d"),
9534 str, regno);
9535 if ((strcmp(str + strlen(str) - 5, "any4f") == 0
9536 || strcmp(str + strlen(str) - 5, "any4t") == 0)
9537 && (regno & 3) != 0)
9538 as_warn(_("Condition code register should be 0 or 4 for %s, was %d"),
9539 str, regno);
9540 if (*args == 'N')
9157 ip->insn_opcode |= regno << OP_SH_BCC;
9541 INSERT_OPERAND (BCC, *ip, regno);
9158 else
9542 else
9159 ip->insn_opcode |= regno << OP_SH_CCC;
9543 INSERT_OPERAND (CCC, *ip, regno);
9160 continue;
9161
9162 case 'H':
9163 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9164 s += 2;
9165 if (ISDIGIT (*s))
9166 {
9167 c = 0;

--- 21 unchanged lines hidden (view full) ---

9189 if ((unsigned long) imm_expr.X_add_number
9190 > (unsigned long) OP_MASK_VECBYTE)
9191 {
9192 as_bad (_("bad byte vector index (%ld)"),
9193 (long) imm_expr.X_add_number);
9194 imm_expr.X_add_number = 0;
9195 }
9196
9544 continue;
9545
9546 case 'H':
9547 if (s[0] == '0' && (s[1] == 'x' || s[1] == 'X'))
9548 s += 2;
9549 if (ISDIGIT (*s))
9550 {
9551 c = 0;

--- 21 unchanged lines hidden (view full) ---

9573 if ((unsigned long) imm_expr.X_add_number
9574 > (unsigned long) OP_MASK_VECBYTE)
9575 {
9576 as_bad (_("bad byte vector index (%ld)"),
9577 (long) imm_expr.X_add_number);
9578 imm_expr.X_add_number = 0;
9579 }
9580
9197 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECBYTE;
9581 INSERT_OPERAND (VECBYTE, *ip, imm_expr.X_add_number);
9198 imm_expr.X_op = O_absent;
9199 s = expr_end;
9200 continue;
9201
9202 case '%':
9203 my_getExpression (&imm_expr, s);
9204 check_absolute_expr (ip, &imm_expr);
9205
9206 if ((unsigned long) imm_expr.X_add_number
9207 > (unsigned long) OP_MASK_VECALIGN)
9208 {
9209 as_bad (_("bad byte vector index (%ld)"),
9210 (long) imm_expr.X_add_number);
9211 imm_expr.X_add_number = 0;
9212 }
9213
9582 imm_expr.X_op = O_absent;
9583 s = expr_end;
9584 continue;
9585
9586 case '%':
9587 my_getExpression (&imm_expr, s);
9588 check_absolute_expr (ip, &imm_expr);
9589
9590 if ((unsigned long) imm_expr.X_add_number
9591 > (unsigned long) OP_MASK_VECALIGN)
9592 {
9593 as_bad (_("bad byte vector index (%ld)"),
9594 (long) imm_expr.X_add_number);
9595 imm_expr.X_add_number = 0;
9596 }
9597
9214 ip->insn_opcode |= imm_expr.X_add_number << OP_SH_VECALIGN;
9598 INSERT_OPERAND (VECALIGN, *ip, imm_expr.X_add_number);
9215 imm_expr.X_op = O_absent;
9216 s = expr_end;
9217 continue;
9218
9219 default:
9220 as_bad (_("bad char = '%c'\n"), *args);
9221 internalError ();
9222 }

--- 10 unchanged lines hidden (view full) ---

9233 }
9234 if (save_c)
9235 *(--s) = save_c;
9236 insn_error = _("illegal operands");
9237 return;
9238 }
9239}
9240
9599 imm_expr.X_op = O_absent;
9600 s = expr_end;
9601 continue;
9602
9603 default:
9604 as_bad (_("bad char = '%c'\n"), *args);
9605 internalError ();
9606 }

--- 10 unchanged lines hidden (view full) ---

9617 }
9618 if (save_c)
9619 *(--s) = save_c;
9620 insn_error = _("illegal operands");
9621 return;
9622 }
9623}
9624
9625#define SKIP_SPACE_TABS(S) { while (*(S) == ' ' || *(S) == '\t') ++(S); }
9626
9241/* This routine assembles an instruction into its binary format when
9242 assembling for the mips16. As a side effect, it sets one of the
9243 global variables imm_reloc or offset_reloc to the type of
9244 relocation to do if one of the operands is an address expression.
9245 It also sets mips16_small and mips16_ext if the user explicitly
9246 requested a small or extended instruction. */
9247
9248static void
9249mips16_ip (char *str, struct mips_cl_insn *ip)
9250{
9251 char *s;
9252 const char *args;
9253 struct mips_opcode *insn;
9254 char *argsstart;
9255 unsigned int regno;
9256 unsigned int lastregno = 0;
9257 char *s_reset;
9627/* This routine assembles an instruction into its binary format when
9628 assembling for the mips16. As a side effect, it sets one of the
9629 global variables imm_reloc or offset_reloc to the type of
9630 relocation to do if one of the operands is an address expression.
9631 It also sets mips16_small and mips16_ext if the user explicitly
9632 requested a small or extended instruction. */
9633
9634static void
9635mips16_ip (char *str, struct mips_cl_insn *ip)
9636{
9637 char *s;
9638 const char *args;
9639 struct mips_opcode *insn;
9640 char *argsstart;
9641 unsigned int regno;
9642 unsigned int lastregno = 0;
9643 char *s_reset;
9644 size_t i;
9258
9259 insn_error = NULL;
9260
9261 mips16_small = FALSE;
9262 mips16_ext = FALSE;
9263
9264 for (s = str; ISLOWER (*s); ++s)
9265 ;

--- 36 unchanged lines hidden (view full) ---

9302 return;
9303 }
9304
9305 argsstart = s;
9306 for (;;)
9307 {
9308 assert (strcmp (insn->name, str) == 0);
9309
9645
9646 insn_error = NULL;
9647
9648 mips16_small = FALSE;
9649 mips16_ext = FALSE;
9650
9651 for (s = str; ISLOWER (*s); ++s)
9652 ;

--- 36 unchanged lines hidden (view full) ---

9689 return;
9690 }
9691
9692 argsstart = s;
9693 for (;;)
9694 {
9695 assert (strcmp (insn->name, str) == 0);
9696
9310 ip->insn_mo = insn;
9311 ip->insn_opcode = insn->match;
9312 ip->use_extend = FALSE;
9697 create_insn (ip, insn);
9313 imm_expr.X_op = O_absent;
9314 imm_reloc[0] = BFD_RELOC_UNUSED;
9315 imm_reloc[1] = BFD_RELOC_UNUSED;
9316 imm_reloc[2] = BFD_RELOC_UNUSED;
9317 imm2_expr.X_op = O_absent;
9318 offset_expr.X_op = O_absent;
9319 offset_reloc[0] = BFD_RELOC_UNUSED;
9320 offset_reloc[1] = BFD_RELOC_UNUSED;

--- 15 unchanged lines hidden (view full) ---

9336 case '\0':
9337 if (*s == '\0')
9338 {
9339 /* Stuff the immediate value in now, if we can. */
9340 if (imm_expr.X_op == O_constant
9341 && *imm_reloc > BFD_RELOC_UNUSED
9342 && insn->pinfo != INSN_MACRO)
9343 {
9698 imm_expr.X_op = O_absent;
9699 imm_reloc[0] = BFD_RELOC_UNUSED;
9700 imm_reloc[1] = BFD_RELOC_UNUSED;
9701 imm_reloc[2] = BFD_RELOC_UNUSED;
9702 imm2_expr.X_op = O_absent;
9703 offset_expr.X_op = O_absent;
9704 offset_reloc[0] = BFD_RELOC_UNUSED;
9705 offset_reloc[1] = BFD_RELOC_UNUSED;

--- 15 unchanged lines hidden (view full) ---

9721 case '\0':
9722 if (*s == '\0')
9723 {
9724 /* Stuff the immediate value in now, if we can. */
9725 if (imm_expr.X_op == O_constant
9726 && *imm_reloc > BFD_RELOC_UNUSED
9727 && insn->pinfo != INSN_MACRO)
9728 {
9729 *offset_reloc = BFD_RELOC_UNUSED;
9730
9344 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9345 imm_expr.X_add_number, TRUE, mips16_small,
9346 mips16_ext, &ip->insn_opcode,
9347 &ip->use_extend, &ip->extend);
9348 imm_expr.X_op = O_absent;
9349 *imm_reloc = BFD_RELOC_UNUSED;
9350 }
9351
9352 return;
9353 }
9354 break;
9355
9356 case ',':
9357 if (*s++ == c)
9358 continue;
9359 s--;
9360 switch (*++args)
9361 {
9362 case 'v':
9731 mips16_immed (NULL, 0, *imm_reloc - BFD_RELOC_UNUSED,
9732 imm_expr.X_add_number, TRUE, mips16_small,
9733 mips16_ext, &ip->insn_opcode,
9734 &ip->use_extend, &ip->extend);
9735 imm_expr.X_op = O_absent;
9736 *imm_reloc = BFD_RELOC_UNUSED;
9737 }
9738
9739 return;
9740 }
9741 break;
9742
9743 case ',':
9744 if (*s++ == c)
9745 continue;
9746 s--;
9747 switch (*++args)
9748 {
9749 case 'v':
9363 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9750 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9364 continue;
9365 case 'w':
9751 continue;
9752 case 'w':
9366 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9753 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9367 continue;
9368 }
9369 break;
9370
9371 case '(':
9372 case ')':
9373 if (*s++ == c)
9374 continue;
9375 break;
9376
9377 case 'v':
9378 case 'w':
9379 if (s[0] != '$')
9380 {
9381 if (c == 'v')
9754 continue;
9755 }
9756 break;
9757
9758 case '(':
9759 case ')':
9760 if (*s++ == c)
9761 continue;
9762 break;
9763
9764 case 'v':
9765 case 'w':
9766 if (s[0] != '$')
9767 {
9768 if (c == 'v')
9382 ip->insn_opcode |= lastregno << MIPS16OP_SH_RX;
9769 MIPS16_INSERT_OPERAND (RX, *ip, lastregno);
9383 else
9770 else
9384 ip->insn_opcode |= lastregno << MIPS16OP_SH_RY;
9771 MIPS16_INSERT_OPERAND (RY, *ip, lastregno);
9385 ++args;
9386 continue;
9387 }
9388 /* Fall through. */
9389 case 'x':
9390 case 'y':
9391 case 'z':
9392 case 'Z':

--- 118 unchanged lines hidden (view full) ---

9511
9512 if (regno == ILLEGAL_REG)
9513 break;
9514
9515 switch (c)
9516 {
9517 case 'x':
9518 case 'v':
9772 ++args;
9773 continue;
9774 }
9775 /* Fall through. */
9776 case 'x':
9777 case 'y':
9778 case 'z':
9779 case 'Z':

--- 118 unchanged lines hidden (view full) ---

9898
9899 if (regno == ILLEGAL_REG)
9900 break;
9901
9902 switch (c)
9903 {
9904 case 'x':
9905 case 'v':
9519 ip->insn_opcode |= regno << MIPS16OP_SH_RX;
9906 MIPS16_INSERT_OPERAND (RX, *ip, regno);
9520 break;
9521 case 'y':
9522 case 'w':
9907 break;
9908 case 'y':
9909 case 'w':
9523 ip->insn_opcode |= regno << MIPS16OP_SH_RY;
9910 MIPS16_INSERT_OPERAND (RY, *ip, regno);
9524 break;
9525 case 'z':
9911 break;
9912 case 'z':
9526 ip->insn_opcode |= regno << MIPS16OP_SH_RZ;
9913 MIPS16_INSERT_OPERAND (RZ, *ip, regno);
9527 break;
9528 case 'Z':
9914 break;
9915 case 'Z':
9529 ip->insn_opcode |= regno << MIPS16OP_SH_MOVE32Z;
9916 MIPS16_INSERT_OPERAND (MOVE32Z, *ip, regno);
9530 case '0':
9531 case 'S':
9532 case 'R':
9533 break;
9534 case 'X':
9917 case '0':
9918 case 'S':
9919 case 'R':
9920 break;
9921 case 'X':
9535 ip->insn_opcode |= regno << MIPS16OP_SH_REGR32;
9922 MIPS16_INSERT_OPERAND (REGR32, *ip, regno);
9536 break;
9537 case 'Y':
9538 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9923 break;
9924 case 'Y':
9925 regno = ((regno & 7) << 2) | ((regno & 0x18) >> 3);
9539 ip->insn_opcode |= regno << MIPS16OP_SH_REG32R;
9926 MIPS16_INSERT_OPERAND (REG32R, *ip, regno);
9540 break;
9541 default:
9542 internalError ();
9543 }
9544
9545 lastregno = regno;
9546 continue;
9547
9548 case 'P':
9549 if (strncmp (s, "$pc", 3) == 0)
9550 {
9551 s += 3;
9552 continue;
9553 }
9554 break;
9555
9927 break;
9928 default:
9929 internalError ();
9930 }
9931
9932 lastregno = regno;
9933 continue;
9934
9935 case 'P':
9936 if (strncmp (s, "$pc", 3) == 0)
9937 {
9938 s += 3;
9939 continue;
9940 }
9941 break;
9942
9556 case '<':
9557 case '>':
9558 case '[':
9559 case ']':
9560 case '4':
9561 case '5':
9562 case 'H':
9563 case 'W':
9564 case 'D':
9565 case 'j':
9943 case '5':
9944 case 'H':
9945 case 'W':
9946 case 'D':
9947 case 'j':
9566 case '8':
9567 case 'V':
9568 case 'C':
9569 case 'U':
9570 case 'k':
9571 case 'K':
9948 case 'V':
9949 case 'C':
9950 case 'U':
9951 case 'k':
9952 case 'K':
9572 if (s[0] == '%'
9573 && strncmp (s + 1, "gprel(", sizeof "gprel(" - 1) == 0)
9953 i = my_getSmallExpression (&imm_expr, imm_reloc, s);
9954 if (i > 0)
9574 {
9955 {
9575 /* This is %gprel(SYMBOL). We need to read SYMBOL,
9576 and generate the appropriate reloc. If the text
9577 inside %gprel is not a symbol name with an
9578 optional offset, then we generate a normal reloc
9579 and will probably fail later. */
9580 my_getExpression (&imm_expr, s + sizeof "%gprel" - 1);
9581 if (imm_expr.X_op == O_symbol)
9956 if (imm_expr.X_op != O_constant)
9582 {
9583 mips16_ext = TRUE;
9957 {
9958 mips16_ext = TRUE;
9584 *imm_reloc = BFD_RELOC_MIPS16_GPREL;
9585 s = expr_end;
9586 ip->use_extend = TRUE;
9587 ip->extend = 0;
9959 ip->use_extend = TRUE;
9960 ip->extend = 0;
9588 continue;
9589 }
9961 }
9962 else
9963 {
9964 /* We need to relax this instruction. */
9965 *offset_reloc = *imm_reloc;
9966 *imm_reloc = (int) BFD_RELOC_UNUSED + c;
9967 }
9968 s = expr_end;
9969 continue;
9590 }
9970 }
9591 else
9592 {
9593 /* Just pick up a normal expression. */
9594 my_getExpression (&imm_expr, s);
9595 }
9596
9971 *imm_reloc = BFD_RELOC_UNUSED;
9972 /* Fall through. */
9973 case '<':
9974 case '>':
9975 case '[':
9976 case ']':
9977 case '4':
9978 case '8':
9979 my_getExpression (&imm_expr, s);
9597 if (imm_expr.X_op == O_register)
9598 {
9599 /* What we thought was an expression turned out to
9600 be a register. */
9601
9602 if (s[0] == '(' && args[1] == '(')
9603 {
9604 /* It looks like the expression was omitted

--- 32 unchanged lines hidden (view full) ---

9637 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
9638 s = expr_end;
9639 continue;
9640
9641 case '6': /* break code */
9642 my_getExpression (&imm_expr, s);
9643 check_absolute_expr (ip, &imm_expr);
9644 if ((unsigned long) imm_expr.X_add_number > 63)
9980 if (imm_expr.X_op == O_register)
9981 {
9982 /* What we thought was an expression turned out to
9983 be a register. */
9984
9985 if (s[0] == '(' && args[1] == '(')
9986 {
9987 /* It looks like the expression was omitted

--- 32 unchanged lines hidden (view full) ---

10020 *offset_reloc = (int) BFD_RELOC_UNUSED + c;
10021 s = expr_end;
10022 continue;
10023
10024 case '6': /* break code */
10025 my_getExpression (&imm_expr, s);
10026 check_absolute_expr (ip, &imm_expr);
10027 if ((unsigned long) imm_expr.X_add_number > 63)
9645 {
9646 as_warn (_("Invalid value for `%s' (%lu)"),
9647 ip->insn_mo->name,
9648 (unsigned long) imm_expr.X_add_number);
9649 imm_expr.X_add_number &= 0x3f;
9650 }
9651 ip->insn_opcode |= imm_expr.X_add_number << MIPS16OP_SH_IMM6;
10028 as_warn (_("Invalid value for `%s' (%lu)"),
10029 ip->insn_mo->name,
10030 (unsigned long) imm_expr.X_add_number);
10031 MIPS16_INSERT_OPERAND (IMM6, *ip, imm_expr.X_add_number);
9652 imm_expr.X_op = O_absent;
9653 s = expr_end;
9654 continue;
9655
9656 case 'a': /* 26 bit address */
9657 my_getExpression (&offset_expr, s);
9658 s = expr_end;
9659 *offset_reloc = BFD_RELOC_MIPS16_JMP;

--- 88 unchanged lines hidden (view full) ---

9748 /* The mask is filled in in the opcode table for the
9749 benefit of the disassembler. We remove it before
9750 applying the actual mask. */
9751 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
9752 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
9753 }
9754 continue;
9755
10032 imm_expr.X_op = O_absent;
10033 s = expr_end;
10034 continue;
10035
10036 case 'a': /* 26 bit address */
10037 my_getExpression (&offset_expr, s);
10038 s = expr_end;
10039 *offset_reloc = BFD_RELOC_MIPS16_JMP;

--- 88 unchanged lines hidden (view full) ---

10128 /* The mask is filled in in the opcode table for the
10129 benefit of the disassembler. We remove it before
10130 applying the actual mask. */
10131 ip->insn_opcode &= ~ ((7 << 3) << MIPS16OP_SH_IMM6);
10132 ip->insn_opcode |= mask << MIPS16OP_SH_IMM6;
10133 }
10134 continue;
10135
10136 case 'm': /* Register list for save insn. */
10137 case 'M': /* Register list for restore insn. */
10138 {
10139 int opcode = 0;
10140 int framesz = 0, seen_framesz = 0;
10141 int args = 0, statics = 0, sregs = 0;
10142
10143 while (*s != '\0')
10144 {
10145 unsigned int reg1, reg2;
10146
10147 SKIP_SPACE_TABS (s);
10148 while (*s == ',')
10149 ++s;
10150 SKIP_SPACE_TABS (s);
10151
10152 my_getExpression (&imm_expr, s);
10153 if (imm_expr.X_op == O_constant)
10154 {
10155 /* Handle the frame size. */
10156 if (seen_framesz)
10157 {
10158 as_bad (_("more than one frame size in list"));
10159 break;
10160 }
10161 seen_framesz = 1;
10162 framesz = imm_expr.X_add_number;
10163 imm_expr.X_op = O_absent;
10164 s = expr_end;
10165 continue;
10166 }
10167
10168 if (*s != '$')
10169 {
10170 as_bad (_("can't parse register list"));
10171 break;
10172 }
10173 ++s;
10174
10175 reg1 = 0;
10176 while (ISDIGIT (*s))
10177 {
10178 reg1 *= 10;
10179 reg1 += *s - '0';
10180 ++s;
10181 }
10182 SKIP_SPACE_TABS (s);
10183 if (*s != '-')
10184 reg2 = reg1;
10185 else
10186 {
10187 ++s;
10188 if (*s != '$')
10189 {
10190 as_bad (_("can't parse register list"));
10191 break;
10192 }
10193 ++s;
10194 reg2 = 0;
10195 while (ISDIGIT (*s))
10196 {
10197 reg2 *= 10;
10198 reg2 += *s - '0';
10199 ++s;
10200 }
10201 }
10202
10203 while (reg1 <= reg2)
10204 {
10205 if (reg1 >= 4 && reg1 <= 7)
10206 {
10207 if (c == 'm' && !seen_framesz)
10208 /* args $a0-$a3 */
10209 args |= 1 << (reg1 - 4);
10210 else
10211 /* statics $a0-$a3 */
10212 statics |= 1 << (reg1 - 4);
10213 }
10214 else if ((reg1 >= 16 && reg1 <= 23) || reg1 == 30)
10215 {
10216 /* $s0-$s8 */
10217 sregs |= 1 << ((reg1 == 30) ? 8 : (reg1 - 16));
10218 }
10219 else if (reg1 == 31)
10220 {
10221 /* Add $ra to insn. */
10222 opcode |= 0x40;
10223 }
10224 else
10225 {
10226 as_bad (_("unexpected register in list"));
10227 break;
10228 }
10229 if (++reg1 == 24)
10230 reg1 = 30;
10231 }
10232 }
10233
10234 /* Encode args/statics combination. */
10235 if (args & statics)
10236 as_bad (_("arg/static registers overlap"));
10237 else if (args == 0xf)
10238 /* All $a0-$a3 are args. */
10239 opcode |= MIPS16_ALL_ARGS << 16;
10240 else if (statics == 0xf)
10241 /* All $a0-$a3 are statics. */
10242 opcode |= MIPS16_ALL_STATICS << 16;
10243 else
10244 {
10245 int narg = 0, nstat = 0;
10246
10247 /* Count arg registers. */
10248 while (args & 0x1)
10249 {
10250 args >>= 1;
10251 narg++;
10252 }
10253 if (args != 0)
10254 as_bad (_("invalid arg register list"));
10255
10256 /* Count static registers. */
10257 while (statics & 0x8)
10258 {
10259 statics = (statics << 1) & 0xf;
10260 nstat++;
10261 }
10262 if (statics != 0)
10263 as_bad (_("invalid static register list"));
10264
10265 /* Encode args/statics. */
10266 opcode |= ((narg << 2) | nstat) << 16;
10267 }
10268
10269 /* Encode $s0/$s1. */
10270 if (sregs & (1 << 0)) /* $s0 */
10271 opcode |= 0x20;
10272 if (sregs & (1 << 1)) /* $s1 */
10273 opcode |= 0x10;
10274 sregs >>= 2;
10275
10276 if (sregs != 0)
10277 {
10278 /* Count regs $s2-$s8. */
10279 int nsreg = 0;
10280 while (sregs & 1)
10281 {
10282 sregs >>= 1;
10283 nsreg++;
10284 }
10285 if (sregs != 0)
10286 as_bad (_("invalid static register list"));
10287 /* Encode $s2-$s8. */
10288 opcode |= nsreg << 24;
10289 }
10290
10291 /* Encode frame size. */
10292 if (!seen_framesz)
10293 as_bad (_("missing frame size"));
10294 else if ((framesz & 7) != 0 || framesz < 0
10295 || framesz > 0xff * 8)
10296 as_bad (_("invalid frame size"));
10297 else if (framesz != 128 || (opcode >> 16) != 0)
10298 {
10299 framesz /= 8;
10300 opcode |= (((framesz & 0xf0) << 16)
10301 | (framesz & 0x0f));
10302 }
10303
10304 /* Finally build the instruction. */
10305 if ((opcode >> 16) != 0 || framesz == 0)
10306 {
10307 ip->use_extend = TRUE;
10308 ip->extend = opcode >> 16;
10309 }
10310 ip->insn_opcode |= opcode & 0x7f;
10311 }
10312 continue;
10313
9756 case 'e': /* extend code */
9757 my_getExpression (&imm_expr, s);
9758 check_absolute_expr (ip, &imm_expr);
9759 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
9760 {
9761 as_warn (_("Invalid value for `%s' (%lu)"),
9762 ip->insn_mo->name,
9763 (unsigned long) imm_expr.X_add_number);

--- 186 unchanged lines hidden (view full) ---

9950 val = 0;
9951 }
9952
9953 *extend = (unsigned short) extval;
9954 *insn |= val;
9955 }
9956}
9957
10314 case 'e': /* extend code */
10315 my_getExpression (&imm_expr, s);
10316 check_absolute_expr (ip, &imm_expr);
10317 if ((unsigned long) imm_expr.X_add_number > 0x7ff)
10318 {
10319 as_warn (_("Invalid value for `%s' (%lu)"),
10320 ip->insn_mo->name,
10321 (unsigned long) imm_expr.X_add_number);

--- 186 unchanged lines hidden (view full) ---

10508 val = 0;
10509 }
10510
10511 *extend = (unsigned short) extval;
10512 *insn |= val;
10513 }
10514}
10515
9958static const struct percent_op_match
10516struct percent_op_match
9959{
9960 const char *str;
9961 bfd_reloc_code_real_type reloc;
10517{
10518 const char *str;
10519 bfd_reloc_code_real_type reloc;
9962} percent_op[] =
10520};
10521
10522static const struct percent_op_match mips_percent_op[] =
9963{
9964 {"%lo", BFD_RELOC_LO16},
9965#ifdef OBJ_ELF
9966 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
9967 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
9968 {"%call16", BFD_RELOC_MIPS_CALL16},
9969 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
9970 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},

--- 5 unchanged lines hidden (view full) ---

9976 {"%half", BFD_RELOC_16},
9977 {"%highest", BFD_RELOC_MIPS_HIGHEST},
9978 {"%higher", BFD_RELOC_MIPS_HIGHER},
9979 {"%neg", BFD_RELOC_MIPS_SUB},
9980#endif
9981 {"%hi", BFD_RELOC_HI16_S}
9982};
9983
10523{
10524 {"%lo", BFD_RELOC_LO16},
10525#ifdef OBJ_ELF
10526 {"%call_hi", BFD_RELOC_MIPS_CALL_HI16},
10527 {"%call_lo", BFD_RELOC_MIPS_CALL_LO16},
10528 {"%call16", BFD_RELOC_MIPS_CALL16},
10529 {"%got_disp", BFD_RELOC_MIPS_GOT_DISP},
10530 {"%got_page", BFD_RELOC_MIPS_GOT_PAGE},

--- 5 unchanged lines hidden (view full) ---

10536 {"%half", BFD_RELOC_16},
10537 {"%highest", BFD_RELOC_MIPS_HIGHEST},
10538 {"%higher", BFD_RELOC_MIPS_HIGHER},
10539 {"%neg", BFD_RELOC_MIPS_SUB},
10540#endif
10541 {"%hi", BFD_RELOC_HI16_S}
10542};
10543
9984
9985/* Return true if *STR points to a relocation operator. When returning true,
9986 move *STR over the operator and store its relocation code in *RELOC.
9987 Leave both *STR and *RELOC alone when returning false. */
9988
9989static bfd_boolean
9990parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
9991{
10544/* Return true if *STR points to a relocation operator. When returning true,
10545 move *STR over the operator and store its relocation code in *RELOC.
10546 Leave both *STR and *RELOC alone when returning false. */
10547
10548static bfd_boolean
10549parse_relocation (char **str, bfd_reloc_code_real_type *reloc)
10550{
9992 size_t i;
10551 const struct percent_op_match *percent_op;
10552 size_t limit, i;
9993
10553
9994 for (i = 0; i < ARRAY_SIZE (percent_op); i++)
10554 percent_op = mips_percent_op;
10555 limit = ARRAY_SIZE (mips_percent_op);
10556
10557 for (i = 0; i < limit; i++)
9995 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
9996 {
10558 if (strncasecmp (*str, percent_op[i].str, strlen (percent_op[i].str)) == 0)
10559 {
10560 int len = strlen (percent_op[i].str);
10561
10562 if (!ISSPACE ((*str)[len]) && (*str)[len] != '(')
10563 continue;
10564
9997 *str += strlen (percent_op[i].str);
9998 *reloc = percent_op[i].reloc;
9999
10000 /* Check whether the output BFD supports this relocation.
10001 If not, issue an error and fall back on something safe. */
10002 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10003 {
10004 as_bad ("relocation %s isn't supported by the current ABI",
10005 percent_op[i].str);
10565 *str += strlen (percent_op[i].str);
10566 *reloc = percent_op[i].reloc;
10567
10568 /* Check whether the output BFD supports this relocation.
10569 If not, issue an error and fall back on something safe. */
10570 if (!bfd_reloc_type_lookup (stdoutput, percent_op[i].reloc))
10571 {
10572 as_bad ("relocation %s isn't supported by the current ABI",
10573 percent_op[i].str);
10006 *reloc = BFD_RELOC_LO16;
10574 *reloc = BFD_RELOC_UNUSED;
10007 }
10008 return TRUE;
10009 }
10010 return FALSE;
10011}
10012
10013
10014/* Parse string STR as a 16-bit relocatable operand. Store the
10015 expression in *EP and the relocations in the array starting
10016 at RELOC. Return the number of relocation operators used.
10017
10575 }
10576 return TRUE;
10577 }
10578 return FALSE;
10579}
10580
10581
10582/* Parse string STR as a 16-bit relocatable operand. Store the
10583 expression in *EP and the relocations in the array starting
10584 at RELOC. Return the number of relocation operators used.
10585
10018 On exit, EXPR_END points to the first character after the expression.
10019 If no relocation operators are used, RELOC[0] is set to BFD_RELOC_LO16. */
10586 On exit, EXPR_END points to the first character after the expression. */
10020
10021static size_t
10022my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10023 char *str)
10024{
10025 bfd_reloc_code_real_type reversed_reloc[3];
10026 size_t reloc_index, i;
10027 int crux_depth, str_depth;

--- 29 unchanged lines hidden (view full) ---

10057 if (*str++ == ')')
10058 crux_depth--;
10059
10060 if (crux_depth > 0)
10061 as_bad ("unclosed '('");
10062
10063 expr_end = str;
10064
10587
10588static size_t
10589my_getSmallExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
10590 char *str)
10591{
10592 bfd_reloc_code_real_type reversed_reloc[3];
10593 size_t reloc_index, i;
10594 int crux_depth, str_depth;

--- 29 unchanged lines hidden (view full) ---

10624 if (*str++ == ')')
10625 crux_depth--;
10626
10627 if (crux_depth > 0)
10628 as_bad ("unclosed '('");
10629
10630 expr_end = str;
10631
10065 if (reloc_index == 0)
10066 reloc[0] = BFD_RELOC_LO16;
10067 else
10632 if (reloc_index != 0)
10068 {
10069 prev_reloc_op_frag = frag_now;
10070 for (i = 0; i < reloc_index; i++)
10071 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10072 }
10073
10074 return reloc_index;
10075}

--- 149 unchanged lines hidden (view full) ---

10225#define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10226 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10227#define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10228 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10229#define OPTION_MDMX (OPTION_ASE_BASE + 4)
10230 {"mdmx", no_argument, NULL, OPTION_MDMX},
10231#define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10232 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10633 {
10634 prev_reloc_op_frag = frag_now;
10635 for (i = 0; i < reloc_index; i++)
10636 reloc[i] = reversed_reloc[reloc_index - 1 - i];
10637 }
10638
10639 return reloc_index;
10640}

--- 149 unchanged lines hidden (view full) ---

10790#define OPTION_MIPS3D (OPTION_ASE_BASE + 2)
10791 {"mips3d", no_argument, NULL, OPTION_MIPS3D},
10792#define OPTION_NO_MIPS3D (OPTION_ASE_BASE + 3)
10793 {"no-mips3d", no_argument, NULL, OPTION_NO_MIPS3D},
10794#define OPTION_MDMX (OPTION_ASE_BASE + 4)
10795 {"mdmx", no_argument, NULL, OPTION_MDMX},
10796#define OPTION_NO_MDMX (OPTION_ASE_BASE + 5)
10797 {"no-mdmx", no_argument, NULL, OPTION_NO_MDMX},
10798#define OPTION_DSP (OPTION_ASE_BASE + 6)
10799 {"mdsp", no_argument, NULL, OPTION_DSP},
10800#define OPTION_NO_DSP (OPTION_ASE_BASE + 7)
10801 {"mno-dsp", no_argument, NULL, OPTION_NO_DSP},
10802#define OPTION_MT (OPTION_ASE_BASE + 8)
10803 {"mmt", no_argument, NULL, OPTION_MT},
10804#define OPTION_NO_MT (OPTION_ASE_BASE + 9)
10805 {"mno-mt", no_argument, NULL, OPTION_NO_MT},
10233
10234 /* Old-style architecture options. Don't add more of these. */
10806
10807 /* Old-style architecture options. Don't add more of these. */
10235#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 6)
10808#define OPTION_COMPAT_ARCH_BASE (OPTION_ASE_BASE + 10)
10236#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10237 {"m4650", no_argument, NULL, OPTION_M4650},
10238#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10239 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10240#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10241 {"m4010", no_argument, NULL, OPTION_M4010},
10242#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10243 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},

--- 12 unchanged lines hidden (view full) ---

10256 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10257#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10258 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10259 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10260#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10261#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10262 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10263 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10809#define OPTION_M4650 (OPTION_COMPAT_ARCH_BASE + 0)
10810 {"m4650", no_argument, NULL, OPTION_M4650},
10811#define OPTION_NO_M4650 (OPTION_COMPAT_ARCH_BASE + 1)
10812 {"no-m4650", no_argument, NULL, OPTION_NO_M4650},
10813#define OPTION_M4010 (OPTION_COMPAT_ARCH_BASE + 2)
10814 {"m4010", no_argument, NULL, OPTION_M4010},
10815#define OPTION_NO_M4010 (OPTION_COMPAT_ARCH_BASE + 3)
10816 {"no-m4010", no_argument, NULL, OPTION_NO_M4010},

--- 12 unchanged lines hidden (view full) ---

10829 {"mfix7000", no_argument, NULL, OPTION_M7000_HILO_FIX},
10830#define OPTION_MNO_7000_HILO_FIX (OPTION_FIX_BASE + 1)
10831 {"no-fix-7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10832 {"mno-fix7000", no_argument, NULL, OPTION_MNO_7000_HILO_FIX},
10833#define OPTION_FIX_VR4120 (OPTION_FIX_BASE + 2)
10834#define OPTION_NO_FIX_VR4120 (OPTION_FIX_BASE + 3)
10835 {"mfix-vr4120", no_argument, NULL, OPTION_FIX_VR4120},
10836 {"mno-fix-vr4120", no_argument, NULL, OPTION_NO_FIX_VR4120},
10837#define OPTION_FIX_VR4130 (OPTION_FIX_BASE + 4)
10838#define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
10839 {"mfix-vr4130", no_argument, NULL, OPTION_FIX_VR4130},
10840 {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
10264
10265 /* Miscellaneous options. */
10841
10842 /* Miscellaneous options. */
10266#define OPTION_MISC_BASE (OPTION_FIX_BASE + 4)
10267#define OPTION_MEMBEDDED_PIC (OPTION_MISC_BASE + 0)
10268 {"membedded-pic", no_argument, NULL, OPTION_MEMBEDDED_PIC},
10269#define OPTION_TRAP (OPTION_MISC_BASE + 1)
10843#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
10844#define OPTION_TRAP (OPTION_MISC_BASE + 0)
10270 {"trap", no_argument, NULL, OPTION_TRAP},
10271 {"no-break", no_argument, NULL, OPTION_TRAP},
10845 {"trap", no_argument, NULL, OPTION_TRAP},
10846 {"no-break", no_argument, NULL, OPTION_TRAP},
10272#define OPTION_BREAK (OPTION_MISC_BASE + 2)
10847#define OPTION_BREAK (OPTION_MISC_BASE + 1)
10273 {"break", no_argument, NULL, OPTION_BREAK},
10274 {"no-trap", no_argument, NULL, OPTION_BREAK},
10848 {"break", no_argument, NULL, OPTION_BREAK},
10849 {"no-trap", no_argument, NULL, OPTION_BREAK},
10275#define OPTION_EB (OPTION_MISC_BASE + 3)
10850#define OPTION_EB (OPTION_MISC_BASE + 2)
10276 {"EB", no_argument, NULL, OPTION_EB},
10851 {"EB", no_argument, NULL, OPTION_EB},
10277#define OPTION_EL (OPTION_MISC_BASE + 4)
10852#define OPTION_EL (OPTION_MISC_BASE + 3)
10278 {"EL", no_argument, NULL, OPTION_EL},
10853 {"EL", no_argument, NULL, OPTION_EL},
10279#define OPTION_FP32 (OPTION_MISC_BASE + 5)
10854#define OPTION_FP32 (OPTION_MISC_BASE + 4)
10280 {"mfp32", no_argument, NULL, OPTION_FP32},
10855 {"mfp32", no_argument, NULL, OPTION_FP32},
10281#define OPTION_GP32 (OPTION_MISC_BASE + 6)
10856#define OPTION_GP32 (OPTION_MISC_BASE + 5)
10282 {"mgp32", no_argument, NULL, OPTION_GP32},
10857 {"mgp32", no_argument, NULL, OPTION_GP32},
10283#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10858#define OPTION_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 6)
10284 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10859 {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS},
10285#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 8)
10860#define OPTION_NO_CONSTRUCT_FLOATS (OPTION_MISC_BASE + 7)
10286 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10861 {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS},
10287#define OPTION_FP64 (OPTION_MISC_BASE + 9)
10862#define OPTION_FP64 (OPTION_MISC_BASE + 8)
10288 {"mfp64", no_argument, NULL, OPTION_FP64},
10863 {"mfp64", no_argument, NULL, OPTION_FP64},
10289#define OPTION_GP64 (OPTION_MISC_BASE + 10)
10864#define OPTION_GP64 (OPTION_MISC_BASE + 9)
10290 {"mgp64", no_argument, NULL, OPTION_GP64},
10865 {"mgp64", no_argument, NULL, OPTION_GP64},
10291#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10292#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 12)
10866#define OPTION_RELAX_BRANCH (OPTION_MISC_BASE + 10)
10867#define OPTION_NO_RELAX_BRANCH (OPTION_MISC_BASE + 11)
10293 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10294 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10868 {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH},
10869 {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH},
10870#define OPTION_MSHARED (OPTION_MISC_BASE + 12)
10871#define OPTION_MNO_SHARED (OPTION_MISC_BASE + 13)
10872 {"mshared", no_argument, NULL, OPTION_MSHARED},
10873 {"mno-shared", no_argument, NULL, OPTION_MNO_SHARED},
10874#define OPTION_MSYM32 (OPTION_MISC_BASE + 14)
10875#define OPTION_MNO_SYM32 (OPTION_MISC_BASE + 15)
10876 {"msym32", no_argument, NULL, OPTION_MSYM32},
10877 {"mno-sym32", no_argument, NULL, OPTION_MNO_SYM32},
10295
10296 /* ELF-specific options. */
10297#ifdef OBJ_ELF
10878
10879 /* ELF-specific options. */
10880#ifdef OBJ_ELF
10298#define OPTION_ELF_BASE (OPTION_MISC_BASE + 13)
10881#define OPTION_ELF_BASE (OPTION_MISC_BASE + 16)
10299#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10300 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10301 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10302#define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10303 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10304#define OPTION_XGOT (OPTION_ELF_BASE + 2)
10305 {"xgot", no_argument, NULL, OPTION_XGOT},
10306#define OPTION_MABI (OPTION_ELF_BASE + 3)

--- 9 unchanged lines hidden (view full) ---

10316#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10317 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10318#define OPTION_PDR (OPTION_ELF_BASE + 9)
10319 {"mpdr", no_argument, NULL, OPTION_PDR},
10320#define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10321 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10322#endif /* OBJ_ELF */
10323
10882#define OPTION_CALL_SHARED (OPTION_ELF_BASE + 0)
10883 {"KPIC", no_argument, NULL, OPTION_CALL_SHARED},
10884 {"call_shared", no_argument, NULL, OPTION_CALL_SHARED},
10885#define OPTION_NON_SHARED (OPTION_ELF_BASE + 1)
10886 {"non_shared", no_argument, NULL, OPTION_NON_SHARED},
10887#define OPTION_XGOT (OPTION_ELF_BASE + 2)
10888 {"xgot", no_argument, NULL, OPTION_XGOT},
10889#define OPTION_MABI (OPTION_ELF_BASE + 3)

--- 9 unchanged lines hidden (view full) ---

10899#define OPTION_NO_MDEBUG (OPTION_ELF_BASE + 8)
10900 {"no-mdebug", no_argument, NULL, OPTION_NO_MDEBUG},
10901#define OPTION_PDR (OPTION_ELF_BASE + 9)
10902 {"mpdr", no_argument, NULL, OPTION_PDR},
10903#define OPTION_NO_PDR (OPTION_ELF_BASE + 10)
10904 {"mno-pdr", no_argument, NULL, OPTION_NO_PDR},
10905#endif /* OBJ_ELF */
10906
10907#define OPTION_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 28)
10908#define OPTION_NO_MOCTEON_UNSUPPORTED (OPTION_MISC_BASE + 29)
10909 {"mocteon-unsupported", no_argument, NULL, OPTION_MOCTEON_UNSUPPORTED},
10910 {"mno-octeon-unsupported", no_argument, NULL, OPTION_NO_MOCTEON_UNSUPPORTED},
10911
10912#define OPTION_MOCTEON_USEUN (OPTION_MISC_BASE + 30)
10913#define OPTION_NO_MOCTEON_USEUN (OPTION_MISC_BASE + 31)
10914 {"mocteon-useun", no_argument, NULL, OPTION_MOCTEON_USEUN},
10915 {"mno-octeon-useun", no_argument, NULL, OPTION_NO_MOCTEON_USEUN},
10916
10324 {NULL, no_argument, NULL, 0}
10325};
10326size_t md_longopts_size = sizeof (md_longopts);
10327
10328/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10329 NEW_VALUE. Warn if another value was already specified. Note:
10330 we have to defer parsing the -march and -mtune arguments in order
10331 to handle 'from-abi' correctly, since the ABI might be specified

--- 34 unchanged lines hidden (view full) ---

10366 case OPTION_EB:
10367 target_big_endian = 1;
10368 break;
10369
10370 case OPTION_EL:
10371 target_big_endian = 0;
10372 break;
10373
10917 {NULL, no_argument, NULL, 0}
10918};
10919size_t md_longopts_size = sizeof (md_longopts);
10920
10921/* Set STRING_PTR (either &mips_arch_string or &mips_tune_string) to
10922 NEW_VALUE. Warn if another value was already specified. Note:
10923 we have to defer parsing the -march and -mtune arguments in order
10924 to handle 'from-abi' correctly, since the ABI might be specified

--- 34 unchanged lines hidden (view full) ---

10959 case OPTION_EB:
10960 target_big_endian = 1;
10961 break;
10962
10963 case OPTION_EL:
10964 target_big_endian = 0;
10965 break;
10966
10967 case OPTION_MOCTEON_UNSUPPORTED:
10968 octeon_error_on_unsupported = 1;
10969 break;
10970
10971 case OPTION_NO_MOCTEON_UNSUPPORTED:
10972 octeon_error_on_unsupported = 0;
10973 break;
10974
10975 case OPTION_MOCTEON_USEUN:
10976 octeon_use_unalign = 1;
10977 break;
10978
10979 case OPTION_NO_MOCTEON_USEUN:
10980 octeon_use_unalign = 0;
10981 break;
10982
10374 case 'O':
10375 if (arg && arg[1] == '0')
10376 mips_optimize = 1;
10377 else
10378 mips_optimize = 2;
10379 break;
10380
10381 case 'g':

--- 87 unchanged lines hidden (view full) ---

10469 case OPTION_MDMX:
10470 mips_opts.ase_mdmx = 1;
10471 break;
10472
10473 case OPTION_NO_MDMX:
10474 mips_opts.ase_mdmx = 0;
10475 break;
10476
10983 case 'O':
10984 if (arg && arg[1] == '0')
10985 mips_optimize = 1;
10986 else
10987 mips_optimize = 2;
10988 break;
10989
10990 case 'g':

--- 87 unchanged lines hidden (view full) ---

11078 case OPTION_MDMX:
11079 mips_opts.ase_mdmx = 1;
11080 break;
11081
11082 case OPTION_NO_MDMX:
11083 mips_opts.ase_mdmx = 0;
11084 break;
11085
11086 case OPTION_DSP:
11087 mips_opts.ase_dsp = 1;
11088 break;
11089
11090 case OPTION_NO_DSP:
11091 mips_opts.ase_dsp = 0;
11092 break;
11093
11094 case OPTION_MT:
11095 mips_opts.ase_mt = 1;
11096 break;
11097
11098 case OPTION_NO_MT:
11099 mips_opts.ase_mt = 0;
11100 break;
11101
10477 case OPTION_MIPS16:
10478 mips_opts.mips16 = 1;
11102 case OPTION_MIPS16:
11103 mips_opts.mips16 = 1;
10479 mips_no_prev_insn (FALSE);
11104 mips_no_prev_insn ();
10480 break;
10481
10482 case OPTION_NO_MIPS16:
10483 mips_opts.mips16 = 0;
11105 break;
11106
11107 case OPTION_NO_MIPS16:
11108 mips_opts.mips16 = 0;
10484 mips_no_prev_insn (FALSE);
11109 mips_no_prev_insn ();
10485 break;
10486
10487 case OPTION_MIPS3D:
10488 mips_opts.ase_mips3d = 1;
10489 break;
10490
10491 case OPTION_NO_MIPS3D:
10492 mips_opts.ase_mips3d = 0;
10493 break;
10494
11110 break;
11111
11112 case OPTION_MIPS3D:
11113 mips_opts.ase_mips3d = 1;
11114 break;
11115
11116 case OPTION_NO_MIPS3D:
11117 mips_opts.ase_mips3d = 0;
11118 break;
11119
10495 case OPTION_MEMBEDDED_PIC:
10496 mips_pic = EMBEDDED_PIC;
10497 if (USE_GLOBAL_POINTER_OPT && g_switch_seen)
10498 {
10499 as_bad (_("-G may not be used with embedded PIC code"));
10500 return 0;
10501 }
10502 g_switch_value = 0x7fffffff;
10503 break;
10504
10505 case OPTION_FIX_VR4120:
10506 mips_fix_vr4120 = 1;
10507 break;
10508
10509 case OPTION_NO_FIX_VR4120:
10510 mips_fix_vr4120 = 0;
10511 break;
10512
11120 case OPTION_FIX_VR4120:
11121 mips_fix_vr4120 = 1;
11122 break;
11123
11124 case OPTION_NO_FIX_VR4120:
11125 mips_fix_vr4120 = 0;
11126 break;
11127
11128 case OPTION_FIX_VR4130:
11129 mips_fix_vr4130 = 1;
11130 break;
11131
11132 case OPTION_NO_FIX_VR4130:
11133 mips_fix_vr4130 = 0;
11134 break;
11135
10513 case OPTION_RELAX_BRANCH:
10514 mips_relax_branch = 1;
10515 break;
10516
10517 case OPTION_NO_RELAX_BRANCH:
10518 mips_relax_branch = 0;
10519 break;
10520
11136 case OPTION_RELAX_BRANCH:
11137 mips_relax_branch = 1;
11138 break;
11139
11140 case OPTION_NO_RELAX_BRANCH:
11141 mips_relax_branch = 0;
11142 break;
11143
11144 case OPTION_MSHARED:
11145 mips_in_shared = TRUE;
11146 break;
11147
11148 case OPTION_MNO_SHARED:
11149 mips_in_shared = FALSE;
11150 break;
11151
11152 case OPTION_MSYM32:
11153 mips_opts.sym32 = TRUE;
11154 break;
11155
11156 case OPTION_MNO_SYM32:
11157 mips_opts.sym32 = FALSE;
11158 break;
11159
10521#ifdef OBJ_ELF
10522 /* When generating ELF code, we permit -KPIC and -call_shared to
10523 select SVR4_PIC, and -non_shared to select no PIC. This is
10524 intended to be compatible with Irix 5. */
10525 case OPTION_CALL_SHARED:
10526 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10527 {
10528 as_bad (_("-call_shared is supported only for ELF format"));
10529 return 0;
10530 }
10531 mips_pic = SVR4_PIC;
10532 mips_abicalls = TRUE;
11160#ifdef OBJ_ELF
11161 /* When generating ELF code, we permit -KPIC and -call_shared to
11162 select SVR4_PIC, and -non_shared to select no PIC. This is
11163 intended to be compatible with Irix 5. */
11164 case OPTION_CALL_SHARED:
11165 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11166 {
11167 as_bad (_("-call_shared is supported only for ELF format"));
11168 return 0;
11169 }
11170 mips_pic = SVR4_PIC;
11171 mips_abicalls = TRUE;
10533 if (g_switch_seen && g_switch_value != 0)
10534 {
10535 as_bad (_("-G may not be used with SVR4 PIC code"));
10536 return 0;
10537 }
10538 g_switch_value = 0;
10539 break;
10540
10541 case OPTION_NON_SHARED:
10542 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
10543 {
10544 as_bad (_("-non_shared is supported only for ELF format"));
10545 return 0;
10546 }
10547 mips_pic = NO_PIC;
10548 mips_abicalls = FALSE;
10549 break;
10550
11172 break;
11173
11174 case OPTION_NON_SHARED:
11175 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
11176 {
11177 as_bad (_("-non_shared is supported only for ELF format"));
11178 return 0;
11179 }
11180 mips_pic = NO_PIC;
11181 mips_abicalls = FALSE;
11182 break;
11183
10551 /* The -xgot option tells the assembler to use 32 offsets when
10552 accessing the got in SVR4_PIC mode. It is for Irix
11184 /* The -xgot option tells the assembler to use 32 bit offsets
11185 when accessing the got in SVR4_PIC mode. It is for Irix
10553 compatibility. */
10554 case OPTION_XGOT:
10555 mips_big_got = 1;
10556 break;
10557#endif /* OBJ_ELF */
10558
10559 case 'G':
11186 compatibility. */
11187 case OPTION_XGOT:
11188 mips_big_got = 1;
11189 break;
11190#endif /* OBJ_ELF */
11191
11192 case 'G':
10560 if (! USE_GLOBAL_POINTER_OPT)
10561 {
10562 as_bad (_("-G is not supported for this configuration"));
10563 return 0;
10564 }
10565 else if (mips_pic == SVR4_PIC || mips_pic == EMBEDDED_PIC)
10566 {
10567 as_bad (_("-G may not be used with SVR4 or embedded PIC code"));
10568 return 0;
10569 }
10570 else
10571 g_switch_value = atoi (arg);
11193 g_switch_value = atoi (arg);
10572 g_switch_seen = 1;
10573 break;
10574
10575#ifdef OBJ_ELF
10576 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
10577 and -mabi=64. */
10578 case OPTION_32:
10579 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)

--- 131 unchanged lines hidden (view full) ---

10711
10712void
10713mips_after_parse_args (void)
10714{
10715 const struct mips_cpu_info *arch_info = 0;
10716 const struct mips_cpu_info *tune_info = 0;
10717
10718 /* GP relative stuff not working for PE */
11194 g_switch_seen = 1;
11195 break;
11196
11197#ifdef OBJ_ELF
11198 /* The -32, -n32 and -64 options are shortcuts for -mabi=32, -mabi=n32
11199 and -mabi=64. */
11200 case OPTION_32:
11201 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)

--- 131 unchanged lines hidden (view full) ---

11333
11334void
11335mips_after_parse_args (void)
11336{
11337 const struct mips_cpu_info *arch_info = 0;
11338 const struct mips_cpu_info *tune_info = 0;
11339
11340 /* GP relative stuff not working for PE */
10719 if (strncmp (TARGET_OS, "pe", 2) == 0
10720 && g_switch_value != 0)
11341 if (strncmp (TARGET_OS, "pe", 2) == 0)
10721 {
11342 {
10722 if (g_switch_seen)
11343 if (g_switch_seen && g_switch_value != 0)
10723 as_bad (_("-G not supported in this configuration."));
10724 g_switch_value = 0;
10725 }
10726
10727 if (mips_abi == NO_ABI)
10728 mips_abi = MIPS_DEFAULT_ABI;
10729
10730 /* The following code determines the architecture and register size.

--- 85 unchanged lines hidden (view full) ---

10816 /* If the selected architecture includes support for ASEs, enable
10817 generation of code for them. */
10818 if (mips_opts.mips16 == -1)
10819 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
10820 if (mips_opts.ase_mips3d == -1)
10821 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
10822 if (mips_opts.ase_mdmx == -1)
10823 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11344 as_bad (_("-G not supported in this configuration."));
11345 g_switch_value = 0;
11346 }
11347
11348 if (mips_abi == NO_ABI)
11349 mips_abi = MIPS_DEFAULT_ABI;
11350
11351 /* The following code determines the architecture and register size.

--- 85 unchanged lines hidden (view full) ---

11437 /* If the selected architecture includes support for ASEs, enable
11438 generation of code for them. */
11439 if (mips_opts.mips16 == -1)
11440 mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0;
11441 if (mips_opts.ase_mips3d == -1)
11442 mips_opts.ase_mips3d = (CPU_HAS_MIPS3D (file_mips_arch)) ? 1 : 0;
11443 if (mips_opts.ase_mdmx == -1)
11444 mips_opts.ase_mdmx = (CPU_HAS_MDMX (file_mips_arch)) ? 1 : 0;
11445 if (mips_opts.ase_dsp == -1)
11446 mips_opts.ase_dsp = (CPU_HAS_DSP (file_mips_arch)) ? 1 : 0;
11447 if (mips_opts.ase_mt == -1)
11448 mips_opts.ase_mt = (CPU_HAS_MT (file_mips_arch)) ? 1 : 0;
10824
10825 file_mips_isa = mips_opts.isa;
10826 file_ase_mips16 = mips_opts.mips16;
10827 file_ase_mips3d = mips_opts.ase_mips3d;
10828 file_ase_mdmx = mips_opts.ase_mdmx;
11449
11450 file_mips_isa = mips_opts.isa;
11451 file_ase_mips16 = mips_opts.mips16;
11452 file_ase_mips3d = mips_opts.ase_mips3d;
11453 file_ase_mdmx = mips_opts.ase_mdmx;
11454 file_ase_dsp = mips_opts.ase_dsp;
11455 file_ase_mt = mips_opts.ase_mt;
10829 mips_opts.gp32 = file_mips_gp32;
10830 mips_opts.fp32 = file_mips_fp32;
10831
10832 if (mips_flag_mdebug < 0)
10833 {
10834#ifdef OBJ_MAYBE_ECOFF
10835 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
10836 mips_flag_mdebug = 1;

--- 39 unchanged lines hidden (view full) ---

10876#ifndef NO_ECOFF_DEBUGGING
10877 if (ECOFF_DEBUGGING
10878 && mips_debug != 0
10879 && ! ecoff_debugging_seen)
10880 flag_keep_locals = 1;
10881#endif
10882}
10883
11456 mips_opts.gp32 = file_mips_gp32;
11457 mips_opts.fp32 = file_mips_fp32;
11458
11459 if (mips_flag_mdebug < 0)
11460 {
11461#ifdef OBJ_MAYBE_ECOFF
11462 if (OUTPUT_FLAVOR == bfd_target_ecoff_flavour)
11463 mips_flag_mdebug = 1;

--- 39 unchanged lines hidden (view full) ---

11503#ifndef NO_ECOFF_DEBUGGING
11504 if (ECOFF_DEBUGGING
11505 && mips_debug != 0
11506 && ! ecoff_debugging_seen)
11507 flag_keep_locals = 1;
11508#endif
11509}
11510
10884/* Sort any unmatched HI16_S relocs so that they immediately precede
10885 the corresponding LO reloc. This is called before md_apply_fix3 and
10886 tc_gen_reloc. Unmatched HI16_S relocs can only be generated by
10887 explicit use of the %hi modifier. */
11511/* Sort any unmatched HI16 and GOT16 relocs so that they immediately precede
11512 the corresponding LO16 reloc. This is called before md_apply_fix3 and
11513 tc_gen_reloc. Unmatched relocs can only be generated by use of explicit
11514 relocation operators.
10888
11515
11516 For our purposes, a %lo() expression matches a %got() or %hi()
11517 expression if:
11518
11519 (a) it refers to the same symbol; and
11520 (b) the offset applied in the %lo() expression is no lower than
11521 the offset applied in the %got() or %hi().
11522
11523 (b) allows us to cope with code like:
11524
11525 lui $4,%hi(foo)
11526 lh $4,%lo(foo+2)($4)
11527
11528 ...which is legal on RELA targets, and has a well-defined behaviour
11529 if the user knows that adding 2 to "foo" will not induce a carry to
11530 the high 16 bits.
11531
11532 When several %lo()s match a particular %got() or %hi(), we use the
11533 following rules to distinguish them:
11534
11535 (1) %lo()s with smaller offsets are a better match than %lo()s with
11536 higher offsets.
11537
11538 (2) %lo()s with no matching %got() or %hi() are better than those
11539 that already have a matching %got() or %hi().
11540
11541 (3) later %lo()s are better than earlier %lo()s.
11542
11543 These rules are applied in order.
11544
11545 (1) means, among other things, that %lo()s with identical offsets are
11546 chosen if they exist.
11547
11548 (2) means that we won't associate several high-part relocations with
11549 the same low-part relocation unless there's no alternative. Having
11550 several high parts for the same low part is a GNU extension; this rule
11551 allows careful users to avoid it.
11552
11553 (3) is purely cosmetic. mips_hi_fixup_list is is in reverse order,
11554 with the last high-part relocation being at the front of the list.
11555 It therefore makes sense to choose the last matching low-part
11556 relocation, all other things being equal. It's also easier
11557 to code that way. */
11558
10889void
10890mips_frob_file (void)
10891{
10892 struct mips_hi_fixup *l;
10893
10894 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
10895 {
10896 segment_info_type *seginfo;
11559void
11560mips_frob_file (void)
11561{
11562 struct mips_hi_fixup *l;
11563
11564 for (l = mips_hi_fixup_list; l != NULL; l = l->next)
11565 {
11566 segment_info_type *seginfo;
10897 int pass;
11567 bfd_boolean matched_lo_p;
11568 fixS **hi_pos, **lo_pos, **pos;
10898
10899 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
10900
10901 /* If a GOT16 relocation turns out to be against a global symbol,
10902 there isn't supposed to be a matching LO. */
10903 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
10904 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
10905 continue;
10906
10907 /* Check quickly whether the next fixup happens to be a matching %lo. */
10908 if (fixup_has_matching_lo_p (l->fixp))
10909 continue;
10910
11569
11570 assert (reloc_needs_lo_p (l->fixp->fx_r_type));
11571
11572 /* If a GOT16 relocation turns out to be against a global symbol,
11573 there isn't supposed to be a matching LO. */
11574 if (l->fixp->fx_r_type == BFD_RELOC_MIPS_GOT16
11575 && !pic_need_relax (l->fixp->fx_addsy, l->seg))
11576 continue;
11577
11578 /* Check quickly whether the next fixup happens to be a matching %lo. */
11579 if (fixup_has_matching_lo_p (l->fixp))
11580 continue;
11581
10911 /* Look through the fixups for this segment for a matching %lo.
10912 When we find one, move the %hi just in front of it. We do
10913 this in two passes. In the first pass, we try to find a
10914 unique %lo. In the second pass, we permit multiple %hi
10915 relocs for a single %lo (this is a GNU extension). */
10916 seginfo = seg_info (l->seg);
11582 seginfo = seg_info (l->seg);
10917 for (pass = 0; pass < 2; pass++)
11583
11584 /* Set HI_POS to the position of this relocation in the chain.
11585 Set LO_POS to the position of the chosen low-part relocation.
11586 MATCHED_LO_P is true on entry to the loop if *POS is a low-part
11587 relocation that matches an immediately-preceding high-part
11588 relocation. */
11589 hi_pos = NULL;
11590 lo_pos = NULL;
11591 matched_lo_p = FALSE;
11592 for (pos = &seginfo->fix_root; *pos != NULL; pos = &(*pos)->fx_next)
10918 {
11593 {
10919 fixS *f, *prev;
11594 if (*pos == l->fixp)
11595 hi_pos = pos;
10920
11596
10921 prev = NULL;
10922 for (f = seginfo->fix_root; f != NULL; f = f->fx_next)
10923 {
10924 /* Check whether this is a %lo fixup which matches l->fixp. */
10925 if (f->fx_r_type == BFD_RELOC_LO16
10926 && f->fx_addsy == l->fixp->fx_addsy
10927 && f->fx_offset == l->fixp->fx_offset
10928 && (pass == 1
10929 || prev == NULL
10930 || !reloc_needs_lo_p (prev->fx_r_type)
10931 || !fixup_has_matching_lo_p (prev)))
10932 {
10933 fixS **pf;
11597 if ((*pos)->fx_r_type == BFD_RELOC_LO16
11598 && (*pos)->fx_addsy == l->fixp->fx_addsy
11599 && (*pos)->fx_offset >= l->fixp->fx_offset
11600 && (lo_pos == NULL
11601 || (*pos)->fx_offset < (*lo_pos)->fx_offset
11602 || (!matched_lo_p
11603 && (*pos)->fx_offset == (*lo_pos)->fx_offset)))
11604 lo_pos = pos;
10934
11605
10935 /* Move l->fixp before f. */
10936 for (pf = &seginfo->fix_root;
10937 *pf != l->fixp;
10938 pf = &(*pf)->fx_next)
10939 assert (*pf != NULL);
11606 matched_lo_p = (reloc_needs_lo_p ((*pos)->fx_r_type)
11607 && fixup_has_matching_lo_p (*pos));
11608 }
10940
11609
10941 *pf = l->fixp->fx_next;
11610 /* If we found a match, remove the high-part relocation from its
11611 current position and insert it before the low-part relocation.
11612 Make the offsets match so that fixup_has_matching_lo_p()
11613 will return true.
10942
11614
10943 l->fixp->fx_next = f;
10944 if (prev == NULL)
10945 seginfo->fix_root = l->fixp;
10946 else
10947 prev->fx_next = l->fixp;
10948
10949 break;
10950 }
10951
10952 prev = f;
11615 We don't warn about unmatched high-part relocations since some
11616 versions of gcc have been known to emit dead "lui ...%hi(...)"
11617 instructions. */
11618 if (lo_pos != NULL)
11619 {
11620 l->fixp->fx_offset = (*lo_pos)->fx_offset;
11621 if (l->fixp->fx_next != *lo_pos)
11622 {
11623 *hi_pos = l->fixp->fx_next;
11624 l->fixp->fx_next = *lo_pos;
11625 *lo_pos = l->fixp;
10953 }
11626 }
10954
10955 if (f != NULL)
10956 break;
10957
10958#if 0 /* GCC code motion plus incomplete dead code elimination
10959 can leave a %hi without a %lo. */
10960 if (pass == 1)
10961 as_warn_where (l->fixp->fx_file, l->fixp->fx_line,
10962 _("Unmatched %%hi reloc"));
10963#endif
10964 }
10965 }
10966}
10967
11627 }
11628 }
11629}
11630
10968/* When generating embedded PIC code we need to use a special
10969 relocation to represent the difference of two symbols in the .text
10970 section (switch tables use a difference of this sort). See
10971 include/coff/mips.h for details. This macro checks whether this
10972 fixup requires the special reloc. */
10973#define SWITCH_TABLE(fixp) \
10974 ((fixp)->fx_r_type == BFD_RELOC_32 \
10975 && OUTPUT_FLAVOR != bfd_target_elf_flavour \
10976 && (fixp)->fx_addsy != NULL \
10977 && (fixp)->fx_subsy != NULL \
10978 && S_GET_SEGMENT ((fixp)->fx_addsy) == text_section \
10979 && S_GET_SEGMENT ((fixp)->fx_subsy) == text_section)
10980
10981/* When generating embedded PIC code we must keep all PC relative
10982 relocations, in case the linker has to relax a call. We also need
10983 to keep relocations for switch table entries.
10984
10985 We may have combined relocations without symbols in the N32/N64 ABI.
11631/* We may have combined relocations without symbols in the N32/N64 ABI.
10986 We have to prevent gas from dropping them. */
10987
10988int
10989mips_force_relocation (fixS *fixp)
10990{
10991 if (generic_force_reloc (fixp))
10992 return 1;
10993
10994 if (HAVE_NEWABI
10995 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
10996 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
10997 || fixp->fx_r_type == BFD_RELOC_HI16_S
10998 || fixp->fx_r_type == BFD_RELOC_LO16))
10999 return 1;
11000
11632 We have to prevent gas from dropping them. */
11633
11634int
11635mips_force_relocation (fixS *fixp)
11636{
11637 if (generic_force_reloc (fixp))
11638 return 1;
11639
11640 if (HAVE_NEWABI
11641 && S_GET_SEGMENT (fixp->fx_addsy) == bfd_abs_section_ptr
11642 && (fixp->fx_r_type == BFD_RELOC_MIPS_SUB
11643 || fixp->fx_r_type == BFD_RELOC_HI16_S
11644 || fixp->fx_r_type == BFD_RELOC_LO16))
11645 return 1;
11646
11001 return (mips_pic == EMBEDDED_PIC
11002 && (fixp->fx_pcrel
11003 || SWITCH_TABLE (fixp)
11004 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S
11005 || fixp->fx_r_type == BFD_RELOC_PCREL_LO16));
11647 return 0;
11006}
11007
11648}
11649
11008/* This hook is called before a fix is simplified. We don't really
11009 decide whether to skip a fix here. Rather, we turn global symbols
11010 used as branch targets into local symbols, such that they undergo
11011 simplification. We can only do this if the symbol is defined and
11012 it is in the same section as the branch. If this doesn't hold, we
11013 emit a better error message than just saying the relocation is not
11014 valid for the selected object format.
11015
11016 FIXP is the fix-up we're going to try to simplify, SEG is the
11017 segment in which the fix up occurs. The return value should be
11018 non-zero to indicate the fix-up is valid for further
11019 simplifications. */
11020
11021int
11022mips_validate_fix (struct fix *fixP, asection *seg)
11023{
11024 /* There's a lot of discussion on whether it should be possible to
11025 use R_MIPS_PC16 to represent branch relocations. The outcome
11026 seems to be that it can, but gas/bfd are very broken in creating
11027 RELA relocations for this, so for now we only accept branches to
11028 symbols in the same section. Anything else is of dubious value,
11029 since there's no guarantee that at link time the symbol would be
11030 in range. Even for branches to local symbols this is arguably
11031 wrong, since it we assume the symbol is not going to be
11032 overridden, which should be possible per ELF library semantics,
11033 but then, there isn't a dynamic relocation that could be used to
11034 this effect, and the target would likely be out of range as well.
11035
11036 Unfortunately, it seems that there is too much code out there
11037 that relies on branches to symbols that are global to be resolved
11038 as if they were local, like the IRIX tools do, so we do it as
11039 well, but with a warning so that people are reminded to fix their
11040 code. If we ever get back to using R_MIPS_PC16 for branch
11041 targets, this entire block should go away (and probably the
11042 whole function). */
11043
11044 if (fixP->fx_r_type == BFD_RELOC_16_PCREL_S2
11045 && (((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
11046 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
11047 && mips_pic != EMBEDDED_PIC)
11048 || bfd_reloc_type_lookup (stdoutput, BFD_RELOC_16_PCREL_S2) == NULL)
11049 && fixP->fx_addsy)
11050 {
11051 if (! S_IS_DEFINED (fixP->fx_addsy))
11052 {
11053 as_bad_where (fixP->fx_file, fixP->fx_line,
11054 _("Cannot branch to undefined symbol."));
11055 /* Avoid any further errors about this fixup. */
11056 fixP->fx_done = 1;
11057 }
11058 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
11059 {
11060 as_bad_where (fixP->fx_file, fixP->fx_line,
11061 _("Cannot branch to symbol in another section."));
11062 fixP->fx_done = 1;
11063 }
11064 else if (S_IS_EXTERNAL (fixP->fx_addsy))
11065 {
11066 symbolS *sym = fixP->fx_addsy;
11067
11068 if (mips_pic == SVR4_PIC)
11069 as_warn_where (fixP->fx_file, fixP->fx_line,
11070 _("Pretending global symbol used as branch target is local."));
11071
11072 fixP->fx_addsy = symbol_create (S_GET_NAME (sym),
11073 S_GET_SEGMENT (sym),
11074 S_GET_VALUE (sym),
11075 symbol_get_frag (sym));
11076 copy_symbol_attributes (fixP->fx_addsy, sym);
11077 S_CLEAR_EXTERNAL (fixP->fx_addsy);
11078 assert (symbol_resolved_p (sym));
11079 symbol_mark_resolved (fixP->fx_addsy);
11080 }
11081 }
11082
11083 return 1;
11084}
11085
11086/* Apply a fixup to the object file. */
11087
11088void
11089md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11090{
11091 bfd_byte *buf;
11092 long insn;
11650/* Apply a fixup to the object file. */
11651
11652void
11653md_apply_fix3 (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
11654{
11655 bfd_byte *buf;
11656 long insn;
11093 static int previous_fx_r_type = 0;
11094 reloc_howto_type *howto;
11095
11096 /* We ignore generic BFD relocations we don't know about. */
11097 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11098 if (! howto)
11099 return;
11100
11101 assert (fixP->fx_size == 4
11102 || fixP->fx_r_type == BFD_RELOC_16
11103 || fixP->fx_r_type == BFD_RELOC_64
11104 || fixP->fx_r_type == BFD_RELOC_CTOR
11105 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11106 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11107 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11108
11109 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11110
11657 reloc_howto_type *howto;
11658
11659 /* We ignore generic BFD relocations we don't know about. */
11660 howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
11661 if (! howto)
11662 return;
11663
11664 assert (fixP->fx_size == 4
11665 || fixP->fx_r_type == BFD_RELOC_16
11666 || fixP->fx_r_type == BFD_RELOC_64
11667 || fixP->fx_r_type == BFD_RELOC_CTOR
11668 || fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11669 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
11670 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY);
11671
11672 buf = (bfd_byte *) (fixP->fx_frag->fr_literal + fixP->fx_where);
11673
11111 /* We are not done if this is a composite relocation to set up gp. */
11112 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel
11113 && !(fixP->fx_r_type == BFD_RELOC_MIPS_SUB
11114 || (fixP->fx_r_type == BFD_RELOC_64
11115 && (previous_fx_r_type == BFD_RELOC_GPREL32
11116 || previous_fx_r_type == BFD_RELOC_GPREL16))
11117 || (previous_fx_r_type == BFD_RELOC_MIPS_SUB
11118 && (fixP->fx_r_type == BFD_RELOC_HI16_S
11119 || fixP->fx_r_type == BFD_RELOC_LO16))))
11674 assert (! fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2);
11675
11676 /* Don't treat parts of a composite relocation as done. There are two
11677 reasons for this:
11678
11679 (1) The second and third parts will be against 0 (RSS_UNDEF) but
11680 should nevertheless be emitted if the first part is.
11681
11682 (2) In normal usage, composite relocations are never assembly-time
11683 constants. The easiest way of dealing with the pathological
11684 exceptions is to generate a relocation against STN_UNDEF and
11685 leave everything up to the linker. */
11686 if (fixP->fx_addsy == NULL && ! fixP->fx_pcrel && fixP->fx_tcbit == 0)
11120 fixP->fx_done = 1;
11687 fixP->fx_done = 1;
11121 previous_fx_r_type = fixP->fx_r_type;
11122
11123 switch (fixP->fx_r_type)
11124 {
11125 case BFD_RELOC_MIPS_JMP:
11126 case BFD_RELOC_MIPS_SHIFT5:
11127 case BFD_RELOC_MIPS_SHIFT6:
11128 case BFD_RELOC_MIPS_GOT_DISP:
11129 case BFD_RELOC_MIPS_GOT_PAGE:

--- 15 unchanged lines hidden (view full) ---

11145 case BFD_RELOC_MIPS_CALL16:
11146 case BFD_RELOC_MIPS_GOT16:
11147 case BFD_RELOC_GPREL32:
11148 case BFD_RELOC_MIPS_GOT_HI16:
11149 case BFD_RELOC_MIPS_GOT_LO16:
11150 case BFD_RELOC_MIPS_CALL_HI16:
11151 case BFD_RELOC_MIPS_CALL_LO16:
11152 case BFD_RELOC_MIPS16_GPREL:
11688
11689 switch (fixP->fx_r_type)
11690 {
11691 case BFD_RELOC_MIPS_JMP:
11692 case BFD_RELOC_MIPS_SHIFT5:
11693 case BFD_RELOC_MIPS_SHIFT6:
11694 case BFD_RELOC_MIPS_GOT_DISP:
11695 case BFD_RELOC_MIPS_GOT_PAGE:

--- 15 unchanged lines hidden (view full) ---

11711 case BFD_RELOC_MIPS_CALL16:
11712 case BFD_RELOC_MIPS_GOT16:
11713 case BFD_RELOC_GPREL32:
11714 case BFD_RELOC_MIPS_GOT_HI16:
11715 case BFD_RELOC_MIPS_GOT_LO16:
11716 case BFD_RELOC_MIPS_CALL_HI16:
11717 case BFD_RELOC_MIPS_CALL_LO16:
11718 case BFD_RELOC_MIPS16_GPREL:
11153 if (fixP->fx_pcrel)
11154 as_bad_where (fixP->fx_file, fixP->fx_line,
11155 _("Invalid PC relative reloc"));
11156 /* Nothing needed to do. The value comes from the reloc entry */
11157 break;
11158
11159 case BFD_RELOC_MIPS16_JMP:
11160 /* We currently always generate a reloc against a symbol, which
11161 means that we don't want an addend even if the symbol is
11162 defined. */
11163 *valP = 0;
11164 break;
11165
11719 /* Nothing needed to do. The value comes from the reloc entry */
11720 break;
11721
11722 case BFD_RELOC_MIPS16_JMP:
11723 /* We currently always generate a reloc against a symbol, which
11724 means that we don't want an addend even if the symbol is
11725 defined. */
11726 *valP = 0;
11727 break;
11728
11166 case BFD_RELOC_PCREL_HI16_S:
11167 /* The addend for this is tricky if it is internal, so we just
11168 do everything here rather than in bfd_install_relocation. */
11169 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11170 break;
11171 if (fixP->fx_addsy
11172 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11173 {
11174 /* For an external symbol adjust by the address to make it
11175 pcrel_offset. We use the address of the RELLO reloc
11176 which follows this one. */
11177 *valP += (fixP->fx_next->fx_frag->fr_address
11178 + fixP->fx_next->fx_where);
11179 }
11180 *valP = ((*valP + 0x8000) >> 16) & 0xffff;
11181 if (target_big_endian)
11182 buf += 2;
11183 md_number_to_chars (buf, *valP, 2);
11184 break;
11185
11186 case BFD_RELOC_PCREL_LO16:
11187 /* The addend for this is tricky if it is internal, so we just
11188 do everything here rather than in bfd_install_relocation. */
11189 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && !fixP->fx_done)
11190 break;
11191 if (fixP->fx_addsy
11192 && (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_SECTION_SYM) == 0)
11193 *valP += fixP->fx_frag->fr_address + fixP->fx_where;
11194 if (target_big_endian)
11195 buf += 2;
11196 md_number_to_chars (buf, *valP, 2);
11197 break;
11198
11199 case BFD_RELOC_64:
11200 /* This is handled like BFD_RELOC_32, but we output a sign
11201 extended value if we are only 32 bits. */
11729 case BFD_RELOC_64:
11730 /* This is handled like BFD_RELOC_32, but we output a sign
11731 extended value if we are only 32 bits. */
11202 if (fixP->fx_done
11203 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11732 if (fixP->fx_done)
11204 {
11205 if (8 <= sizeof (valueT))
11733 {
11734 if (8 <= sizeof (valueT))
11206 md_number_to_chars (buf, *valP, 8);
11735 md_number_to_chars ((char *) buf, *valP, 8);
11207 else
11208 {
11209 valueT hiv;
11210
11211 if ((*valP & 0x80000000) != 0)
11212 hiv = 0xffffffff;
11213 else
11214 hiv = 0;
11736 else
11737 {
11738 valueT hiv;
11739
11740 if ((*valP & 0x80000000) != 0)
11741 hiv = 0xffffffff;
11742 else
11743 hiv = 0;
11215 md_number_to_chars ((char *)(buf + target_big_endian ? 4 : 0),
11744 md_number_to_chars ((char *)(buf + (target_big_endian ? 4 : 0)),
11216 *valP, 4);
11745 *valP, 4);
11217 md_number_to_chars ((char *)(buf + target_big_endian ? 0 : 4),
11746 md_number_to_chars ((char *)(buf + (target_big_endian ? 0 : 4)),
11218 hiv, 4);
11219 }
11220 }
11221 break;
11222
11223 case BFD_RELOC_RVA:
11224 case BFD_RELOC_32:
11225 /* If we are deleting this reloc entry, we must fill in the
11226 value now. This can happen if we have a .word which is not
11747 hiv, 4);
11748 }
11749 }
11750 break;
11751
11752 case BFD_RELOC_RVA:
11753 case BFD_RELOC_32:
11754 /* If we are deleting this reloc entry, we must fill in the
11755 value now. This can happen if we have a .word which is not
11227 resolved when it appears but is later defined. We also need
11228 to fill in the value if this is an embedded PIC switch table
11229 entry. */
11230 if (fixP->fx_done
11231 || (mips_pic == EMBEDDED_PIC && SWITCH_TABLE (fixP)))
11232 md_number_to_chars (buf, *valP, 4);
11756 resolved when it appears but is later defined. */
11757 if (fixP->fx_done)
11758 md_number_to_chars ((char *) buf, *valP, 4);
11233 break;
11234
11235 case BFD_RELOC_16:
11236 /* If we are deleting this reloc entry, we must fill in the
11237 value now. */
11759 break;
11760
11761 case BFD_RELOC_16:
11762 /* If we are deleting this reloc entry, we must fill in the
11763 value now. */
11238 assert (fixP->fx_size == 2);
11239 if (fixP->fx_done)
11764 if (fixP->fx_done)
11240 md_number_to_chars (buf, *valP, 2);
11765 md_number_to_chars ((char *) buf, *valP, 2);
11241 break;
11242
11243 case BFD_RELOC_LO16:
11766 break;
11767
11768 case BFD_RELOC_LO16:
11769 /* FIXME: Now that embedded-PIC is gone, some of this code/comment
11770 may be safe to remove, but if so it's not obvious. */
11244 /* When handling an embedded PIC switch statement, we can wind
11245 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11246 if (fixP->fx_done)
11247 {
11248 if (*valP + 0x8000 > 0xffff)
11249 as_bad_where (fixP->fx_file, fixP->fx_line,
11250 _("relocation overflow"));
11251 if (target_big_endian)
11252 buf += 2;
11771 /* When handling an embedded PIC switch statement, we can wind
11772 up deleting a LO16 reloc. See the 'o' case in mips_ip. */
11773 if (fixP->fx_done)
11774 {
11775 if (*valP + 0x8000 > 0xffff)
11776 as_bad_where (fixP->fx_file, fixP->fx_line,
11777 _("relocation overflow"));
11778 if (target_big_endian)
11779 buf += 2;
11253 md_number_to_chars (buf, *valP, 2);
11780 md_number_to_chars ((char *) buf, *valP, 2);
11254 }
11255 break;
11256
11257 case BFD_RELOC_16_PCREL_S2:
11258 if ((*valP & 0x3) != 0)
11259 as_bad_where (fixP->fx_file, fixP->fx_line,
11781 }
11782 break;
11783
11784 case BFD_RELOC_16_PCREL_S2:
11785 if ((*valP & 0x3) != 0)
11786 as_bad_where (fixP->fx_file, fixP->fx_line,
11260 _("Branch to odd address (%lx)"), (long) *valP);
11787 _("Branch to misaligned address (%lx)"), (long) *valP);
11261
11262 /*
11263 * We need to save the bits in the instruction since fixup_segment()
11264 * might be deleting the relocation entry (i.e., a branch within
11265 * the current segment).
11266 */
11267 if (! fixP->fx_done)
11268 break;
11269
11270 /* update old instruction data */
11271 if (target_big_endian)
11272 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11273 else
11274 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11275
11276 if (*valP + 0x20000 <= 0x3ffff)
11277 {
11278 insn |= (*valP >> 2) & 0xffff;
11788
11789 /*
11790 * We need to save the bits in the instruction since fixup_segment()
11791 * might be deleting the relocation entry (i.e., a branch within
11792 * the current segment).
11793 */
11794 if (! fixP->fx_done)
11795 break;
11796
11797 /* update old instruction data */
11798 if (target_big_endian)
11799 insn = (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
11800 else
11801 insn = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0];
11802
11803 if (*valP + 0x20000 <= 0x3ffff)
11804 {
11805 insn |= (*valP >> 2) & 0xffff;
11279 md_number_to_chars (buf, insn, 4);
11806 md_number_to_chars ((char *) buf, insn, 4);
11280 }
11281 else if (mips_pic == NO_PIC
11282 && fixP->fx_done
11283 && fixP->fx_frag->fr_address >= text_section->vma
11284 && (fixP->fx_frag->fr_address
11285 < text_section->vma + text_section->_raw_size)
11286 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11287 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */

--- 5 unchanged lines hidden (view full) ---

11293 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11294 insn = 0x0c000000; /* jal */
11295 else
11296 insn = 0x08000000; /* j */
11297 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11298 fixP->fx_done = 0;
11299 fixP->fx_addsy = section_symbol (text_section);
11300 *valP += md_pcrel_from (fixP);
11807 }
11808 else if (mips_pic == NO_PIC
11809 && fixP->fx_done
11810 && fixP->fx_frag->fr_address >= text_section->vma
11811 && (fixP->fx_frag->fr_address
11812 < text_section->vma + text_section->_raw_size)
11813 && ((insn & 0xffff0000) == 0x10000000 /* beq $0,$0 */
11814 || (insn & 0xffff0000) == 0x04010000 /* bgez $0 */

--- 5 unchanged lines hidden (view full) ---

11820 if ((insn & 0xffff0000) == 0x04110000) /* bgezal $0 */
11821 insn = 0x0c000000; /* jal */
11822 else
11823 insn = 0x08000000; /* j */
11824 fixP->fx_r_type = BFD_RELOC_MIPS_JMP;
11825 fixP->fx_done = 0;
11826 fixP->fx_addsy = section_symbol (text_section);
11827 *valP += md_pcrel_from (fixP);
11301 md_number_to_chars (buf, insn, 4);
11828 md_number_to_chars ((char *) buf, insn, 4);
11302 }
11303 else
11304 {
11305 /* If we got here, we have branch-relaxation disabled,
11306 and there's nothing we can do to fix this instruction
11307 without turning it into a longer sequence. */
11308 as_bad_where (fixP->fx_file, fixP->fx_line,
11309 _("Branch out of range"));

--- 15 unchanged lines hidden (view full) ---

11325 default:
11326 internalError ();
11327 }
11328
11329 /* Remember value for tc_gen_reloc. */
11330 fixP->fx_addnumber = *valP;
11331}
11332
11829 }
11830 else
11831 {
11832 /* If we got here, we have branch-relaxation disabled,
11833 and there's nothing we can do to fix this instruction
11834 without turning it into a longer sequence. */
11835 as_bad_where (fixP->fx_file, fixP->fx_line,
11836 _("Branch out of range"));

--- 15 unchanged lines hidden (view full) ---

11852 default:
11853 internalError ();
11854 }
11855
11856 /* Remember value for tc_gen_reloc. */
11857 fixP->fx_addnumber = *valP;
11858}
11859
11333#if 0
11334void
11335printInsn (unsigned long oc)
11336{
11337 const struct mips_opcode *p;
11338 int treg, sreg, dreg, shamt;
11339 short imm;
11340 const char *args;
11341 int i;
11342
11343 for (i = 0; i < NUMOPCODES; ++i)
11344 {
11345 p = &mips_opcodes[i];
11346 if (((oc & p->mask) == p->match) && (p->pinfo != INSN_MACRO))
11347 {
11348 printf ("%08lx %s\t", oc, p->name);
11349 treg = (oc >> 16) & 0x1f;
11350 sreg = (oc >> 21) & 0x1f;
11351 dreg = (oc >> 11) & 0x1f;
11352 shamt = (oc >> 6) & 0x1f;
11353 imm = oc;
11354 for (args = p->args;; ++args)
11355 {
11356 switch (*args)
11357 {
11358 case '\0':
11359 printf ("\n");
11360 break;
11361
11362 case ',':
11363 case '(':
11364 case ')':
11365 printf ("%c", *args);
11366 continue;
11367
11368 case 'r':
11369 assert (treg == sreg);
11370 printf ("$%d,$%d", treg, sreg);
11371 continue;
11372
11373 case 'd':
11374 case 'G':
11375 printf ("$%d", dreg);
11376 continue;
11377
11378 case 't':
11379 case 'E':
11380 printf ("$%d", treg);
11381 continue;
11382
11383 case 'k':
11384 printf ("0x%x", treg);
11385 continue;
11386
11387 case 'b':
11388 case 's':
11389 printf ("$%d", sreg);
11390 continue;
11391
11392 case 'a':
11393 printf ("0x%08lx", oc & 0x1ffffff);
11394 continue;
11395
11396 case 'i':
11397 case 'j':
11398 case 'o':
11399 case 'u':
11400 printf ("%d", imm);
11401 continue;
11402
11403 case '<':
11404 case '>':
11405 printf ("$%d", shamt);
11406 continue;
11407
11408 default:
11409 internalError ();
11410 }
11411 break;
11412 }
11413 return;
11414 }
11415 }
11416 printf (_("%08lx UNDEFINED\n"), oc);
11417}
11418#endif
11419
11420static symbolS *
11421get_symbol (void)
11422{
11423 int c;
11424 char *name;
11425 symbolS *p;
11426
11427 name = input_line_pointer;

--- 4 unchanged lines hidden (view full) ---

11432}
11433
11434/* Align the current frag to a given power of two. The MIPS assembler
11435 also automatically adjusts any preceding label. */
11436
11437static void
11438mips_align (int to, int fill, symbolS *label)
11439{
11860static symbolS *
11861get_symbol (void)
11862{
11863 int c;
11864 char *name;
11865 symbolS *p;
11866
11867 name = input_line_pointer;

--- 4 unchanged lines hidden (view full) ---

11872}
11873
11874/* Align the current frag to a given power of two. The MIPS assembler
11875 also automatically adjusts any preceding label. */
11876
11877static void
11878mips_align (int to, int fill, symbolS *label)
11879{
11440 mips_emit_delays (FALSE);
11880 mips_emit_delays ();
11441 frag_align (to, fill, 0);
11442 record_alignment (now_seg, to);
11443 if (label != NULL)
11444 {
11445 assert (S_GET_SEGMENT (label) == now_seg);
11446 symbol_set_frag (label, frag_now);
11447 S_SET_VALUE (label, (valueT) frag_now_fix ());
11448 }

--- 45 unchanged lines hidden (view full) ---

11494 else
11495 {
11496 auto_align = 0;
11497 }
11498
11499 demand_empty_rest_of_line ();
11500}
11501
11881 frag_align (to, fill, 0);
11882 record_alignment (now_seg, to);
11883 if (label != NULL)
11884 {
11885 assert (S_GET_SEGMENT (label) == now_seg);
11886 symbol_set_frag (label, frag_now);
11887 S_SET_VALUE (label, (valueT) frag_now_fix ());
11888 }

--- 45 unchanged lines hidden (view full) ---

11934 else
11935 {
11936 auto_align = 0;
11937 }
11938
11939 demand_empty_rest_of_line ();
11940}
11941
11502void
11503mips_flush_pending_output (void)
11504{
11505 mips_emit_delays (FALSE);
11506 mips_clear_insn_labels ();
11507}
11508
11509static void
11510s_change_sec (int sec)
11511{
11512 segT seg;
11513
11942static void
11943s_change_sec (int sec)
11944{
11945 segT seg;
11946
11514 /* When generating embedded PIC code, we only use the .text, .lit8,
11515 .sdata and .sbss sections. We change the .data and .rdata
11516 pseudo-ops to use .sdata. */
11517 if (mips_pic == EMBEDDED_PIC
11518 && (sec == 'd' || sec == 'r'))
11519 sec = 's';
11520
11521#ifdef OBJ_ELF
11522 /* The ELF backend needs to know that we are changing sections, so
11523 that .previous works correctly. We could do something like check
11524 for an obj_section_change_hook macro, but that might be confusing
11525 as it would not be appropriate to use it in the section changing
11526 functions in read.c, since obj-elf.c intercepts those. FIXME:
11527 This should be cleaner, somehow. */
11528 obj_elf_section_change_hook ();
11529#endif
11530
11947#ifdef OBJ_ELF
11948 /* The ELF backend needs to know that we are changing sections, so
11949 that .previous works correctly. We could do something like check
11950 for an obj_section_change_hook macro, but that might be confusing
11951 as it would not be appropriate to use it in the section changing
11952 functions in read.c, since obj-elf.c intercepts those. FIXME:
11953 This should be cleaner, somehow. */
11954 obj_elf_section_change_hook ();
11955#endif
11956
11531 mips_emit_delays (FALSE);
11957 mips_emit_delays ();
11532 switch (sec)
11533 {
11534 case 't':
11535 s_text (0);
11536 break;
11537 case 'd':
11538 s_data (0);
11539 break;
11540 case 'b':
11541 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11542 demand_empty_rest_of_line ();
11543 break;
11544
11545 case 'r':
11958 switch (sec)
11959 {
11960 case 't':
11961 s_text (0);
11962 break;
11963 case 'd':
11964 s_data (0);
11965 break;
11966 case 'b':
11967 subseg_set (bss_section, (subsegT) get_absolute_expression ());
11968 demand_empty_rest_of_line ();
11969 break;
11970
11971 case 'r':
11546 if (USE_GLOBAL_POINTER_OPT)
11972 seg = subseg_new (RDATA_SECTION_NAME,
11973 (subsegT) get_absolute_expression ());
11974 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11547 {
11975 {
11548 seg = subseg_new (RDATA_SECTION_NAME,
11549 (subsegT) get_absolute_expression ());
11550 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11551 {
11552 bfd_set_section_flags (stdoutput, seg,
11553 (SEC_ALLOC
11554 | SEC_LOAD
11555 | SEC_READONLY
11556 | SEC_RELOC
11557 | SEC_DATA));
11558 if (strcmp (TARGET_OS, "elf") != 0)
11559 record_alignment (seg, 4);
11560 }
11561 demand_empty_rest_of_line ();
11976 bfd_set_section_flags (stdoutput, seg, (SEC_ALLOC | SEC_LOAD
11977 | SEC_READONLY | SEC_RELOC
11978 | SEC_DATA));
11979 if (strcmp (TARGET_OS, "elf") != 0)
11980 record_alignment (seg, 4);
11562 }
11981 }
11563 else
11564 {
11565 as_bad (_("No read only data section in this object file format"));
11566 demand_empty_rest_of_line ();
11567 return;
11568 }
11982 demand_empty_rest_of_line ();
11569 break;
11570
11571 case 's':
11983 break;
11984
11985 case 's':
11572 if (USE_GLOBAL_POINTER_OPT)
11986 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11987 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11573 {
11988 {
11574 seg = subseg_new (".sdata", (subsegT) get_absolute_expression ());
11575 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
11576 {
11577 bfd_set_section_flags (stdoutput, seg,
11578 SEC_ALLOC | SEC_LOAD | SEC_RELOC
11579 | SEC_DATA);
11580 if (strcmp (TARGET_OS, "elf") != 0)
11581 record_alignment (seg, 4);
11582 }
11583 demand_empty_rest_of_line ();
11584 break;
11989 bfd_set_section_flags (stdoutput, seg,
11990 SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_DATA);
11991 if (strcmp (TARGET_OS, "elf") != 0)
11992 record_alignment (seg, 4);
11585 }
11993 }
11586 else
11587 {
11588 as_bad (_("Global pointers not supported; recompile -G 0"));
11589 demand_empty_rest_of_line ();
11590 return;
11591 }
11994 demand_empty_rest_of_line ();
11995 break;
11592 }
11593
11594 auto_align = 1;
11595}
11596
11597void
11598s_change_section (int ignore ATTRIBUTE_UNUSED)
11599{

--- 76 unchanged lines hidden (view full) ---

11676}
11677
11678static void
11679s_cons (int log_size)
11680{
11681 symbolS *label;
11682
11683 label = insn_labels != NULL ? insn_labels->label : NULL;
11996 }
11997
11998 auto_align = 1;
11999}
12000
12001void
12002s_change_section (int ignore ATTRIBUTE_UNUSED)
12003{

--- 76 unchanged lines hidden (view full) ---

12080}
12081
12082static void
12083s_cons (int log_size)
12084{
12085 symbolS *label;
12086
12087 label = insn_labels != NULL ? insn_labels->label : NULL;
11684 mips_emit_delays (FALSE);
12088 mips_emit_delays ();
11685 if (log_size > 0 && auto_align)
11686 mips_align (log_size, 0, label);
11687 mips_clear_insn_labels ();
11688 cons (1 << log_size);
11689}
11690
11691static void
11692s_float_cons (int type)
11693{
11694 symbolS *label;
11695
11696 label = insn_labels != NULL ? insn_labels->label : NULL;
11697
12089 if (log_size > 0 && auto_align)
12090 mips_align (log_size, 0, label);
12091 mips_clear_insn_labels ();
12092 cons (1 << log_size);
12093}
12094
12095static void
12096s_float_cons (int type)
12097{
12098 symbolS *label;
12099
12100 label = insn_labels != NULL ? insn_labels->label : NULL;
12101
11698 mips_emit_delays (FALSE);
12102 mips_emit_delays ();
11699
11700 if (auto_align)
11701 {
11702 if (type == 'd')
11703 mips_align (3, 0, label);
11704 else
11705 mips_align (2, 0, label);
11706 }

--- 12 unchanged lines hidden (view full) ---

11719static void
11720s_mips_globl (int x ATTRIBUTE_UNUSED)
11721{
11722 char *name;
11723 int c;
11724 symbolS *symbolP;
11725 flagword flag;
11726
12103
12104 if (auto_align)
12105 {
12106 if (type == 'd')
12107 mips_align (3, 0, label);
12108 else
12109 mips_align (2, 0, label);
12110 }

--- 12 unchanged lines hidden (view full) ---

12123static void
12124s_mips_globl (int x ATTRIBUTE_UNUSED)
12125{
12126 char *name;
12127 int c;
12128 symbolS *symbolP;
12129 flagword flag;
12130
11727 name = input_line_pointer;
11728 c = get_symbol_end ();
11729 symbolP = symbol_find_or_make (name);
11730 *input_line_pointer = c;
11731 SKIP_WHITESPACE ();
11732
11733 /* On Irix 5, every global symbol that is not explicitly labelled as
11734 being a function is apparently labelled as being an object. */
11735 flag = BSF_OBJECT;
11736
11737 if (! is_end_of_line[(unsigned char) *input_line_pointer])
12131 do
11738 {
12132 {
11739 char *secname;
11740 asection *sec;
11741
11742 secname = input_line_pointer;
12133 name = input_line_pointer;
11743 c = get_symbol_end ();
12134 c = get_symbol_end ();
11744 sec = bfd_get_section_by_name (stdoutput, secname);
11745 if (sec == NULL)
11746 as_bad (_("%s: no such section"), secname);
12135 symbolP = symbol_find_or_make (name);
12136 S_SET_EXTERNAL (symbolP);
12137
11747 *input_line_pointer = c;
12138 *input_line_pointer = c;
12139 SKIP_WHITESPACE ();
11748
12140
11749 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
11750 flag = BSF_FUNCTION;
11751 }
12141 /* On Irix 5, every global symbol that is not explicitly labelled as
12142 being a function is apparently labelled as being an object. */
12143 flag = BSF_OBJECT;
11752
12144
11753 symbol_get_bfdsym (symbolP)->flags |= flag;
12145 if (!is_end_of_line[(unsigned char) *input_line_pointer]
12146 && (*input_line_pointer != ','))
12147 {
12148 char *secname;
12149 asection *sec;
11754
12150
11755 S_SET_EXTERNAL (symbolP);
12151 secname = input_line_pointer;
12152 c = get_symbol_end ();
12153 sec = bfd_get_section_by_name (stdoutput, secname);
12154 if (sec == NULL)
12155 as_bad (_("%s: no such section"), secname);
12156 *input_line_pointer = c;
12157
12158 if (sec != NULL && (sec->flags & SEC_CODE) != 0)
12159 flag = BSF_FUNCTION;
12160 }
12161
12162 symbol_get_bfdsym (symbolP)->flags |= flag;
12163
12164 c = *input_line_pointer;
12165 if (c == ',')
12166 {
12167 input_line_pointer++;
12168 SKIP_WHITESPACE ();
12169 if (is_end_of_line[(unsigned char) *input_line_pointer])
12170 c = '\n';
12171 }
12172 }
12173 while (c == ',');
12174
11756 demand_empty_rest_of_line ();
11757}
11758
11759static void
11760s_option (int x ATTRIBUTE_UNUSED)
11761{
11762 char *opt;
11763 char c;

--- 15 unchanged lines hidden (view full) ---

11779 else if (i == 2)
11780 {
11781 mips_pic = SVR4_PIC;
11782 mips_abicalls = TRUE;
11783 }
11784 else
11785 as_bad (_(".option pic%d not supported"), i);
11786
12175 demand_empty_rest_of_line ();
12176}
12177
12178static void
12179s_option (int x ATTRIBUTE_UNUSED)
12180{
12181 char *opt;
12182 char c;

--- 15 unchanged lines hidden (view full) ---

12198 else if (i == 2)
12199 {
12200 mips_pic = SVR4_PIC;
12201 mips_abicalls = TRUE;
12202 }
12203 else
12204 as_bad (_(".option pic%d not supported"), i);
12205
11787 if (USE_GLOBAL_POINTER_OPT && mips_pic == SVR4_PIC)
12206 if (mips_pic == SVR4_PIC)
11788 {
11789 if (g_switch_seen && g_switch_value != 0)
11790 as_warn (_("-G may not be used with SVR4 PIC code"));
11791 g_switch_value = 0;
11792 bfd_set_gp_size (stdoutput, 0);
11793 }
11794 }
11795 else

--- 22 unchanged lines hidden (view full) ---

11818
11819 while (!is_end_of_line[(unsigned char) *input_line_pointer])
11820 ++input_line_pointer;
11821 ch = *input_line_pointer;
11822 *input_line_pointer = '\0';
11823
11824 if (strcmp (name, "reorder") == 0)
11825 {
12207 {
12208 if (g_switch_seen && g_switch_value != 0)
12209 as_warn (_("-G may not be used with SVR4 PIC code"));
12210 g_switch_value = 0;
12211 bfd_set_gp_size (stdoutput, 0);
12212 }
12213 }
12214 else

--- 22 unchanged lines hidden (view full) ---

12237
12238 while (!is_end_of_line[(unsigned char) *input_line_pointer])
12239 ++input_line_pointer;
12240 ch = *input_line_pointer;
12241 *input_line_pointer = '\0';
12242
12243 if (strcmp (name, "reorder") == 0)
12244 {
11826 if (mips_opts.noreorder && prev_nop_frag != NULL)
11827 {
11828 /* If we still have pending nops, we can discard them. The
11829 usual nop handling will insert any that are still
11830 needed. */
11831 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
11832 * (mips_opts.mips16 ? 2 : 4));
11833 prev_nop_frag = NULL;
11834 }
11835 mips_opts.noreorder = 0;
12245 if (mips_opts.noreorder)
12246 end_noreorder ();
11836 }
11837 else if (strcmp (name, "noreorder") == 0)
11838 {
12247 }
12248 else if (strcmp (name, "noreorder") == 0)
12249 {
11839 mips_emit_delays (TRUE);
11840 mips_opts.noreorder = 1;
11841 mips_any_noreorder = 1;
12250 if (!mips_opts.noreorder)
12251 start_noreorder ();
11842 }
11843 else if (strcmp (name, "at") == 0)
11844 {
11845 mips_opts.noat = 0;
11846 }
11847 else if (strcmp (name, "noat") == 0)
11848 {
11849 mips_opts.noat = 1;

--- 33 unchanged lines hidden (view full) ---

11883 else if (strcmp (name, "mips3d") == 0)
11884 mips_opts.ase_mips3d = 1;
11885 else if (strcmp (name, "nomips3d") == 0)
11886 mips_opts.ase_mips3d = 0;
11887 else if (strcmp (name, "mdmx") == 0)
11888 mips_opts.ase_mdmx = 1;
11889 else if (strcmp (name, "nomdmx") == 0)
11890 mips_opts.ase_mdmx = 0;
12252 }
12253 else if (strcmp (name, "at") == 0)
12254 {
12255 mips_opts.noat = 0;
12256 }
12257 else if (strcmp (name, "noat") == 0)
12258 {
12259 mips_opts.noat = 1;

--- 33 unchanged lines hidden (view full) ---

12293 else if (strcmp (name, "mips3d") == 0)
12294 mips_opts.ase_mips3d = 1;
12295 else if (strcmp (name, "nomips3d") == 0)
12296 mips_opts.ase_mips3d = 0;
12297 else if (strcmp (name, "mdmx") == 0)
12298 mips_opts.ase_mdmx = 1;
12299 else if (strcmp (name, "nomdmx") == 0)
12300 mips_opts.ase_mdmx = 0;
12301 else if (strcmp (name, "dsp") == 0)
12302 mips_opts.ase_dsp = 1;
12303 else if (strcmp (name, "nodsp") == 0)
12304 mips_opts.ase_dsp = 0;
12305 else if (strcmp (name, "mt") == 0)
12306 mips_opts.ase_mt = 1;
12307 else if (strcmp (name, "nomt") == 0)
12308 mips_opts.ase_mt = 0;
11891 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
11892 {
11893 int reset = 0;
11894
11895 /* Permit the user to change the ISA and architecture on the fly.
11896 Needless to say, misuse can cause serious problems. */
12309 else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0)
12310 {
12311 int reset = 0;
12312
12313 /* Permit the user to change the ISA and architecture on the fly.
12314 Needless to say, misuse can cause serious problems. */
11897 if (strcmp (name, "mips0") == 0)
12315 if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0)
11898 {
11899 reset = 1;
11900 mips_opts.isa = file_mips_isa;
12316 {
12317 reset = 1;
12318 mips_opts.isa = file_mips_isa;
11901 }
11902 else if (strcmp (name, "mips1") == 0)
11903 mips_opts.isa = ISA_MIPS1;
11904 else if (strcmp (name, "mips2") == 0)
11905 mips_opts.isa = ISA_MIPS2;
11906 else if (strcmp (name, "mips3") == 0)
11907 mips_opts.isa = ISA_MIPS3;
11908 else if (strcmp (name, "mips4") == 0)
11909 mips_opts.isa = ISA_MIPS4;
11910 else if (strcmp (name, "mips5") == 0)
11911 mips_opts.isa = ISA_MIPS5;
11912 else if (strcmp (name, "mips32") == 0)
11913 mips_opts.isa = ISA_MIPS32;
11914 else if (strcmp (name, "mips32r2") == 0)
11915 mips_opts.isa = ISA_MIPS32R2;
11916 else if (strcmp (name, "mips64") == 0)
11917 mips_opts.isa = ISA_MIPS64;
11918 else if (strcmp (name, "mips64r2") == 0)
11919 mips_opts.isa = ISA_MIPS64R2;
11920 else if (strcmp (name, "arch=default") == 0)
11921 {
11922 reset = 1;
11923 mips_opts.arch = file_mips_arch;
12319 mips_opts.arch = file_mips_arch;
11924 mips_opts.isa = file_mips_isa;
11925 }
11926 else if (strncmp (name, "arch=", 5) == 0)
11927 {
11928 const struct mips_cpu_info *p;
11929
11930 p = mips_parse_cpu("internal use", name + 5);
11931 if (!p)
11932 as_bad (_("unknown architecture %s"), name + 5);
11933 else
11934 {
11935 mips_opts.arch = p->cpu;
11936 mips_opts.isa = p->isa;
11937 }
11938 }
12320 }
12321 else if (strncmp (name, "arch=", 5) == 0)
12322 {
12323 const struct mips_cpu_info *p;
12324
12325 p = mips_parse_cpu("internal use", name + 5);
12326 if (!p)
12327 as_bad (_("unknown architecture %s"), name + 5);
12328 else
12329 {
12330 mips_opts.arch = p->cpu;
12331 mips_opts.isa = p->isa;
12332 }
12333 }
12334 else if (strncmp (name, "mips", 4) == 0)
12335 {
12336 const struct mips_cpu_info *p;
12337
12338 p = mips_parse_cpu("internal use", name);
12339 if (!p)
12340 as_bad (_("unknown ISA level %s"), name + 4);
12341 else
12342 {
12343 mips_opts.arch = p->cpu;
12344 mips_opts.isa = p->isa;
12345 }
12346 }
11939 else
12347 else
11940 as_bad (_("unknown ISA level %s"), name + 4);
12348 as_bad (_("unknown ISA or architecture %s"), name);
11941
11942 switch (mips_opts.isa)
11943 {
11944 case 0:
11945 break;
11946 case ISA_MIPS1:
11947 case ISA_MIPS2:
11948 case ISA_MIPS32:

--- 39 unchanged lines hidden (view full) ---

11988 s = mips_opts_stack;
11989 if (s == NULL)
11990 as_bad (_(".set pop with no .set push"));
11991 else
11992 {
11993 /* If we're changing the reorder mode we need to handle
11994 delay slots correctly. */
11995 if (s->options.noreorder && ! mips_opts.noreorder)
12349
12350 switch (mips_opts.isa)
12351 {
12352 case 0:
12353 break;
12354 case ISA_MIPS1:
12355 case ISA_MIPS2:
12356 case ISA_MIPS32:

--- 39 unchanged lines hidden (view full) ---

12396 s = mips_opts_stack;
12397 if (s == NULL)
12398 as_bad (_(".set pop with no .set push"));
12399 else
12400 {
12401 /* If we're changing the reorder mode we need to handle
12402 delay slots correctly. */
12403 if (s->options.noreorder && ! mips_opts.noreorder)
11996 mips_emit_delays (TRUE);
12404 start_noreorder ();
11997 else if (! s->options.noreorder && mips_opts.noreorder)
12405 else if (! s->options.noreorder && mips_opts.noreorder)
11998 {
11999 if (prev_nop_frag != NULL)
12000 {
12001 prev_nop_frag->fr_fix -= (prev_nop_frag_holds
12002 * (mips_opts.mips16 ? 2 : 4));
12003 prev_nop_frag = NULL;
12004 }
12005 }
12406 end_noreorder ();
12006
12007 mips_opts = s->options;
12008 mips_opts_stack = s->next;
12009 free (s);
12010 }
12011 }
12407
12408 mips_opts = s->options;
12409 mips_opts_stack = s->next;
12410 free (s);
12411 }
12412 }
12413 else if (strcmp (name, "sym32") == 0)
12414 mips_opts.sym32 = TRUE;
12415 else if (strcmp (name, "nosym32") == 0)
12416 mips_opts.sym32 = FALSE;
12012 else
12013 {
12014 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12015 }
12016 *input_line_pointer = ch;
12017 demand_empty_rest_of_line ();
12018}
12019
12020/* Handle the .abicalls pseudo-op. I believe this is equivalent to
12021 .option pic2. It means to generate SVR4 PIC calls. */
12022
12023static void
12024s_abicalls (int ignore ATTRIBUTE_UNUSED)
12025{
12026 mips_pic = SVR4_PIC;
12027 mips_abicalls = TRUE;
12417 else
12418 {
12419 as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
12420 }
12421 *input_line_pointer = ch;
12422 demand_empty_rest_of_line ();
12423}
12424
12425/* Handle the .abicalls pseudo-op. I believe this is equivalent to
12426 .option pic2. It means to generate SVR4 PIC calls. */
12427
12428static void
12429s_abicalls (int ignore ATTRIBUTE_UNUSED)
12430{
12431 mips_pic = SVR4_PIC;
12432 mips_abicalls = TRUE;
12028 if (USE_GLOBAL_POINTER_OPT)
12029 {
12030 if (g_switch_seen && g_switch_value != 0)
12031 as_warn (_("-G may not be used with SVR4 PIC code"));
12032 g_switch_value = 0;
12033 }
12433
12434 if (g_switch_seen && g_switch_value != 0)
12435 as_warn (_("-G may not be used with SVR4 PIC code"));
12436 g_switch_value = 0;
12437
12034 bfd_set_gp_size (stdoutput, 0);
12035 demand_empty_rest_of_line ();
12036}
12037
12038/* Handle the .cpload pseudo-op. This is used when generating SVR4
12039 PIC code. It sets the $gp register for the function based on the
12040 function address, which is in the register named in the argument.
12041 This uses a relocation against _gp_disp, which is handled specially
12042 by the linker. The result is:
12043 lui $gp,%hi(_gp_disp)
12044 addiu $gp,$gp,%lo(_gp_disp)
12045 addu $gp,$gp,.cpload argument
12438 bfd_set_gp_size (stdoutput, 0);
12439 demand_empty_rest_of_line ();
12440}
12441
12442/* Handle the .cpload pseudo-op. This is used when generating SVR4
12443 PIC code. It sets the $gp register for the function based on the
12444 function address, which is in the register named in the argument.
12445 This uses a relocation against _gp_disp, which is handled specially
12446 by the linker. The result is:
12447 lui $gp,%hi(_gp_disp)
12448 addiu $gp,$gp,%lo(_gp_disp)
12449 addu $gp,$gp,.cpload argument
12046 The .cpload argument is normally $25 == $t9. */
12450 The .cpload argument is normally $25 == $t9.
12047
12451
12452 The -mno-shared option changes this to:
12453 lui $gp,%hi(__gnu_local_gp)
12454 addiu $gp,$gp,%lo(__gnu_local_gp)
12455 and the argument is ignored. This saves an instruction, but the
12456 resulting code is not position independent; it uses an absolute
12457 address for __gnu_local_gp. Thus code assembled with -mno-shared
12458 can go into an ordinary executable, but not into a shared library. */
12459
12048static void
12049s_cpload (int ignore ATTRIBUTE_UNUSED)
12050{
12051 expressionS ex;
12460static void
12461s_cpload (int ignore ATTRIBUTE_UNUSED)
12462{
12463 expressionS ex;
12464 int reg;
12465 int in_shared;
12052
12053 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12054 .cpload is ignored. */
12055 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12056 {
12057 s_ignore (0);
12058 return;
12059 }
12060
12061 /* .cpload should be in a .set noreorder section. */
12062 if (mips_opts.noreorder == 0)
12063 as_warn (_(".cpload not in noreorder section"));
12064
12466
12467 /* If we are not generating SVR4 PIC code, or if this is NewABI code,
12468 .cpload is ignored. */
12469 if (mips_pic != SVR4_PIC || HAVE_NEWABI)
12470 {
12471 s_ignore (0);
12472 return;
12473 }
12474
12475 /* .cpload should be in a .set noreorder section. */
12476 if (mips_opts.noreorder == 0)
12477 as_warn (_(".cpload not in noreorder section"));
12478
12479 reg = tc_get_register (0);
12480
12481 /* If we need to produce a 64-bit address, we are better off using
12482 the default instruction sequence. */
12483 in_shared = mips_in_shared || HAVE_64BIT_SYMBOLS;
12484
12065 ex.X_op = O_symbol;
12485 ex.X_op = O_symbol;
12066 ex.X_add_symbol = symbol_find_or_make ("_gp_disp");
12486 ex.X_add_symbol = symbol_find_or_make (in_shared ? "_gp_disp" :
12487 "__gnu_local_gp");
12067 ex.X_op_symbol = NULL;
12068 ex.X_add_number = 0;
12069
12070 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12071 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12072
12073 macro_start ();
12074 macro_build_lui (&ex, mips_gp_register);
12075 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12076 mips_gp_register, BFD_RELOC_LO16);
12488 ex.X_op_symbol = NULL;
12489 ex.X_add_number = 0;
12490
12491 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12492 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12493
12494 macro_start ();
12495 macro_build_lui (&ex, mips_gp_register);
12496 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12497 mips_gp_register, BFD_RELOC_LO16);
12077 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12078 mips_gp_register, tc_get_register (0));
12498 if (in_shared)
12499 macro_build (NULL, "addu", "d,v,t", mips_gp_register,
12500 mips_gp_register, reg);
12079 macro_end ();
12080
12081 demand_empty_rest_of_line ();
12082}
12083
12084/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12085 .cpsetup $reg1, offset|$reg2, label
12086
12087 If offset is given, this results in:
12088 sd $gp, offset($sp)
12089 lui $gp, %hi(%neg(%gp_rel(label)))
12090 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12091 daddu $gp, $gp, $reg1
12092
12093 If $reg2 is given, this results in:
12094 daddu $reg2, $gp, $0
12095 lui $gp, %hi(%neg(%gp_rel(label)))
12096 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12097 daddu $gp, $gp, $reg1
12501 macro_end ();
12502
12503 demand_empty_rest_of_line ();
12504}
12505
12506/* Handle the .cpsetup pseudo-op defined for NewABI PIC code. The syntax is:
12507 .cpsetup $reg1, offset|$reg2, label
12508
12509 If offset is given, this results in:
12510 sd $gp, offset($sp)
12511 lui $gp, %hi(%neg(%gp_rel(label)))
12512 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12513 daddu $gp, $gp, $reg1
12514
12515 If $reg2 is given, this results in:
12516 daddu $reg2, $gp, $0
12517 lui $gp, %hi(%neg(%gp_rel(label)))
12518 addiu $gp, $gp, %lo(%neg(%gp_rel(label)))
12519 daddu $gp, $gp, $reg1
12098 $reg1 is normally $25 == $t9. */
12520 $reg1 is normally $25 == $t9.
12521
12522 The -mno-shared option replaces the last three instructions with
12523 lui $gp,%hi(_gp)
12524 addiu $gp,$gp,%lo(_gp)
12525 */
12526
12099static void
12100s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12101{
12102 expressionS ex_off;
12103 expressionS ex_sym;
12104 int reg1;
12527static void
12528s_cpsetup (int ignore ATTRIBUTE_UNUSED)
12529{
12530 expressionS ex_off;
12531 expressionS ex_sym;
12532 int reg1;
12105 char *f;
12106
12107 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12108 We also need NewABI support. */
12109 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12110 {
12111 s_ignore (0);
12112 return;
12113 }

--- 39 unchanged lines hidden (view full) ---

12153
12154 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12155 BFD_RELOC_LO16, SP);
12156 }
12157 else
12158 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12159 mips_gp_register, 0);
12160
12533
12534 /* If we are not generating SVR4 PIC code, .cpsetup is ignored.
12535 We also need NewABI support. */
12536 if (mips_pic != SVR4_PIC || ! HAVE_NEWABI)
12537 {
12538 s_ignore (0);
12539 return;
12540 }

--- 39 unchanged lines hidden (view full) ---

12580
12581 macro_build (&ex_off, "sd", "t,o(b)", mips_gp_register,
12582 BFD_RELOC_LO16, SP);
12583 }
12584 else
12585 macro_build (NULL, "daddu", "d,v,t", mips_cpreturn_register,
12586 mips_gp_register, 0);
12587
12161 /* Ensure there's room for the next two instructions, so that `f'
12162 doesn't end up with an address in the wrong frag. */
12163 frag_grow (8);
12164 f = frag_more (0);
12165 macro_build (&ex_sym, "lui", "t,u", mips_gp_register, BFD_RELOC_GPREL16);
12166 fix_new (frag_now, f - frag_now->fr_literal,
12167 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12168 fix_new (frag_now, f - frag_now->fr_literal,
12169 4, NULL, 0, 0, BFD_RELOC_HI16_S);
12588 if (mips_in_shared || HAVE_64BIT_SYMBOLS)
12589 {
12590 macro_build (&ex_sym, "lui", "t,u", mips_gp_register,
12591 -1, BFD_RELOC_GPREL16, BFD_RELOC_MIPS_SUB,
12592 BFD_RELOC_HI16_S);
12170
12593
12171 f = frag_more (0);
12172 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12173 mips_gp_register, BFD_RELOC_GPREL16);
12174 fix_new (frag_now, f - frag_now->fr_literal,
12175 8, NULL, 0, 0, BFD_RELOC_MIPS_SUB);
12176 fix_new (frag_now, f - frag_now->fr_literal,
12177 4, NULL, 0, 0, BFD_RELOC_LO16);
12594 macro_build (&ex_sym, "addiu", "t,r,j", mips_gp_register,
12595 mips_gp_register, -1, BFD_RELOC_GPREL16,
12596 BFD_RELOC_MIPS_SUB, BFD_RELOC_LO16);
12178
12597
12179 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12180 mips_gp_register, reg1);
12598 macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", mips_gp_register,
12599 mips_gp_register, reg1);
12600 }
12601 else
12602 {
12603 expressionS ex;
12604
12605 ex.X_op = O_symbol;
12606 ex.X_add_symbol = symbol_find_or_make ("__gnu_local_gp");
12607 ex.X_op_symbol = NULL;
12608 ex.X_add_number = 0;
12609
12610 /* In ELF, this symbol is implicitly an STT_OBJECT symbol. */
12611 symbol_get_bfdsym (ex.X_add_symbol)->flags |= BSF_OBJECT;
12612
12613 macro_build_lui (&ex, mips_gp_register);
12614 macro_build (&ex, "addiu", "t,r,j", mips_gp_register,
12615 mips_gp_register, BFD_RELOC_LO16);
12616 }
12617
12181 macro_end ();
12182
12183 demand_empty_rest_of_line ();
12184}
12185
12186static void
12187s_cplocal (int ignore ATTRIBUTE_UNUSED)
12188{

--- 112 unchanged lines hidden (view full) ---

12301 /* When not generating PIC code, this is treated as .word. */
12302 if (mips_pic != SVR4_PIC)
12303 {
12304 s_cons (2);
12305 return;
12306 }
12307
12308 label = insn_labels != NULL ? insn_labels->label : NULL;
12618 macro_end ();
12619
12620 demand_empty_rest_of_line ();
12621}
12622
12623static void
12624s_cplocal (int ignore ATTRIBUTE_UNUSED)
12625{

--- 112 unchanged lines hidden (view full) ---

12738 /* When not generating PIC code, this is treated as .word. */
12739 if (mips_pic != SVR4_PIC)
12740 {
12741 s_cons (2);
12742 return;
12743 }
12744
12745 label = insn_labels != NULL ? insn_labels->label : NULL;
12309 mips_emit_delays (TRUE);
12746 mips_emit_delays ();
12310 if (auto_align)
12311 mips_align (2, 0, label);
12312 mips_clear_insn_labels ();
12313
12314 expression (&ex);
12315
12316 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12317 {

--- 19 unchanged lines hidden (view full) ---

12337 /* When not generating PIC code, this is treated as .dword. */
12338 if (mips_pic != SVR4_PIC)
12339 {
12340 s_cons (3);
12341 return;
12342 }
12343
12344 label = insn_labels != NULL ? insn_labels->label : NULL;
12747 if (auto_align)
12748 mips_align (2, 0, label);
12749 mips_clear_insn_labels ();
12750
12751 expression (&ex);
12752
12753 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12754 {

--- 19 unchanged lines hidden (view full) ---

12774 /* When not generating PIC code, this is treated as .dword. */
12775 if (mips_pic != SVR4_PIC)
12776 {
12777 s_cons (3);
12778 return;
12779 }
12780
12781 label = insn_labels != NULL ? insn_labels->label : NULL;
12345 mips_emit_delays (TRUE);
12782 mips_emit_delays ();
12346 if (auto_align)
12347 mips_align (3, 0, label);
12348 mips_clear_insn_labels ();
12349
12350 expression (&ex);
12351
12352 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12353 {
12354 as_bad (_("Unsupported use of .gpdword"));
12355 ignore_rest_of_line ();
12356 }
12357
12358 p = frag_more (8);
12359 md_number_to_chars (p, 0, 8);
12360 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12783 if (auto_align)
12784 mips_align (3, 0, label);
12785 mips_clear_insn_labels ();
12786
12787 expression (&ex);
12788
12789 if (ex.X_op != O_symbol || ex.X_add_number != 0)
12790 {
12791 as_bad (_("Unsupported use of .gpdword"));
12792 ignore_rest_of_line ();
12793 }
12794
12795 p = frag_more (8);
12796 md_number_to_chars (p, 0, 8);
12797 fix_new_exp (frag_now, p - frag_now->fr_literal, 4, &ex, FALSE,
12361 BFD_RELOC_GPREL32);
12798 BFD_RELOC_GPREL32)->fx_tcbit = 1;
12362
12363 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12799
12800 /* GPREL32 composed with 64 gives a 64-bit GP offset. */
12364 ex.X_op = O_absent;
12365 ex.X_add_symbol = 0;
12366 ex.X_add_number = 0;
12367 fix_new_exp (frag_now, p - frag_now->fr_literal, 8, &ex, FALSE,
12368 BFD_RELOC_64);
12801 fix_new (frag_now, p - frag_now->fr_literal, 8, NULL, 0,
12802 FALSE, BFD_RELOC_64)->fx_tcbit = 1;
12369
12370 demand_empty_rest_of_line ();
12371}
12372
12373/* Handle the .cpadd pseudo-op. This is used when dealing with switch
12374 tables in SVR4 PIC code. */
12375
12376static void

--- 205 unchanged lines hidden (view full) ---

12582 undefined earlier.) */
12583
12584static int
12585nopic_need_relax (symbolS *sym, int before_relaxing)
12586{
12587 if (sym == 0)
12588 return 0;
12589
12803
12804 demand_empty_rest_of_line ();
12805}
12806
12807/* Handle the .cpadd pseudo-op. This is used when dealing with switch
12808 tables in SVR4 PIC code. */
12809
12810static void

--- 205 unchanged lines hidden (view full) ---

13016 undefined earlier.) */
13017
13018static int
13019nopic_need_relax (symbolS *sym, int before_relaxing)
13020{
13021 if (sym == 0)
13022 return 0;
13023
12590 if (USE_GLOBAL_POINTER_OPT && g_switch_value > 0)
13024 if (g_switch_value > 0)
12591 {
12592 const char *symname;
12593 int change;
12594
12595 /* Find out whether this symbol can be referenced off the $gp
12596 register. It can be if it is smaller than the -G size or if
12597 it is in the .sdata or .sbss section. Certain symbols can
12598 not be referenced off the $gp, although it appears as though

--- 90 unchanged lines hidden (view full) ---

12689 /* This must duplicate the test in adjust_reloc_syms. */
12690 return (symsec != &bfd_und_section
12691 && symsec != &bfd_abs_section
12692 && ! bfd_is_com_section (symsec)
12693 && !linkonce
12694#ifdef OBJ_ELF
12695 /* A global or weak symbol is treated as external. */
12696 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
13025 {
13026 const char *symname;
13027 int change;
13028
13029 /* Find out whether this symbol can be referenced off the $gp
13030 register. It can be if it is smaller than the -G size or if
13031 it is in the .sdata or .sbss section. Certain symbols can
13032 not be referenced off the $gp, although it appears as though

--- 90 unchanged lines hidden (view full) ---

13123 /* This must duplicate the test in adjust_reloc_syms. */
13124 return (symsec != &bfd_und_section
13125 && symsec != &bfd_abs_section
13126 && ! bfd_is_com_section (symsec)
13127 && !linkonce
13128#ifdef OBJ_ELF
13129 /* A global or weak symbol is treated as external. */
13130 && (OUTPUT_FLAVOR != bfd_target_elf_flavour
12697 || (! S_IS_WEAK (sym)
12698 && (! S_IS_EXTERNAL (sym)
12699 || mips_pic == EMBEDDED_PIC)))
13131 || (! S_IS_WEAK (sym) && ! S_IS_EXTERNAL (sym)))
12700#endif
12701 );
12702}
12703
12704
12705/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
12706 extended opcode. SEC is the section the frag is in. */
12707

--- 291 unchanged lines hidden (view full) ---

12999 fragp->fr_subtype |= RELAX_USE_SECOND;
13000 return -RELAX_FIRST (fragp->fr_subtype);
13001 }
13002 else
13003 return -RELAX_SECOND (fragp->fr_subtype);
13004}
13005
13006/* This is called to see whether a reloc against a defined symbol
13132#endif
13133 );
13134}
13135
13136
13137/* Given a mips16 variant frag FRAGP, return non-zero if it needs an
13138 extended opcode. SEC is the section the frag is in. */
13139

--- 291 unchanged lines hidden (view full) ---

13431 fragp->fr_subtype |= RELAX_USE_SECOND;
13432 return -RELAX_FIRST (fragp->fr_subtype);
13433 }
13434 else
13435 return -RELAX_SECOND (fragp->fr_subtype);
13436}
13437
13438/* This is called to see whether a reloc against a defined symbol
13007 should be converted into a reloc against a section. Don't adjust
13008 MIPS16 jump relocations, so we don't have to worry about the format
13009 of the offset in the .o file. Don't adjust relocations against
13010 mips16 symbols, so that the linker can find them if it needs to set
13011 up a stub. */
13439 should be converted into a reloc against a section. */
13012
13013int
13014mips_fix_adjustable (fixS *fixp)
13015{
13440
13441int
13442mips_fix_adjustable (fixS *fixp)
13443{
13444 /* Don't adjust MIPS16 jump relocations, so we don't have to worry
13445 about the format of the offset in the .o file. */
13016 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13017 return 0;
13018
13019 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13020 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13021 return 0;
13022
13023 if (fixp->fx_addsy == NULL)

--- 15 unchanged lines hidden (view full) ---

13039 original symbol. This will work with either linker behavior. */
13040 if ((fixp->fx_r_type == BFD_RELOC_LO16
13041 || reloc_needs_lo_p (fixp->fx_r_type))
13042 && HAVE_IN_PLACE_ADDENDS
13043 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13044 return 0;
13045
13046#ifdef OBJ_ELF
13446 if (fixp->fx_r_type == BFD_RELOC_MIPS16_JMP)
13447 return 0;
13448
13449 if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
13450 || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13451 return 0;
13452
13453 if (fixp->fx_addsy == NULL)

--- 15 unchanged lines hidden (view full) ---

13469 original symbol. This will work with either linker behavior. */
13470 if ((fixp->fx_r_type == BFD_RELOC_LO16
13471 || reloc_needs_lo_p (fixp->fx_r_type))
13472 && HAVE_IN_PLACE_ADDENDS
13473 && (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE) != 0)
13474 return 0;
13475
13476#ifdef OBJ_ELF
13477 /* Don't adjust relocations against mips16 symbols, so that the linker
13478 can find them if it needs to set up a stub. */
13047 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13048 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13049 && fixp->fx_subsy == NULL)
13050 return 0;
13051#endif
13052
13053 return 1;
13054}

--- 9 unchanged lines hidden (view full) ---

13064 bfd_reloc_code_real_type code;
13065
13066 memset (retval, 0, sizeof(retval));
13067 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13068 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13069 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13070 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13071
13479 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
13480 && S_GET_OTHER (fixp->fx_addsy) == STO_MIPS16
13481 && fixp->fx_subsy == NULL)
13482 return 0;
13483#endif
13484
13485 return 1;
13486}

--- 9 unchanged lines hidden (view full) ---

13496 bfd_reloc_code_real_type code;
13497
13498 memset (retval, 0, sizeof(retval));
13499 reloc = retval[0] = (arelent *) xcalloc (1, sizeof (arelent));
13500 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
13501 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
13502 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
13503
13072 if (mips_pic == EMBEDDED_PIC
13073 && SWITCH_TABLE (fixp))
13504 if (fixp->fx_pcrel)
13074 {
13505 {
13075 /* For a switch table entry we use a special reloc. The addend
13076 is actually the difference between the reloc address and the
13077 subtrahend. */
13078 reloc->addend = reloc->address - S_GET_VALUE (fixp->fx_subsy);
13079 if (OUTPUT_FLAVOR != bfd_target_ecoff_flavour)
13080 as_fatal (_("Double check fx_r_type in tc-mips.c:tc_gen_reloc"));
13081 fixp->fx_r_type = BFD_RELOC_GPREL32;
13082 }
13083 else if (fixp->fx_pcrel)
13084 {
13085 bfd_vma pcrel_address;
13506 assert (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2);
13086
13507
13087 /* Set PCREL_ADDRESS to this relocation's "PC". The PC for high
13088 high-part relocs is the address of the low-part reloc. */
13089 if (fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13508 /* At this point, fx_addnumber is "symbol offset - pcrel address".
13509 Relocations want only the symbol offset. */
13510 reloc->addend = fixp->fx_addnumber + reloc->address;
13511 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
13090 {
13512 {
13091 assert (fixp->fx_next != NULL
13092 && fixp->fx_next->fx_r_type == BFD_RELOC_PCREL_LO16);
13093 pcrel_address = (fixp->fx_next->fx_where
13094 + fixp->fx_next->fx_frag->fr_address);
13513 /* A gruesome hack which is a result of the gruesome gas
13514 reloc handling. What's worse, for COFF (as opposed to
13515 ECOFF), we might need yet another copy of reloc->address.
13516 See bfd_install_relocation. */
13517 reloc->addend += reloc->address;
13095 }
13518 }
13096 else
13097 pcrel_address = reloc->address;
13098
13099 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
13100 {
13101 /* At this point, fx_addnumber is "symbol offset - pcrel_address".
13102 Relocations want only the symbol offset. */
13103 reloc->addend = fixp->fx_addnumber + pcrel_address;
13104 }
13105 else if (fixp->fx_r_type == BFD_RELOC_PCREL_LO16
13106 || fixp->fx_r_type == BFD_RELOC_PCREL_HI16_S)
13107 {
13108 /* We use a special addend for an internal RELLO or RELHI reloc. */
13109 if (symbol_section_p (fixp->fx_addsy))
13110 reloc->addend = pcrel_address - S_GET_VALUE (fixp->fx_subsy);
13111 else
13112 reloc->addend = fixp->fx_addnumber + pcrel_address;
13113 }
13114 else
13115 {
13116 if (OUTPUT_FLAVOR != bfd_target_aout_flavour)
13117 /* A gruesome hack which is a result of the gruesome gas reloc
13118 handling. */
13119 reloc->addend = pcrel_address;
13120 else
13121 reloc->addend = -pcrel_address;
13122 }
13123 }
13124 else
13125 reloc->addend = fixp->fx_addnumber;
13126
13127 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13128 entry to be used in the relocation's section offset. */
13129 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13130 {
13131 reloc->address = reloc->addend;
13132 reloc->addend = 0;
13133 }
13134
13519 }
13520 else
13521 reloc->addend = fixp->fx_addnumber;
13522
13523 /* Since the old MIPS ELF ABI uses Rel instead of Rela, encode the vtable
13524 entry to be used in the relocation's section offset. */
13525 if (! HAVE_NEWABI && fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
13526 {
13527 reloc->address = reloc->addend;
13528 reloc->addend = 0;
13529 }
13530
13135 /* Since DIFF_EXPR_OK is defined in tc-mips.h, it is possible that
13136 fixup_segment converted a non-PC relative reloc into a PC
13137 relative reloc. In such a case, we need to convert the reloc
13138 code. */
13139 code = fixp->fx_r_type;
13531 code = fixp->fx_r_type;
13140 if (fixp->fx_pcrel)
13141 {
13142 switch (code)
13143 {
13144 case BFD_RELOC_8:
13145 code = BFD_RELOC_8_PCREL;
13146 break;
13147 case BFD_RELOC_16:
13148 code = BFD_RELOC_16_PCREL;
13149 break;
13150 case BFD_RELOC_32:
13151 code = BFD_RELOC_32_PCREL;
13152 break;
13153 case BFD_RELOC_64:
13154 code = BFD_RELOC_64_PCREL;
13155 break;
13156 case BFD_RELOC_8_PCREL:
13157 case BFD_RELOC_16_PCREL:
13158 case BFD_RELOC_32_PCREL:
13159 case BFD_RELOC_64_PCREL:
13160 case BFD_RELOC_16_PCREL_S2:
13161 case BFD_RELOC_PCREL_HI16_S:
13162 case BFD_RELOC_PCREL_LO16:
13163 break;
13164 default:
13165 as_bad_where (fixp->fx_file, fixp->fx_line,
13166 _("Cannot make %s relocation PC relative"),
13167 bfd_get_reloc_code_name (code));
13168 }
13169 }
13170
13532
13171 /* To support a PC relative reloc when generating embedded PIC code
13172 for ECOFF, we use a Cygnus extension. We check for that here to
13173 make sure that we don't let such a reloc escape normally. */
13174 if ((OUTPUT_FLAVOR == bfd_target_ecoff_flavour
13175 || OUTPUT_FLAVOR == bfd_target_elf_flavour)
13176 && code == BFD_RELOC_16_PCREL_S2
13177 && mips_pic != EMBEDDED_PIC)
13178 reloc->howto = NULL;
13179 else
13180 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13181
13533 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
13182 if (reloc->howto == NULL)
13183 {
13184 as_bad_where (fixp->fx_file, fixp->fx_line,
13185 _("Can not represent %s relocation in this object file format"),
13186 bfd_get_reloc_code_name (code));
13187 retval[0] = NULL;
13188 }
13189

--- 60 unchanged lines hidden (view full) ---

13250 /* We generate a fixup instead of applying it right now
13251 because, if there are linker relaxations, we're going to
13252 need the relocations. */
13253 exp.X_op = O_symbol;
13254 exp.X_add_symbol = fragp->fr_symbol;
13255 exp.X_add_number = fragp->fr_offset;
13256
13257 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13534 if (reloc->howto == NULL)
13535 {
13536 as_bad_where (fixp->fx_file, fixp->fx_line,
13537 _("Can not represent %s relocation in this object file format"),
13538 bfd_get_reloc_code_name (code));
13539 retval[0] = NULL;
13540 }
13541

--- 60 unchanged lines hidden (view full) ---

13602 /* We generate a fixup instead of applying it right now
13603 because, if there are linker relaxations, we're going to
13604 need the relocations. */
13605 exp.X_op = O_symbol;
13606 exp.X_add_symbol = fragp->fr_symbol;
13607 exp.X_add_number = fragp->fr_offset;
13608
13609 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13258 4, &exp, 1,
13259 BFD_RELOC_16_PCREL_S2);
13610 4, &exp, 1, BFD_RELOC_16_PCREL_S2);
13260 fixp->fx_file = fragp->fr_file;
13261 fixp->fx_line = fragp->fr_line;
13262
13611 fixp->fx_file = fragp->fr_file;
13612 fixp->fx_line = fragp->fr_line;
13613
13263 md_number_to_chars (buf, insn, 4);
13614 md_number_to_chars ((char *) buf, insn, 4);
13264 buf += 4;
13265 }
13266 else
13267 {
13268 int i;
13269
13270 as_warn_where (fragp->fr_file, fragp->fr_line,
13271 _("relaxed out-of-range branch into a jump"));

--- 55 unchanged lines hidden (view full) ---

13327 i = fragp->fr_var - i;
13328 }
13329 /* Convert to instruction count. */
13330 i >>= 2;
13331 /* Branch counts from the next instruction. */
13332 i--;
13333 insn |= i;
13334 /* Branch over the jump. */
13615 buf += 4;
13616 }
13617 else
13618 {
13619 int i;
13620
13621 as_warn_where (fragp->fr_file, fragp->fr_line,
13622 _("relaxed out-of-range branch into a jump"));

--- 55 unchanged lines hidden (view full) ---

13678 i = fragp->fr_var - i;
13679 }
13680 /* Convert to instruction count. */
13681 i >>= 2;
13682 /* Branch counts from the next instruction. */
13683 i--;
13684 insn |= i;
13685 /* Branch over the jump. */
13335 md_number_to_chars (buf, insn, 4);
13686 md_number_to_chars ((char *) buf, insn, 4);
13336 buf += 4;
13337
13338 /* Nop */
13687 buf += 4;
13688
13689 /* Nop */
13339 md_number_to_chars (buf, 0, 4);
13690 md_number_to_chars ((char *) buf, 0, 4);
13340 buf += 4;
13341
13342 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13343 {
13344 /* beql $0, $0, 2f */
13345 insn = 0x50000000;
13346 /* Compute the PC offset from the current instruction to
13347 the end of the variable frag. */
13348 /* How many bytes in instructions we've already emitted? */
13349 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13350 /* How many bytes in instructions from here to the end? */
13351 i = fragp->fr_var - i;
13352 /* Convert to instruction count. */
13353 i >>= 2;
13354 /* Don't decrement i, because we want to branch over the
13355 delay slot. */
13356
13357 insn |= i;
13691 buf += 4;
13692
13693 if (RELAX_BRANCH_LIKELY (fragp->fr_subtype))
13694 {
13695 /* beql $0, $0, 2f */
13696 insn = 0x50000000;
13697 /* Compute the PC offset from the current instruction to
13698 the end of the variable frag. */
13699 /* How many bytes in instructions we've already emitted? */
13700 i = buf - (bfd_byte *)fragp->fr_literal - fragp->fr_fix;
13701 /* How many bytes in instructions from here to the end? */
13702 i = fragp->fr_var - i;
13703 /* Convert to instruction count. */
13704 i >>= 2;
13705 /* Don't decrement i, because we want to branch over the
13706 delay slot. */
13707
13708 insn |= i;
13358 md_number_to_chars (buf, insn, 4);
13709 md_number_to_chars ((char *) buf, insn, 4);
13359 buf += 4;
13360
13710 buf += 4;
13711
13361 md_number_to_chars (buf, 0, 4);
13712 md_number_to_chars ((char *) buf, 0, 4);
13362 buf += 4;
13363 }
13364
13365 uncond:
13366 if (mips_pic == NO_PIC)
13367 {
13368 /* j or jal. */
13369 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13370 ? 0x0c000000 : 0x08000000);
13371 exp.X_op = O_symbol;
13372 exp.X_add_symbol = fragp->fr_symbol;
13373 exp.X_add_number = fragp->fr_offset;
13374
13375 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13376 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13377 fixp->fx_file = fragp->fr_file;
13378 fixp->fx_line = fragp->fr_line;
13379
13713 buf += 4;
13714 }
13715
13716 uncond:
13717 if (mips_pic == NO_PIC)
13718 {
13719 /* j or jal. */
13720 insn = (RELAX_BRANCH_LINK (fragp->fr_subtype)
13721 ? 0x0c000000 : 0x08000000);
13722 exp.X_op = O_symbol;
13723 exp.X_add_symbol = fragp->fr_symbol;
13724 exp.X_add_number = fragp->fr_offset;
13725
13726 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13727 4, &exp, 0, BFD_RELOC_MIPS_JMP);
13728 fixp->fx_file = fragp->fr_file;
13729 fixp->fx_line = fragp->fr_line;
13730
13380 md_number_to_chars (buf, insn, 4);
13731 md_number_to_chars ((char *) buf, insn, 4);
13381 buf += 4;
13382 }
13383 else
13384 {
13385 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13386 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13387 exp.X_op = O_symbol;
13388 exp.X_add_symbol = fragp->fr_symbol;

--- 5 unchanged lines hidden (view full) ---

13394 exp.X_add_number = 0;
13395 }
13396
13397 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13398 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13399 fixp->fx_file = fragp->fr_file;
13400 fixp->fx_line = fragp->fr_line;
13401
13732 buf += 4;
13733 }
13734 else
13735 {
13736 /* lw/ld $at, <sym>($gp) R_MIPS_GOT16 */
13737 insn = HAVE_64BIT_ADDRESSES ? 0xdf810000 : 0x8f810000;
13738 exp.X_op = O_symbol;
13739 exp.X_add_symbol = fragp->fr_symbol;

--- 5 unchanged lines hidden (view full) ---

13745 exp.X_add_number = 0;
13746 }
13747
13748 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13749 4, &exp, 0, BFD_RELOC_MIPS_GOT16);
13750 fixp->fx_file = fragp->fr_file;
13751 fixp->fx_line = fragp->fr_line;
13752
13402 md_number_to_chars (buf, insn, 4);
13753 md_number_to_chars ((char *) buf, insn, 4);
13403 buf += 4;
13404
13405 if (mips_opts.isa == ISA_MIPS1)
13406 {
13407 /* nop */
13754 buf += 4;
13755
13756 if (mips_opts.isa == ISA_MIPS1)
13757 {
13758 /* nop */
13408 md_number_to_chars (buf, 0, 4);
13759 md_number_to_chars ((char *) buf, 0, 4);
13409 buf += 4;
13410 }
13411
13412 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13413 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13414
13415 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13416 4, &exp, 0, BFD_RELOC_LO16);
13417 fixp->fx_file = fragp->fr_file;
13418 fixp->fx_line = fragp->fr_line;
13419
13760 buf += 4;
13761 }
13762
13763 /* d/addiu $at, $at, <sym> R_MIPS_LO16 */
13764 insn = HAVE_64BIT_ADDRESSES ? 0x64210000 : 0x24210000;
13765
13766 fixp = fix_new_exp (fragp, buf - (bfd_byte *)fragp->fr_literal,
13767 4, &exp, 0, BFD_RELOC_LO16);
13768 fixp->fx_file = fragp->fr_file;
13769 fixp->fx_line = fragp->fr_line;
13770
13420 md_number_to_chars (buf, insn, 4);
13771 md_number_to_chars ((char *) buf, insn, 4);
13421 buf += 4;
13422
13423 /* j(al)r $at. */
13424 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13425 insn = 0x0020f809;
13426 else
13427 insn = 0x00200008;
13428
13772 buf += 4;
13773
13774 /* j(al)r $at. */
13775 if (RELAX_BRANCH_LINK (fragp->fr_subtype))
13776 insn = 0x0020f809;
13777 else
13778 insn = 0x00200008;
13779
13429 md_number_to_chars (buf, insn, 4);
13780 md_number_to_chars ((char *) buf, insn, 4);
13430 buf += 4;
13431 }
13432 }
13433
13434 assert (buf == (bfd_byte *)fragp->fr_literal
13435 + fragp->fr_fix + fragp->fr_var);
13436
13437 fragp->fr_fix += fragp->fr_var;

--- 76 unchanged lines hidden (view full) ---

13514 insn = bfd_getl16 (buf);
13515
13516 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13517 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13518 small, ext, &insn, &use_extend, &extend);
13519
13520 if (use_extend)
13521 {
13781 buf += 4;
13782 }
13783 }
13784
13785 assert (buf == (bfd_byte *)fragp->fr_literal
13786 + fragp->fr_fix + fragp->fr_var);
13787
13788 fragp->fr_fix += fragp->fr_var;

--- 76 unchanged lines hidden (view full) ---

13865 insn = bfd_getl16 (buf);
13866
13867 mips16_immed (fragp->fr_file, fragp->fr_line, type, val,
13868 RELAX_MIPS16_USER_EXT (fragp->fr_subtype),
13869 small, ext, &insn, &use_extend, &extend);
13870
13871 if (use_extend)
13872 {
13522 md_number_to_chars (buf, 0xf000 | extend, 2);
13873 md_number_to_chars ((char *) buf, 0xf000 | extend, 2);
13523 fragp->fr_fix += 2;
13524 buf += 2;
13525 }
13526
13874 fragp->fr_fix += 2;
13875 buf += 2;
13876 }
13877
13527 md_number_to_chars (buf, insn, 2);
13878 md_number_to_chars ((char *) buf, insn, 2);
13528 fragp->fr_fix += 2;
13529 buf += 2;
13530 }
13531 else
13532 {
13533 int first, second;
13534 fixS *fixp;
13535

--- 151 unchanged lines hidden (view full) ---

13687 {
13688 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
13689 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13690 }
13691 if (mips_abicalls)
13692 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
13693
13694 /* Set MIPS ELF flags for ASEs. */
13879 fragp->fr_fix += 2;
13880 buf += 2;
13881 }
13882 else
13883 {
13884 int first, second;
13885 fixS *fixp;
13886

--- 151 unchanged lines hidden (view full) ---

14038 {
14039 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_PIC;
14040 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14041 }
14042 if (mips_abicalls)
14043 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_CPIC;
14044
14045 /* Set MIPS ELF flags for ASEs. */
14046 /* We may need to define a new flag for DSP ASE, and set this flag when
14047 file_ase_dsp is true. */
14048 /* We may need to define a new flag for MT ASE, and set this flag when
14049 file_ase_mt is true. */
13695 if (file_ase_mips16)
13696 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
13697#if 0 /* XXX FIXME */
13698 if (file_ase_mips3d)
13699 elf_elfheader (stdoutput)->e_flags |= ???;
13700#endif
13701 if (file_ase_mdmx)
13702 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;

--- 17 unchanged lines hidden (view full) ---

13720
13721 if (mips_32bitmode)
13722 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
13723}
13724
13725#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
13726
13727typedef struct proc {
14050 if (file_ase_mips16)
14051 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16;
14052#if 0 /* XXX FIXME */
14053 if (file_ase_mips3d)
14054 elf_elfheader (stdoutput)->e_flags |= ???;
14055#endif
14056 if (file_ase_mdmx)
14057 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX;

--- 17 unchanged lines hidden (view full) ---

14075
14076 if (mips_32bitmode)
14077 elf_elfheader (stdoutput)->e_flags |= EF_MIPS_32BITMODE;
14078}
14079
14080#endif /* OBJ_ELF || OBJ_MAYBE_ELF */
14081
14082typedef struct proc {
13728 symbolS *isym;
14083 symbolS *func_sym;
14084 symbolS *func_end_sym;
13729 unsigned long reg_mask;
13730 unsigned long reg_offset;
13731 unsigned long fpreg_mask;
13732 unsigned long fpreg_offset;
13733 unsigned long frame_offset;
13734 unsigned long frame_reg;
13735 unsigned long pc_reg;
13736} procS;

--- 167 unchanged lines hidden (view full) ---

13904 as_warn (_(".end directive without a preceding .ent directive."));
13905 demand_empty_rest_of_line ();
13906 return;
13907 }
13908
13909 if (p != NULL)
13910 {
13911 assert (S_GET_NAME (p));
14085 unsigned long reg_mask;
14086 unsigned long reg_offset;
14087 unsigned long fpreg_mask;
14088 unsigned long fpreg_offset;
14089 unsigned long frame_offset;
14090 unsigned long frame_reg;
14091 unsigned long pc_reg;
14092} procS;

--- 167 unchanged lines hidden (view full) ---

14260 as_warn (_(".end directive without a preceding .ent directive."));
14261 demand_empty_rest_of_line ();
14262 return;
14263 }
14264
14265 if (p != NULL)
14266 {
14267 assert (S_GET_NAME (p));
13912 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->isym)))
14268 if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
13913 as_warn (_(".end symbol does not match .ent symbol."));
13914
13915 if (debug_type == DEBUG_STABS)
13916 stabs_generate_asm_endfunc (S_GET_NAME (p),
13917 S_GET_NAME (p));
13918 }
13919 else
13920 as_warn (_(".end directive missing or unknown symbol"));
13921
13922#ifdef OBJ_ELF
14269 as_warn (_(".end symbol does not match .ent symbol."));
14270
14271 if (debug_type == DEBUG_STABS)
14272 stabs_generate_asm_endfunc (S_GET_NAME (p),
14273 S_GET_NAME (p));
14274 }
14275 else
14276 as_warn (_(".end directive missing or unknown symbol"));
14277
14278#ifdef OBJ_ELF
14279 /* Create an expression to calculate the size of the function. */
14280 if (p && cur_proc_ptr)
14281 {
14282 OBJ_SYMFIELD_TYPE *obj = symbol_get_obj (p);
14283 expressionS *exp = xmalloc (sizeof (expressionS));
14284
14285 obj->size = exp;
14286 exp->X_op = O_subtract;
14287 exp->X_add_symbol = symbol_temp_new_now ();
14288 exp->X_op_symbol = p;
14289 exp->X_add_number = 0;
14290
14291 cur_proc_ptr->func_end_sym = exp->X_add_symbol;
14292 }
14293
13923 /* Generate a .pdr section. */
13924 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
13925 && mips_flag_pdr)
13926 {
13927 segT saved_seg = now_seg;
13928 subsegT saved_subseg = now_subseg;
13929 valueT dot;
13930 expressionS exp;

--- 56 unchanged lines hidden (view full) ---

13987 {
13988 /* This function needs its own .frame and .cprestore directives. */
13989 mips_frame_reg_valid = 0;
13990 mips_cprestore_valid = 0;
13991
13992 cur_proc_ptr = &cur_proc;
13993 memset (cur_proc_ptr, '\0', sizeof (procS));
13994
14294 /* Generate a .pdr section. */
14295 if (OUTPUT_FLAVOR == bfd_target_elf_flavour && ! ECOFF_DEBUGGING
14296 && mips_flag_pdr)
14297 {
14298 segT saved_seg = now_seg;
14299 subsegT saved_subseg = now_subseg;
14300 valueT dot;
14301 expressionS exp;

--- 56 unchanged lines hidden (view full) ---

14358 {
14359 /* This function needs its own .frame and .cprestore directives. */
14360 mips_frame_reg_valid = 0;
14361 mips_cprestore_valid = 0;
14362
14363 cur_proc_ptr = &cur_proc;
14364 memset (cur_proc_ptr, '\0', sizeof (procS));
14365
13995 cur_proc_ptr->isym = symbolP;
14366 cur_proc_ptr->func_sym = symbolP;
13996
13997 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
13998
13999 ++numprocs;
14000
14001 if (debug_type == DEBUG_STABS)
14002 stabs_generate_asm_func (S_GET_NAME (symbolP),
14003 S_GET_NAME (symbolP));

--- 89 unchanged lines hidden (view full) ---

14093
14094 demand_empty_rest_of_line ();
14095 }
14096 else
14097#endif /* OBJ_ELF */
14098 s_ignore (reg_type);
14099}
14100
14367
14368 symbol_get_bfdsym (symbolP)->flags |= BSF_FUNCTION;
14369
14370 ++numprocs;
14371
14372 if (debug_type == DEBUG_STABS)
14373 stabs_generate_asm_func (S_GET_NAME (symbolP),
14374 S_GET_NAME (symbolP));

--- 89 unchanged lines hidden (view full) ---

14464
14465 demand_empty_rest_of_line ();
14466 }
14467 else
14468#endif /* OBJ_ELF */
14469 s_ignore (reg_type);
14470}
14471
14101/* The .loc directive. */
14102
14103#if 0
14104static void
14105s_loc (int x)
14106{
14107 symbolS *symbolP;
14108 int lineno;
14109 int addroff;
14110
14111 assert (now_seg == text_section);
14112
14113 lineno = get_number ();
14114 addroff = frag_now_fix ();
14115
14116 symbolP = symbol_new ("", N_SLINE, addroff, frag_now);
14117 S_SET_TYPE (symbolP, N_SLINE);
14118 S_SET_OTHER (symbolP, 0);
14119 S_SET_DESC (symbolP, lineno);
14120 symbolP->sy_segment = now_seg;
14121}
14122#endif
14123
14124/* A table describing all the processors gas knows about. Names are
14125 matched in the order listed.
14126
14127 To ease comparison, please keep this table in the same order as
14128 gcc's mips_cpu_info_table[]. */
14129static const struct mips_cpu_info mips_cpu_info_table[] =
14130{
14131 /* Entries for generic ISAs */

--- 37 unchanged lines hidden (view full) ---

14169 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14170 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14171 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14172 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14173 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14174 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14175 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14176 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14472/* A table describing all the processors gas knows about. Names are
14473 matched in the order listed.
14474
14475 To ease comparison, please keep this table in the same order as
14476 gcc's mips_cpu_info_table[]. */
14477static const struct mips_cpu_info mips_cpu_info_table[] =
14478{
14479 /* Entries for generic ISAs */

--- 37 unchanged lines hidden (view full) ---

14517 { "vr5400", 0, ISA_MIPS4, CPU_VR5400 },
14518 { "vr5500", 0, ISA_MIPS4, CPU_VR5500 },
14519 { "rm5200", 0, ISA_MIPS4, CPU_R5000 },
14520 { "rm5230", 0, ISA_MIPS4, CPU_R5000 },
14521 { "rm5231", 0, ISA_MIPS4, CPU_R5000 },
14522 { "rm5261", 0, ISA_MIPS4, CPU_R5000 },
14523 { "rm5721", 0, ISA_MIPS4, CPU_R5000 },
14524 { "rm7000", 0, ISA_MIPS4, CPU_RM7000 },
14177 { "rm9000", 0, ISA_MIPS4, CPU_RM7000 },
14525 { "rm9000", 0, ISA_MIPS4, CPU_RM9000 },
14178
14179 /* MIPS 32 */
14180 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14181 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14182 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14183
14526
14527 /* MIPS 32 */
14528 { "4kc", 0, ISA_MIPS32, CPU_MIPS32 },
14529 { "4km", 0, ISA_MIPS32, CPU_MIPS32 },
14530 { "4kp", 0, ISA_MIPS32, CPU_MIPS32 },
14531
14532 /* MIPS32 Release 2 */
14533 { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14534 { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14535 { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14536 { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14537 { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 },
14538
14184 /* MIPS 64 */
14185 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14539 /* MIPS 64 */
14540 { "5kc", 0, ISA_MIPS64, CPU_MIPS64 },
14541 { "5kf", 0, ISA_MIPS64, CPU_MIPS64 },
14186 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14187
14188 /* Broadcom SB-1 CPU core */
14189 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14190
14542 { "20kc", 0, ISA_MIPS64, CPU_MIPS64 },
14543
14544 /* Broadcom SB-1 CPU core */
14545 { "sb1", 0, ISA_MIPS64, CPU_SB1 },
14546
14547 /* Cavium Networks Octeon CPU core */
14548 { "octeon", 0, ISA_MIPS64R2, CPU_OCTEON },
14549
14191 /* End marker */
14192 { NULL, 0, 0, 0 }
14193};
14194
14195
14196/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14197 with a final "000" replaced by "k". Ignore case.
14198

--- 150 unchanged lines hidden (view full) ---

14349void
14350md_show_usage (FILE *stream)
14351{
14352 int column, first;
14353 size_t i;
14354
14355 fprintf (stream, _("\
14356MIPS options:\n\
14550 /* End marker */
14551 { NULL, 0, 0, 0 }
14552};
14553
14554
14555/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
14556 with a final "000" replaced by "k". Ignore case.
14557

--- 150 unchanged lines hidden (view full) ---

14708void
14709md_show_usage (FILE *stream)
14710{
14711 int column, first;
14712 size_t i;
14713
14714 fprintf (stream, _("\
14715MIPS options:\n\
14357-membedded-pic generate embedded position independent code\n\
14358-EB generate big endian output\n\
14359-EL generate little endian output\n\
14360-g, -g2 do not remove unneeded NOPs or swap branches\n\
14361-G NUM allow referencing objects up to NUM bytes\n\
14362 implicitly with the gp register [default 8]\n"));
14363 fprintf (stream, _("\
14364-mips1 generate MIPS ISA I instructions\n\
14365-mips2 generate MIPS ISA II instructions\n\

--- 25 unchanged lines hidden (view full) ---

14391 show (stream, "4100", &column, &first);
14392 show (stream, "4650", &column, &first);
14393 fputc ('\n', stream);
14394
14395 fprintf (stream, _("\
14396-mips16 generate mips16 instructions\n\
14397-no-mips16 do not generate mips16 instructions\n"));
14398 fprintf (stream, _("\
14716-EB generate big endian output\n\
14717-EL generate little endian output\n\
14718-g, -g2 do not remove unneeded NOPs or swap branches\n\
14719-G NUM allow referencing objects up to NUM bytes\n\
14720 implicitly with the gp register [default 8]\n"));
14721 fprintf (stream, _("\
14722-mips1 generate MIPS ISA I instructions\n\
14723-mips2 generate MIPS ISA II instructions\n\

--- 25 unchanged lines hidden (view full) ---

14749 show (stream, "4100", &column, &first);
14750 show (stream, "4650", &column, &first);
14751 fputc ('\n', stream);
14752
14753 fprintf (stream, _("\
14754-mips16 generate mips16 instructions\n\
14755-no-mips16 do not generate mips16 instructions\n"));
14756 fprintf (stream, _("\
14757-mdsp generate DSP instructions\n\
14758-mno-dsp do not generate DSP instructions\n"));
14759 fprintf (stream, _("\
14760-mmt generate MT instructions\n\
14761-mno-mt do not generate MT instructions\n"));
14762 fprintf (stream, _("\
14399-mfix-vr4120 work around certain VR4120 errata\n\
14763-mfix-vr4120 work around certain VR4120 errata\n\
14764-mfix-vr4130 work around VR4130 mflo/mfhi errata\n\
14400-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14401-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14765-mgp32 use 32-bit GPRs, regardless of the chosen ISA\n\
14766-mfp32 use 32-bit FPRs, regardless of the chosen ISA\n\
14767-mno-shared optimize output for executables\n\
14768-msym32 assume all symbols have 32-bit values\n\
14402-O0 remove unneeded NOPs, do not swap branches\n\
14403-O remove unneeded NOPs and swap branches\n\
14404--[no-]construct-floats [dis]allow floating point values to be constructed\n\
14405--trap, --no-break trap exception on div by 0 and mult overflow\n\
14406--break, --no-trap break exception on div by 0 and mult overflow\n"));
14407#ifdef OBJ_ELF
14408 fprintf (stream, _("\
14409-KPIC, -call_shared generate SVR4 position independent code\n\
14410-non_shared do not generate position independent code\n\
14411-xgot assume a 32 bit GOT\n\
14412-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14769-O0 remove unneeded NOPs, do not swap branches\n\
14770-O remove unneeded NOPs and swap branches\n\
14771--[no-]construct-floats [dis]allow floating point values to be constructed\n\
14772--trap, --no-break trap exception on div by 0 and mult overflow\n\
14773--break, --no-trap break exception on div by 0 and mult overflow\n"));
14774#ifdef OBJ_ELF
14775 fprintf (stream, _("\
14776-KPIC, -call_shared generate SVR4 position independent code\n\
14777-non_shared do not generate position independent code\n\
14778-xgot assume a 32 bit GOT\n\
14779-mpdr, -mno-pdr enable/disable creation of .pdr sections\n\
14780-mshared, -mno-shared disable/enable .cpload optimization for\n\
14781 non-shared code\n\
14413-mabi=ABI create ABI conformant object file for:\n"));
14414
14415 first = 1;
14416
14417 show (stream, "32", &column, &first);
14418 show (stream, "o64", &column, &first);
14419 show (stream, "n32", &column, &first);
14420 show (stream, "64", &column, &first);
14421 show (stream, "eabi", &column, &first);
14422
14423 fputc ('\n', stream);
14424
14425 fprintf (stream, _("\
14426-32 create o32 ABI object file (default)\n\
14427-n32 create n32 ABI object file\n\
14428-64 create 64 ABI object file\n"));
14429#endif
14782-mabi=ABI create ABI conformant object file for:\n"));
14783
14784 first = 1;
14785
14786 show (stream, "32", &column, &first);
14787 show (stream, "o64", &column, &first);
14788 show (stream, "n32", &column, &first);
14789 show (stream, "64", &column, &first);
14790 show (stream, "eabi", &column, &first);
14791
14792 fputc ('\n', stream);
14793
14794 fprintf (stream, _("\
14795-32 create o32 ABI object file (default)\n\
14796-n32 create n32 ABI object file\n\
14797-64 create 64 ABI object file\n"));
14798#endif
14799 fprintf (stream, _("\
14800-mocteon-unsupported error on unsupported Octeon instructions\n\
14801-mno-octeon-unsupported do not error on unsupported Octeon instructions\n"));
14802 fprintf (stream, _("\
14803-mocteon-useun generate Octeon unaligned load/store instructions\n\
14804-mno-octeon-useun generate MIPS unaligned load/store instructions\n"));
14430}
14431
14432enum dwarf2_format
14433mips_dwarf2_format (void)
14434{
14805}
14806
14807enum dwarf2_format
14808mips_dwarf2_format (void)
14809{
14435 if (mips_abi == N64_ABI)
14810 if (HAVE_64BIT_SYMBOLS)
14436 {
14437#ifdef TE_IRIX
14438 return dwarf2_format_64bit_irix;
14439#else
14440 return dwarf2_format_64bit;
14441#endif
14442 }
14443 else
14444 return dwarf2_format_32bit;
14445}
14446
14447int
14448mips_dwarf2_addr_size (void)
14449{
14811 {
14812#ifdef TE_IRIX
14813 return dwarf2_format_64bit_irix;
14814#else
14815 return dwarf2_format_64bit;
14816#endif
14817 }
14818 else
14819 return dwarf2_format_32bit;
14820}
14821
14822int
14823mips_dwarf2_addr_size (void)
14824{
14450 if (mips_abi == N64_ABI)
14825 if (HAVE_64BIT_SYMBOLS)
14451 return 8;
14452 else
14453 return 4;
14454}
14826 return 8;
14827 else
14828 return 4;
14829}
14830
14831/* Standard calling conventions leave the CFA at SP on entry. */
14832void
14833mips_cfi_frame_initial_instructions (void)
14834{
14835 cfi_add_CFA_def_cfa_register (SP);
14836}
14837