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1.\" Copyright (c) 1999 Chris Costello
2.\" All rights reserved.
3.\"
4.\" Redistribution and use in source and binary forms, with or without
5.\" modification, are permitted provided that the following conditions
6.\" are met:
7.\" 1. Redistributions of source code must retain the above copyright
8.\" notice, this list of conditions and the following disclaimer.
9.\" 2. Redistributions in binary form must reproduce the above copyright
10.\" notice, this list of conditions and the following disclaimer in the
11.\" documentation and/or other materials provided with the distribution.
12.\"
13.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23.\" SUCH DAMAGE.
24.\"
25.\" $FreeBSD: head/usr.sbin/memcontrol/memcontrol.8 99968 2002-07-14 14:47:15Z charnier $
26.\"
27.Dd September 28, 1999
28.Dt MEMCONTROL 8
29.Os
30.Sh NAME
31.Nm memcontrol
32.Nd "control system cache behaviour with respect to memory"
33.Sh SYNOPSIS
34.Nm
35.Ar list
36.Op Fl a
37.Pp
38.Nm
39.Ar set
40.Fl b Ar base
41.Fl l Ar length
42.Fl o Ar owner
43.Ar attribute
44.Pp
45.Nm
46.Ar clear
47.Fl o Ar owner
48.Pp
49.Nm
50.Ar clear
51.Fl b Ar base
52.Fl l Ar length
53.Sh DESCRIPTION
54A number of supported system architectures allow the behaviour of the CPU
55cache to be programmed to behave differently depending on the region being
56written.
57.Pp
58The
59.Nm
60utility
61provides an interface to this facility, allowing CPU cache behavior to
62be altered for ranges of system physical memory.
63.Pp
64These ranges are typically power-of-2 aligned and sized, however the specific
65rules governing their layout vary between architectures. The
66.Nm
67utility does not attempt to enforce these rules, however the system will
68reject any attempt to set an illegal combination.
69.Bl -tag -width clear
70.It Ar list
71List range slots.
72.Bl -tag -width xxxxxx
73.It Op Fl a
74List all range slots, even those that are inactive
75.El
76.It Ar set
77Set memory range attributes.
78.Bl -tag -width xxxxxx
79.It Fl b Ar base
80Memory range base address
81.It Fl l Ar length
82Length of memory range in bytes, power of 2
83.It Fl o Ar owner
84Text identifier for this setting (7 char max)
85.It Ar attribute
86Attributes applied to this range; one of
87.Ar uncacheable ,
88.Ar write-combine ,
89.Ar write-through ,
90.Ar write-back ,
91.Ar write-protect
92.El
93.It Ar clear
94Clear memory range attributes.
95Ranges may be cleared by owner or by
96base/length combination.
97.Pp
98To clear based on ownership:
99.Bl -tag -width xxxxxx
100.It Fl o Ar owner
101All ranges with this owner will be cleared
102.El
103.Pp
104To clear based on the base/length combination:
105.Bl -tag -width xxxxxx
106.It Fl b Ar base
107Memory range base address
108.It Fl l Ar length
109Length of memory range in bytes, power of 2
110.El
111.Pp
112Base and length must exactly match an existing range.
113.El
114.Sh SEE ALSO
115.Xr mem 4