| isa.h (6715) | isa.h (9223) |
|---|---|
| 1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.h 5.7 (Berkeley) 5/9/91 | 1/*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 20 unchanged lines hidden (view full) --- 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)isa.h 5.7 (Berkeley) 5/9/91 |
| 37 * $Id: isa.h,v 1.13 1995/01/25 20:11:50 jmz Exp $ | 37 * $Id: isa.h,v 1.14 1995/02/25 20:26:14 phk Exp $ |
| 38 */ 39 40#ifndef _I386_ISA_ISA_H_ 41#define _I386_ISA_ISA_H_ 42 43/* BEWARE: Included in both assembler and C code */ | 38 */ 39 40#ifndef _I386_ISA_ISA_H_ 41#define _I386_ISA_ISA_H_ 42 43/* BEWARE: Included in both assembler and C code */ |
| 44 |
|
| 44/* 45 * ISA Bus conventions 46 */ 47 48/* 49 * Input / Output Port Assignments 50 */ | 45/* 46 * ISA Bus conventions 47 */ 48 49/* 50 * Input / Output Port Assignments 51 */ |
| 51 52#ifndef IO_BEGIN | 52#ifndef IO_ISABEGIN |
| 53#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 54 55 /* CPU Board */ | 53#define IO_ISABEGIN 0x000 /* 0x000 - Beginning of I/O Registers */ 54 55 /* CPU Board */ |
| 56#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 57#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 58#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ 59#define IO_TIMER1 0x040 /* 8253 Timer #1 */ 60#define IO_TIMER2 0x048 /* 8253 Timer #2 */ 61#define IO_KBD 0x060 /* 8042 Keyboard */ 62#define IO_PPI 0x061 /* Programmable Peripheral Interface */ 63#define IO_RTC 0x070 /* RTC */ 64#define IO_NMI IO_RTC /* NMI Control */ 65#define IO_DMAPG 0x080 /* DMA Page Registers */ 66#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 67#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 68#define IO_NPX 0x0F0 /* Numeric Coprocessor */ | 56#define IO_DMA1 0x000 /* 8237A DMA Controller #1 */ 57#define IO_ICU1 0x020 /* 8259A Interrupt Controller #1 */ 58#define IO_PMP1 0x026 /* 82347 Power Management Peripheral */ 59#define IO_TIMER1 0x040 /* 8253 Timer #1 */ 60#define IO_TIMER2 0x048 /* 8253 Timer #2 */ 61#define IO_KBD 0x060 /* 8042 Keyboard */ 62#define IO_PPI 0x061 /* Programmable Peripheral Interface */ 63#define IO_RTC 0x070 /* RTC */ 64#define IO_NMI IO_RTC /* NMI Control */ 65#define IO_DMAPG 0x080 /* DMA Page Registers */ 66#define IO_ICU2 0x0A0 /* 8259A Interrupt Controller #2 */ 67#define IO_DMA2 0x0C0 /* 8237A DMA Controller #2 */ 68#define IO_NPX 0x0F0 /* Numeric Coprocessor */ |
| 69 70 /* Cards */ 71 /* 0x100 - 0x16F Open */ 72 | 69 70 /* Cards */ 71 /* 0x100 - 0x16F Open */ 72 |
| 73#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ | 73#define IO_WD2 0x170 /* Secondary Fixed Disk Controller */ |
| 74 | 74 |
| 75#define IO_PMP2 0x178 /* 82347 Power Management Peripheral */ | 75#define IO_PMP2 0x178 /* 82347 Power Management Peripheral */ |
| 76 77 /* 0x17A - 0x1EF Open */ 78 | 76 77 /* 0x17A - 0x1EF Open */ 78 |
| 79#define IO_WD1 0x1f0 /* Primary Fixed Disk Controller */ 80#define IO_GAME 0x201 /* Game Controller */ | 79#define IO_WD1 0x1F0 /* Primary Fixed Disk Controller */ 80#define IO_GAME 0x201 /* Game Controller */ |
| 81 | 81 |
| 82#define IO_GSC1 0x270 /* -- 0x27B! GeniScan GS-4500 addr.grp. 1 */ 83#define IO_GSC2 0x2e0 /* GeniScan GS-4500 addr.grp. 2 */ 84#define IO_GSC3 0x370 /* GeniScan GS-4500 addr.grp. 3 */ 85#define IO_GSC4 0x3e0 /* GeniScan GS-4500 addr.grp. 4 */ | 82 /* 0x202 (?) - 0x26F Open */ |
| 86 | 83 |
| 87#define IO_LPT2 0x278 /* Parallel Port #2 */ | 84#define IO_GSC1 0x270 /* -- 0x27B! GeniScan GS-4500 addr.grp. 1 */ 85#define IO_LPT2 0x278 /* Parallel Port #2 */ |
| 88 | 86 |
| 89#define IO_COM4 0x2e8 /* COM4 i/o address */ | 87 /* 0x280 - 0x2DF Open */ |
| 90 | 88 |
| 89#define IO_GSC2 0x2E0 /* GeniScan GS-4500 addr.grp. 2 */ 90#define IO_COM4 0x2E8 /* COM4 i/o address */ 91 |
|
| 91 /* 0x2F0 - 0x2F7 Open */ 92 | 92 /* 0x2F0 - 0x2F7 Open */ 93 |
| 93#define IO_COM2 0x2f8 /* COM2 i/o address */ | 94#define IO_COM2 0x2F8 /* COM2 i/o address */ 95 |
| 94 /* 0x300 - 0x32F Open */ 95 | 96 /* 0x300 - 0x32F Open */ 97 |
| 96#define IO_BT0 0x330 /* bustek 742a default addr. */ | |
| 97#define IO_AHA0 0x330 /* adaptec 1542 default addr. */ | 98#define IO_AHA0 0x330 /* adaptec 1542 default addr. */ |
| 99#define IO_BT0 0x330 /* bustek 742a default addr. */ |
|
| 98#define IO_UHA0 0x330 /* ultrastore 14f default addr. */ | 100#define IO_UHA0 0x330 /* ultrastore 14f default addr. */ |
| 99#define IO_BT1 0x334 /* bustek 742a default addr. */ | |
| 100#define IO_AHA1 0x334 /* adaptec 1542 default addr. */ | 101#define IO_AHA1 0x334 /* adaptec 1542 default addr. */ |
| 101 /* 0x338 - 0x36F Open */ | 102#define IO_BT1 0x334 /* bustek 742a default addr. */ |
| 102 | 103 |
| 103#define IO_FD2 0x370 /* secondary base i/o address */ 104#define IO_LPT1 0x378 /* Parallel Port #1 */ | 104 /* 0x340 - 0x36F Open */ |
| 105 | 105 |
| 106#define IO_GSC3 0x370 /* GeniScan GS-4500 addr.grp. 3 */ 107#define IO_FD2 0x370 /* secondary base i/o address */ 108#define IO_LPT1 0x378 /* Parallel Port #1 */ 109 |
|
| 106 /* 0x380 - 0x3AF Open */ 107 | 110 /* 0x380 - 0x3AF Open */ 111 |
| 108#define IO_MDA 0x3B0 /* Monochome Adapter */ 109#define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 110#define IO_VGA 0x3C0 /* E/VGA Ports */ 111#define IO_CGA 0x3D0 /* CGA Ports */ | 112#define IO_MDA 0x3B0 /* Monochome Adapter */ 113#define IO_LPT3 0x3BC /* Monochome Adapter Printer Port */ 114#define IO_VGA 0x3C0 /* E/VGA Ports */ 115#define IO_CGA 0x3D0 /* CGA Ports */ 116#define IO_GSC4 0x3E0 /* GeniScan GS-4500 addr.grp. 4 */ 117#define IO_COM3 0x3E8 /* COM3 i/o address */ 118#define IO_FD1 0x3F0 /* primary base i/o address */ 119#define IO_COM1 0x3F8 /* COM1 i/o address */ |
| 112 | 120 |
| 113 /* 0x3E0 - 0x3E7 Open */ | 121#define IO_ISAEND 0x3FF /* End (actually Max) of I/O Regs */ 122#endif /* IO_ISABEGIN */ |
| 114 | 123 |
| 115#define IO_COM3 0x3e8 /* COM3 i/o address */ 116#define IO_FD1 0x3f0 /* primary base i/o address */ 117#define IO_COM1 0x3f8 /* COM1 i/o address */ 118 119#define IO_ISAEND 0x3FF /* - 0x3FF End of I/O Registers */ 120#endif IO_ISABEGIN 121 | |
| 122/* 123 * Input / Output Port Sizes - these are from several sources, and tend | 124/* 125 * Input / Output Port Sizes - these are from several sources, and tend |
| 124 * to be the larger of what was found, ie COM ports can be 4, but some 125 * boards do not fully decode the address, thus 8 ports are used. | 126 * to be the larger of what was found. |
| 126 */ | 127 */ |
| 127 | |
| 128#ifndef IO_ISASIZES 129#define IO_ISASIZES 130 | 128#ifndef IO_ISASIZES 129#define IO_ISASIZES 130 |
| 131#define IO_COMSIZE 8 /* 8250, 16X50 com controllers (4?) */ | 131#define IO_COMSIZE 8 /* 8250, 16x50 com controllers */ |
| 132#define IO_CGASIZE 16 /* CGA controllers */ 133#define IO_DMASIZE 16 /* 8237 DMA controllers */ 134#define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */ 135#define IO_FDCSIZE 8 /* Nec765 floppy controllers */ 136#define IO_WDCSIZE 8 /* WD compatible disk controllers */ 137#define IO_GAMSIZE 16 /* AT compatible game controllers */ 138#define IO_ICUSIZE 16 /* 8259A interrupt controllers */ 139#define IO_KBDSIZE 16 /* 8042 Keyboard controllers */ 140#define IO_LPTSIZE 8 /* LPT controllers, some use only 4 */ 141#define IO_MDASIZE 16 /* Monochrome display controllers */ 142#define IO_RTCSIZE 16 /* CMOS real time clock, NMI control */ 143#define IO_TMRSIZE 16 /* 8253 programmable timers */ 144#define IO_NPXSIZE 16 /* 80387/80487 NPX registers */ 145#define IO_VGASIZE 16 /* VGA controllers */ | 132#define IO_CGASIZE 16 /* CGA controllers */ 133#define IO_DMASIZE 16 /* 8237 DMA controllers */ 134#define IO_DPGSIZE 32 /* 74LS612 DMA page reisters */ 135#define IO_FDCSIZE 8 /* Nec765 floppy controllers */ 136#define IO_WDCSIZE 8 /* WD compatible disk controllers */ 137#define IO_GAMSIZE 16 /* AT compatible game controllers */ 138#define IO_ICUSIZE 16 /* 8259A interrupt controllers */ 139#define IO_KBDSIZE 16 /* 8042 Keyboard controllers */ 140#define IO_LPTSIZE 8 /* LPT controllers, some use only 4 */ 141#define IO_MDASIZE 16 /* Monochrome display controllers */ 142#define IO_RTCSIZE 16 /* CMOS real time clock, NMI control */ 143#define IO_TMRSIZE 16 /* 8253 programmable timers */ 144#define IO_NPXSIZE 16 /* 80387/80487 NPX registers */ 145#define IO_VGASIZE 16 /* VGA controllers */ |
| 146#define IO_EISASIZE 256 /* EISA controllers */ | 146#define IO_EISASIZE 256 /* EISA controllers */ |
| 147#define IO_PMPSIZE 2 /* 82347 power management peripheral */ 148 | 147#define IO_PMPSIZE 2 /* 82347 power management peripheral */ 148 |
| 149#endif /* IO_ISASIZES */ | 149#endif /* IO_ISASIZES */ |
| 150 151/* 152 * Input / Output Memory Physical Addresses 153 */ | 150 151/* 152 * Input / Output Memory Physical Addresses 153 */ |
| 154 | |
| 155#ifndef IOM_BEGIN | 154#ifndef IOM_BEGIN |
| 156#define IOM_BEGIN 0x0a0000 /* Start of I/O Memory "hole" */ 157#define IOM_END 0x100000 /* End of I/O Memory "hole" */ | 155#define IOM_BEGIN 0x0A0000 /* Start of I/O Memory "hole" */ 156#define IOM_END 0x100000 /* End of I/O Memory "hole" */ |
| 158#define IOM_SIZE (IOM_END - IOM_BEGIN) | 157#define IOM_SIZE (IOM_END - IOM_BEGIN) |
| 159#endif IOM_BEGIN | 158#endif /* IOM_BEGIN */ |
| 160 161/* 162 * RAM Physical Address Space (ignoring the above mentioned "hole") 163 */ | 159 160/* 161 * RAM Physical Address Space (ignoring the above mentioned "hole") 162 */ |
| 164 | |
| 165#ifndef RAM_BEGIN 166#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ 167#define RAM_END 0x1000000 /* End of RAM Memory */ 168#define RAM_SIZE (RAM_END - RAM_BEGIN) | 163#ifndef RAM_BEGIN 164#define RAM_BEGIN 0x0000000 /* Start of RAM Memory */ 165#define RAM_END 0x1000000 /* End of RAM Memory */ 166#define RAM_SIZE (RAM_END - RAM_BEGIN) |
| 169#endif RAM_BEGIN | 167#endif /* RAM_BEGIN */ |
| 170 171/* 172 * Oddball Physical Memory Addresses 173 */ 174#ifndef COMPAQ_RAMRELOC | 168 169/* 170 * Oddball Physical Memory Addresses 171 */ 172#ifndef COMPAQ_RAMRELOC |
| 175#define COMPAQ_RAMRELOC 0x80c00000 /* Compaq RAM relocation/diag */ 176#define COMPAQ_RAMSETUP 0x80c00002 /* Compaq RAM setup */ | 173#define COMPAQ_RAMRELOC 0x80C00000 /* Compaq RAM relocation/diag */ 174#define COMPAQ_RAMSETUP 0x80C00002 /* Compaq RAM setup */ |
| 177#define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 178#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ | 175#define WEITEK_FPU 0xC0000000 /* WTL 2167 */ 176#define CYRIX_EMC 0xC0000000 /* Cyrix EMC */ |
| 179#endif COMPAQ_RAMRELOC | 177#endif /* COMPAQ_RAMRELOC */ |
| 180 181#endif /* !_I386_ISA_ISA_H_ */ | 178 179#endif /* !_I386_ISA_ISA_H_ */ |