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intel_drv.c (257251) intel_drv.c (259512)
1/*-
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 14 unchanged lines hidden (view full) ---

23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2013 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without

--- 14 unchanged lines hidden (view full) ---

23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#include <sys/cdefs.h>
31__FBSDID("$FreeBSD: head/sys/x86/iommu/intel_drv.c 257251 2013-10-28 13:33:29Z kib $");
31__FBSDID("$FreeBSD: stable/10/sys/x86/iommu/intel_drv.c 259512 2013-12-17 13:49:35Z kib $");
32
33#include "opt_acpi.h"
34#if defined(__amd64__) /* || defined(__ia64__) */
35#define DEV_APIC
36#else
37#include "opt_apic.h"
38#endif
39#include "opt_ddb.h"

--- 26 unchanged lines hidden (view full) ---

66#include <x86/iommu/busdma_dmar.h>
67#include <x86/iommu/intel_dmar.h>
68#include <dev/pci/pcivar.h>
69
70#ifdef DEV_APIC
71#include "pcib_if.h"
72#endif
73
32
33#include "opt_acpi.h"
34#if defined(__amd64__) /* || defined(__ia64__) */
35#define DEV_APIC
36#else
37#include "opt_apic.h"
38#endif
39#include "opt_ddb.h"

--- 26 unchanged lines hidden (view full) ---

66#include <x86/iommu/busdma_dmar.h>
67#include <x86/iommu/intel_dmar.h>
68#include <dev/pci/pcivar.h>
69
70#ifdef DEV_APIC
71#include "pcib_if.h"
72#endif
73
74#define DMAR_REG_RID 1
75#define DMAR_IRQ_RID 0
74#define DMAR_FAULT_IRQ_RID 0
75#define DMAR_QI_IRQ_RID 1
76#define DMAR_REG_RID 2
76
77static devclass_t dmar_devclass;
78static device_t *dmar_devs;
79static int dmar_devcnt;
80
81typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
82
83static void

--- 128 unchanged lines hidden (view full) ---

212
213static int
214dmar_probe(device_t dev)
215{
216
217 if (acpi_get_handle(dev) != NULL)
218 return (ENXIO);
219 device_set_desc(dev, "DMA remap");
77
78static devclass_t dmar_devclass;
79static device_t *dmar_devs;
80static int dmar_devcnt;
81
82typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
83
84static void

--- 128 unchanged lines hidden (view full) ---

213
214static int
215dmar_probe(device_t dev)
216{
217
218 if (acpi_get_handle(dev) != NULL)
219 return (ENXIO);
220 device_set_desc(dev, "DMA remap");
220 return (0);
221 return (BUS_PROBE_NOWILDCARD);
221}
222
223static void
222}
223
224static void
225dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
226{
227 struct dmar_msi_data *dmd;
228
229 dmd = &unit->intrs[idx];
230 if (dmd->irq == -1)
231 return;
232 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
233 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
234 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
235 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
236 dev, dmd->irq);
237 dmd->irq = -1;
238}
239
240static void
224dmar_release_resources(device_t dev, struct dmar_unit *unit)
225{
241dmar_release_resources(device_t dev, struct dmar_unit *unit)
242{
243 int i;
226
227 dmar_fini_busdma(unit);
244
245 dmar_fini_busdma(unit);
246 dmar_fini_qi(unit);
228 dmar_fini_fault_log(unit);
247 dmar_fini_fault_log(unit);
229 if (unit->irq != -1) {
230 bus_teardown_intr(dev, unit->irq_res, unit->intr_handle);
231 bus_release_resource(dev, SYS_RES_IRQ, unit->irq_rid,
232 unit->irq_res);
233 bus_delete_resource(dev, SYS_RES_IRQ, unit->irq_rid);
234 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
235 dev, unit->irq);
236 unit->irq = -1;
237 }
248 for (i = 0; i < DMAR_INTR_TOTAL; i++)
249 dmar_release_intr(dev, unit, i);
238 if (unit->regs != NULL) {
239 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
240 unit->regs);
241 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
242 unit->regs);
243 unit->regs = NULL;
244 }
245 if (unit->domids != NULL) {
246 delete_unrhdr(unit->domids);
247 unit->domids = NULL;
248 }
249 if (unit->ctx_obj != NULL) {
250 vm_object_deallocate(unit->ctx_obj);
251 unit->ctx_obj = NULL;
252 }
253}
254
255static int
250 if (unit->regs != NULL) {
251 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
252 unit->regs);
253 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
254 unit->regs);
255 unit->regs = NULL;
256 }
257 if (unit->domids != NULL) {
258 delete_unrhdr(unit->domids);
259 unit->domids = NULL;
260 }
261 if (unit->ctx_obj != NULL) {
262 vm_object_deallocate(unit->ctx_obj);
263 unit->ctx_obj = NULL;
264 }
265}
266
267static int
256dmar_alloc_irq(device_t dev, struct dmar_unit *unit)
268dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
257{
258 device_t pcib;
269{
270 device_t pcib;
271 struct dmar_msi_data *dmd;
259 uint64_t msi_addr;
260 uint32_t msi_data;
261 int error;
262
272 uint64_t msi_addr;
273 uint32_t msi_data;
274 int error;
275
276 dmd = &unit->intrs[idx];
263 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
277 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
264 error = PCIB_ALLOC_MSIX(pcib, dev, &unit->irq);
278 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
265 if (error != 0) {
279 if (error != 0) {
266 device_printf(dev, "cannot allocate fault interrupt, %d\n",
267 error);
280 device_printf(dev, "cannot allocate %s interrupt, %d\n",
281 dmd->name, error);
268 goto err1;
269 }
282 goto err1;
283 }
270 unit->irq_rid = DMAR_IRQ_RID;
271 error = bus_set_resource(dev, SYS_RES_IRQ, unit->irq_rid, unit->irq,
272 1);
284 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
285 dmd->irq, 1);
273 if (error != 0) {
286 if (error != 0) {
274 device_printf(dev, "cannot set interrupt resource, %d\n",
275 error);
287 device_printf(dev, "cannot set %s interrupt resource, %d\n",
288 dmd->name, error);
276 goto err2;
277 }
289 goto err2;
290 }
278 unit->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
279 &unit->irq_rid, RF_ACTIVE);
280 if (unit->irq_res == NULL) {
281 device_printf(dev, "cannot map fault interrupt\n");
291 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
292 &dmd->irq_rid, RF_ACTIVE);
293 if (dmd->irq_res == NULL) {
294 device_printf(dev,
295 "cannot allocate resource for %s interrupt\n", dmd->name);
282 error = ENXIO;
283 goto err3;
284 }
296 error = ENXIO;
297 goto err3;
298 }
285 error = bus_setup_intr(dev, unit->irq_res, INTR_TYPE_MISC,
286 dmar_intr, NULL, unit, &unit->intr_handle);
299 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
300 dmd->handler, NULL, unit, &dmd->intr_handle);
287 if (error != 0) {
301 if (error != 0) {
288 device_printf(dev, "cannot setup fault interrupt, %d\n", error);
302 device_printf(dev, "cannot setup %s interrupt, %d\n",
303 dmd->name, error);
289 goto err4;
290 }
304 goto err4;
305 }
291 bus_describe_intr(dev, unit->irq_res, unit->intr_handle, "fault");
292 error = PCIB_MAP_MSI(pcib, dev, unit->irq, &msi_addr, &msi_data);
306 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, dmd->name);
307 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
293 if (error != 0) {
308 if (error != 0) {
294 device_printf(dev, "cannot map interrupt, %d\n", error);
309 device_printf(dev, "cannot map %s interrupt, %d\n",
310 dmd->name, error);
295 goto err5;
296 }
311 goto err5;
312 }
297 dmar_write4(unit, DMAR_FEDATA_REG, msi_data);
298 dmar_write4(unit, DMAR_FEADDR_REG, msi_addr);
313 dmar_write4(unit, dmd->msi_data_reg, msi_data);
314 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
299 /* Only for xAPIC mode */
315 /* Only for xAPIC mode */
300 dmar_write4(unit, DMAR_FEUADDR_REG, msi_addr >> 32);
316 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
301 return (0);
302
303err5:
317 return (0);
318
319err5:
304 bus_teardown_intr(dev, unit->irq_res, unit->intr_handle);
320 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
305err4:
321err4:
306 bus_release_resource(dev, SYS_RES_IRQ, unit->irq_rid, unit->irq_res);
322 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
307err3:
323err3:
308 bus_delete_resource(dev, SYS_RES_IRQ, unit->irq_rid);
324 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
309err2:
325err2:
310 PCIB_RELEASE_MSIX(pcib, dev, unit->irq);
311 unit->irq = -1;
326 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
327 dmd->irq = -1;
312err1:
313 return (error);
314}
315
316#ifdef DEV_APIC
317static int
318dmar_remap_intr(device_t dev, device_t child, u_int irq)
319{
320 struct dmar_unit *unit;
328err1:
329 return (error);
330}
331
332#ifdef DEV_APIC
333static int
334dmar_remap_intr(device_t dev, device_t child, u_int irq)
335{
336 struct dmar_unit *unit;
337 struct dmar_msi_data *dmd;
321 uint64_t msi_addr;
322 uint32_t msi_data;
338 uint64_t msi_addr;
339 uint32_t msi_data;
323 int error;
340 int i, error;
324
325 unit = device_get_softc(dev);
341
342 unit = device_get_softc(dev);
326 if (irq != unit->irq)
327 return (ENOENT);
328 error = PCIB_MAP_MSI(device_get_parent(device_get_parent(dev)), dev,
329 irq, &msi_addr, &msi_data);
330 if (error != 0)
331 return (error);
332 dmar_disable_intr(unit);
333 dmar_write4(unit, DMAR_FEDATA_REG, msi_data);
334 dmar_write4(unit, DMAR_FEADDR_REG, msi_addr);
335 dmar_write4(unit, DMAR_FEUADDR_REG, msi_addr >> 32);
336 dmar_enable_intr(unit);
337 return (0);
343 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
344 dmd = &unit->intrs[i];
345 if (irq == dmd->irq) {
346 error = PCIB_MAP_MSI(device_get_parent(
347 device_get_parent(dev)),
348 dev, irq, &msi_addr, &msi_data);
349 if (error != 0)
350 return (error);
351 DMAR_LOCK(unit);
352 (dmd->disable_intr)(unit);
353 dmar_write4(unit, dmd->msi_data_reg, msi_data);
354 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
355 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
356 (dmd->enable_intr)(unit);
357 DMAR_UNLOCK(unit);
358 return (0);
359 }
360 }
361 return (ENOENT);
338}
339#endif
340
341static void
342dmar_print_caps(device_t dev, struct dmar_unit *unit,
343 ACPI_DMAR_HARDWARE_UNIT *dmaru)
344{
345 uint32_t caphi, ecaphi;

--- 21 unchanged lines hidden (view full) ---

367 DMAR_ECAP_IRO(unit->hw_ecap));
368}
369
370static int
371dmar_attach(device_t dev)
372{
373 struct dmar_unit *unit;
374 ACPI_DMAR_HARDWARE_UNIT *dmaru;
362}
363#endif
364
365static void
366dmar_print_caps(device_t dev, struct dmar_unit *unit,
367 ACPI_DMAR_HARDWARE_UNIT *dmaru)
368{
369 uint32_t caphi, ecaphi;

--- 21 unchanged lines hidden (view full) ---

391 DMAR_ECAP_IRO(unit->hw_ecap));
392}
393
394static int
395dmar_attach(device_t dev)
396{
397 struct dmar_unit *unit;
398 ACPI_DMAR_HARDWARE_UNIT *dmaru;
375 int error;
399 int i, error;
376
377 unit = device_get_softc(dev);
378 unit->dev = dev;
379 unit->unit = device_get_unit(dev);
380 dmaru = dmar_find_by_index(unit->unit);
381 if (dmaru == NULL)
382 return (EINVAL);
400
401 unit = device_get_softc(dev);
402 unit->dev = dev;
403 unit->unit = device_get_unit(dev);
404 dmaru = dmar_find_by_index(unit->unit);
405 if (dmaru == NULL)
406 return (EINVAL);
383 unit->irq = -1;
384 unit->segment = dmaru->Segment;
385 unit->base = dmaru->Address;
386 unit->reg_rid = DMAR_REG_RID;
387 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
388 &unit->reg_rid, RF_ACTIVE);
389 if (unit->regs == NULL) {
390 device_printf(dev, "cannot allocate register window\n");
391 return (ENOMEM);
392 }
393 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
394 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
395 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
396 if (bootverbose)
397 dmar_print_caps(dev, unit, dmaru);
398 dmar_quirks_post_ident(unit);
399
407 unit->segment = dmaru->Segment;
408 unit->base = dmaru->Address;
409 unit->reg_rid = DMAR_REG_RID;
410 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
411 &unit->reg_rid, RF_ACTIVE);
412 if (unit->regs == NULL) {
413 device_printf(dev, "cannot allocate register window\n");
414 return (ENOMEM);
415 }
416 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
417 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
418 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
419 if (bootverbose)
420 dmar_print_caps(dev, unit, dmaru);
421 dmar_quirks_post_ident(unit);
422
400 error = dmar_alloc_irq(dev, unit);
423 for (i = 0; i < DMAR_INTR_TOTAL; i++)
424 unit->intrs[i].irq = -1;
425
426 unit->intrs[DMAR_INTR_FAULT].name = "fault";
427 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
428 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
429 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
430 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
431 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
432 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
433 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
434 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
401 if (error != 0) {
402 dmar_release_resources(dev, unit);
403 return (error);
404 }
435 if (error != 0) {
436 dmar_release_resources(dev, unit);
437 return (error);
438 }
439 if (DMAR_HAS_QI(unit)) {
440 unit->intrs[DMAR_INTR_QI].name = "qi";
441 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
442 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
443 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
444 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
445 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
446 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
447 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
448 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
449 if (error != 0) {
450 dmar_release_resources(dev, unit);
451 return (error);
452 }
453 }
454
405 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
406 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
407 &unit->lock);
408
409 /*
410 * 9.2 "Context Entry":
411 * When Caching Mode (CM) field is reported as Set, the
412 * domain-id value of zero is architecturally reserved.

--- 35 unchanged lines hidden (view full) ---

448 }
449
450 DMAR_UNLOCK(unit);
451 error = dmar_init_fault_log(unit);
452 if (error != 0) {
453 dmar_release_resources(dev, unit);
454 return (error);
455 }
455 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
456 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
457 &unit->lock);
458
459 /*
460 * 9.2 "Context Entry":
461 * When Caching Mode (CM) field is reported as Set, the
462 * domain-id value of zero is architecturally reserved.

--- 35 unchanged lines hidden (view full) ---

498 }
499
500 DMAR_UNLOCK(unit);
501 error = dmar_init_fault_log(unit);
502 if (error != 0) {
503 dmar_release_resources(dev, unit);
504 return (error);
505 }
506 error = dmar_init_qi(unit);
507 if (error != 0) {
508 dmar_release_resources(dev, unit);
509 return (error);
510 }
456 error = dmar_init_busdma(unit);
457 if (error != 0) {
458 dmar_release_resources(dev, unit);
459 return (error);
460 }
461
462#ifdef NOTYET
463 DMAR_LOCK(unit);

--- 376 unchanged lines hidden (view full) ---

840 if (resmem->Segment != iria->dmar->segment)
841 return (1);
842 if (dmar_match_verbose) {
843 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
844 (uintmax_t)resmem->BaseAddress,
845 (uintmax_t)resmem->EndAddress);
846 }
847
511 error = dmar_init_busdma(unit);
512 if (error != 0) {
513 dmar_release_resources(dev, unit);
514 return (error);
515 }
516
517#ifdef NOTYET
518 DMAR_LOCK(unit);

--- 376 unchanged lines hidden (view full) ---

895 if (resmem->Segment != iria->dmar->segment)
896 return (1);
897 if (dmar_match_verbose) {
898 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
899 (uintmax_t)resmem->BaseAddress,
900 (uintmax_t)resmem->EndAddress);
901 }
902
848 ptr = (char *)resmem + sizeof(*resmem);
849 ptrend = (char *)resmem + resmem->Header.Length;
903 ptr = (const char *)resmem + sizeof(*resmem);
904 ptrend = (const char *)resmem + resmem->Header.Length;
850 for (;;) {
851 if (ptr >= ptrend)
852 break;
905 for (;;) {
906 if (ptr >= ptrend)
907 break;
853 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
908 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
854 ptr += devscope->Length;
855 /* XXXKIB bridge */
856 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
857 continue;
858 if (dmar_match_verbose) {
859 dmar_print_path(iria->dmar->dev, "RMRR scope",
860 devscope->Bus, (devscope->Length -
861 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
909 ptr += devscope->Length;
910 /* XXXKIB bridge */
911 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
912 continue;
913 if (dmar_match_verbose) {
914 dmar_print_path(iria->dmar->dev, "RMRR scope",
915 devscope->Bus, (devscope->Length -
916 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
862 (ACPI_DMAR_PCI_PATH *)(devscope + 1));
917 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
863 }
864 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
865 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
918 }
919 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
920 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
866 (ACPI_DMAR_PCI_PATH *)(devscope + 1));
921 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
867 if (dev == NULL) {
868 if (dmar_match_verbose)
869 printf("null dev\n");
870 continue;
871 }
872 dev_dmar = dmar_find(dev);
873 if (dev_dmar != iria->dmar) {
874 if (dmar_match_verbose) {

--- 114 unchanged lines hidden (view full) ---

989 if (t != tIDENT) {
990 db_printf("Bad modifier\n");
991 db_radix = radix;
992 db_skip_to_eol();
993 return;
994 }
995 show_mappings = strchr(db_tok_string, 'm') != NULL;
996 t = db_read_token();
922 if (dev == NULL) {
923 if (dmar_match_verbose)
924 printf("null dev\n");
925 continue;
926 }
927 dev_dmar = dmar_find(dev);
928 if (dev_dmar != iria->dmar) {
929 if (dmar_match_verbose) {

--- 114 unchanged lines hidden (view full) ---

1044 if (t != tIDENT) {
1045 db_printf("Bad modifier\n");
1046 db_radix = radix;
1047 db_skip_to_eol();
1048 return;
1049 }
1050 show_mappings = strchr(db_tok_string, 'm') != NULL;
1051 t = db_read_token();
1052 } else {
1053 show_mappings = false;
997 }
998 if (t == tNUMBER) {
999 domain = db_tok_number;
1000 t = db_read_token();
1001 if (t == tNUMBER) {
1002 bus = db_tok_number;
1003 t = db_read_token();
1004 if (t == tNUMBER) {

--- 48 unchanged lines hidden (view full) ---

1053 dmar_read4(unit, DMAR_FEUADDR_REG));
1054 db_printf("primary fault log:\n");
1055 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1056 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1057 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1058 (uintmax_t)dmar_read8(unit, frir),
1059 (uintmax_t)dmar_read8(unit, frir + 8));
1060 }
1054 }
1055 if (t == tNUMBER) {
1056 domain = db_tok_number;
1057 t = db_read_token();
1058 if (t == tNUMBER) {
1059 bus = db_tok_number;
1060 t = db_read_token();
1061 if (t == tNUMBER) {

--- 48 unchanged lines hidden (view full) ---

1110 dmar_read4(unit, DMAR_FEUADDR_REG));
1111 db_printf("primary fault log:\n");
1112 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1113 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1114 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1115 (uintmax_t)dmar_read8(unit, frir),
1116 (uintmax_t)dmar_read8(unit, frir + 8));
1117 }
1118 if (DMAR_HAS_QI(unit)) {
1119 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1120 dmar_read4(unit, DMAR_IEDATA_REG),
1121 dmar_read4(unit, DMAR_IEADDR_REG),
1122 dmar_read4(unit, DMAR_IEUADDR_REG));
1123 if (unit->qi_enabled) {
1124 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1125 "size 0x%jx\n"
1126 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1127 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1128 (uintmax_t)unit->inv_queue,
1129 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1130 (uintmax_t)unit->inv_queue_size,
1131 dmar_read4(unit, DMAR_IQH_REG),
1132 dmar_read4(unit, DMAR_IQT_REG),
1133 unit->inv_queue_avail,
1134 dmar_read4(unit, DMAR_ICS_REG),
1135 dmar_read4(unit, DMAR_IECTL_REG),
1136 unit->inv_waitd_seq_hw,
1137 &unit->inv_waitd_seq_hw,
1138 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1139 unit->inv_waitd_seq,
1140 unit->inv_waitd_gen);
1141 } else {
1142 db_printf("qi is disabled\n");
1143 }
1144 }
1061 if (show_ctxs) {
1062 db_printf("contexts:\n");
1063 LIST_FOREACH(ctx, &unit->contexts, link) {
1064 dmar_print_ctx(ctx, show_mappings);
1065 if (db_pager_quit)
1066 break;
1067 }
1068 }

--- 30 unchanged lines hidden --- 		1145 if (show_ctxs) {
1146 db_printf("contexts:\n");
1147 LIST_FOREACH(ctx, &unit->contexts, link) {
1148 dmar_print_ctx(ctx, show_mappings);
1149 if (db_pager_quit)
1150 break;
1151 }
1152 }

--- 30 unchanged lines hidden ---