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< __FBSDID("$FreeBSD: head/sys/i386/cpufreq/powernow.c 158651 2006-05-16 14:37:58Z phk $");
---
> __FBSDID("$FreeBSD: head/sys/i386/cpufreq/powernow.c 166197 2007-01-23 19:20:30Z bruno $");
57a58,66
> /* Flags for some hardware bugs. */
> #define A0_ERRATA 0x1 /* Bugs for the rev. A0 of Athlon (K7):
> * Interrupts must be disabled and no half
> * multipliers are allowed */
> #define PENDING_STUCK 0x2 /* With some buggy chipset and some newer AMD64
> * processor (Rev. G?):
> * the pending bit from the msr FIDVID_STATUS
> * is set forever. No workaround :( */
>
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< #define READ_PENDING_WAIT(status) \
< do { \
< (status) = rdmsr(MSR_AMDK7_FIDVID_STATUS); \
< } while (PN8_STA_PENDING(status))
<
167,171c171,179
< static int pn8_fid_to_mult[32] = {
< 40, 50, 60, 70, 80, 90, 100, 110,
< 120, 130, 140, 150, 160, 170, 180, 190,
< 220, 230, 240, 250, 260, 270, 280, 290,
< 300, 310, 320, 330, 340, 350,
---
> static int pn8_fid_to_mult[64] = {
> 40, 45, 50, 55, 60, 65, 70, 75,
> 80, 85, 90, 95, 100, 105, 110, 115,
> 120, 125, 130, 135, 140, 145, 150, 155,
> 160, 165, 170, 175, 180, 185, 190, 195,
> 200, 205, 210, 215, 220, 225, 230, 235,
> 240, 245, 250, 255, 260, 265, 270, 275,
> 280, 285, 290, 295, 300, 305, 310, 315,
> 320, 325, 330, 335, 340, 345, 350, 355,
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< int errata_a0;
---
> u_int errata;
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< if (sc->errata_a0)
---
> if (sc->errata & A0_ERRATA)
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< if (sc->errata_a0)
---
> if (sc->errata & A0_ERRATA)
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> pn8_read_pending_wait(uint64_t *status)
> {
> int i = 10000;
>
> do
> *status = rdmsr(MSR_AMDK7_FIDVID_STATUS);
> while (PN8_STA_PENDING(*status) && --i);
>
> return (i == 0 ? ENXIO : 0);
> }
>
> static int
> pn8_write_fidvid(u_int fid, u_int vid, uint64_t ctrl, uint64_t *status)
> {
> int i = 100;
>
> do
> WRITE_FIDVID(fid, vid, ctrl);
> while (pn8_read_pending_wait(status) && --i);
>
> return (i == 0 ? ENXIO : 0);
> }
>
> static int
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> int rv;
315c348,351
< READ_PENDING_WAIT(status);
---
> rv = pn8_read_pending_wait(&status);
> if (rv)
> return (rv);
>
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< WRITE_FIDVID(cfid, (val > 0) ? val : 0, 1ULL);
< READ_PENDING_WAIT(status);
---
> rv = pn8_write_fidvid(cfid, (val > 0) ? val : 0, 1ULL, &status);
> if (rv) {
> sc->errata |= PENDING_STUCK;
> return (rv);
> }
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< WRITE_FIDVID(cfid, cvid - 1, 1ULL);
< READ_PENDING_WAIT(status);
---
> rv = pn8_write_fidvid(cfid, cvid - 1, 1ULL, &status);
> if (rv) {
> sc->errata |= PENDING_STUCK;
> return (rv);
> }
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< u_int vco_fid, vco_cfid;
---
> u_int vco_fid, vco_cfid, fid_delta;
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> fid_delta = (vco_cfid & 1) ? 1 : 2;
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< if (cfid > 6)
< val = cfid + 2;
---
> if (cfid > 7)
> val = cfid + fid_delta;
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< val = FID_TO_VCO_FID(cfid) + 2;
---
> val = FID_TO_VCO_FID(cfid) + fid_delta;
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< val = cfid - 2;
< WRITE_FIDVID(val, cvid, sc->pll * (uint64_t) sc->fsb);
< READ_PENDING_WAIT(status);
---
> val = cfid - fid_delta;
> rv = pn8_write_fidvid(val, cvid,
> sc->pll * (uint64_t) sc->fsb,
> &status);
> if (rv) {
> sc->errata |= PENDING_STUCK;
> return (rv);
> }
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< WRITE_FIDVID(fid, cvid, sc->pll * (uint64_t) sc->fsb);
< READ_PENDING_WAIT(status);
---
> rv = pn8_write_fidvid(fid, cvid,
> sc->pll * (uint64_t) sc->fsb,
> &status);
> if (rv) {
> sc->errata |= PENDING_STUCK;
> return (rv);
> }
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< WRITE_FIDVID(cfid, vid, 1ULL);
< READ_PENDING_WAIT(status);
---
> rv = pn8_write_fidvid(cfid, vid, 1ULL, &status);
384c436
< return (ENXIO);
---
> rv = ENXIO;
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< return (0);
---
> return (rv);
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> if (sc->errata & PENDING_STUCK)
> return (ENXIO);
>
432a488,489
> if (sc->errata & PENDING_STUCK)
> return (ENXIO);
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< if (sc->errata_a0 &&
---
> if ((sc->errata & A0_ERRATA) &&
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< state.freq = 100 * pn8_fid_to_mult[state.fid >> 1] *
< sc->fsb;
---
> state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
543c599
< * Fix powernow_max_states, if errata_a0 give us less states
---
> * Fix powernow_max_states, if errata a0 give us less states
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< sc->errata_a0 = TRUE;
---
> sc->errata |= A0_ERRATA;
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< sc->errata_a0 = TRUE;
---
> sc->errata |= A0_ERRATA;
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< if (sc->errata_a0 &&
---
> if ((sc->errata & A0_ERRATA) &&
769,770c825
< state.freq = 100 * pn8_fid_to_mult[state.fid >> 1] *
< sc->fsb;
---
> state.freq = 100 * pn8_fid_to_mult[state.fid] * sc->fsb;
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< sc->errata_a0 = FALSE;
---
> sc->errata = 0;
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< sc->fsb = rate / 100000 / pn8_fid_to_mult[cfid >> 1];
---
> sc->fsb = rate / 100000 / pn8_fid_to_mult[cfid];