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schizo.c (206020) schizo.c (208097)
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005, 2007, 2008 by Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 * from: FreeBSD: psycho.c 183152 2008-09-18 19:45:22Z marius
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 206020 2010-03-31 22:32:56Z marius $");
35__FBSDID("$FreeBSD: head/sys/sparc64/pci/schizo.c 208097 2010-05-14 20:00:21Z marius $");
36
37/*
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
39 * PCI 2.2 bridges
40 */
41
42#include "opt_ofw_pci.h"
43#include "opt_schizo.h"
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48#include <sys/kernel.h>
49#include <sys/lock.h>
50#include <sys/malloc.h>
51#include <sys/module.h>
52#include <sys/mutex.h>
53#include <sys/pcpu.h>
54#include <sys/rman.h>
36
37/*
38 * Driver for `Schizo' Fireplane/Safari to PCI 2.1 and `Tomatillo' JBus to
39 * PCI 2.2 bridges
40 */
41
42#include "opt_ofw_pci.h"
43#include "opt_schizo.h"
44
45#include <sys/param.h>
46#include <sys/systm.h>
47#include <sys/bus.h>
48#include <sys/kernel.h>
49#include <sys/lock.h>
50#include <sys/malloc.h>
51#include <sys/module.h>
52#include <sys/mutex.h>
53#include <sys/pcpu.h>
54#include <sys/rman.h>
55#include <sys/sysctl.h>
55#include <sys/time.h>
56#include <sys/timetc.h>
57
58#include <dev/ofw/ofw_bus.h>
59#include <dev/ofw/ofw_pci.h>
60#include <dev/ofw/openfirm.h>
61
62#include <machine/bus.h>

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380#ifdef SCHIZO_DEBUG
381 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
382 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
383 (unsigned long long)reg);
384#endif
385 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
386
387 /*
56#include <sys/time.h>
57#include <sys/timetc.h>
58
59#include <dev/ofw/ofw_bus.h>
60#include <dev/ofw/ofw_pci.h>
61#include <dev/ofw/openfirm.h>
62
63#include <machine/bus.h>

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381#ifdef SCHIZO_DEBUG
382 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
383 (unsigned long long)SCHIZO_PCI_READ_8(sc, STX_PCI_DIAG),
384 (unsigned long long)reg);
385#endif
386 SCHIZO_PCI_WRITE_8(sc, STX_PCI_DIAG, reg);
387
388 /*
389 * Enable DMA write parity error interrupts of version >= 7 (i.e.
390 * revision >= 2.5) Schizo.
391 */
392 if (mode == SCHIZO_MODE_SCZ && sc->sc_ver >= 7) {
393 reg = SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD);
394 reg |= SX_PCI_CFG_ICD_DMAW_PERR_IEN;
395#ifdef SCHIZO_DEBUG
396 device_printf(dev, "PCI CFG/ICD 0x%016llx -> 0x%016llx\n",
397 (unsigned long long)SCHIZO_PCI_READ_8(sc, SX_PCI_CFG_ICD),
398 (unsigned long long)reg);
399#endif
400 SCHIZO_PCI_WRITE_8(sc, SX_PCI_CFG_ICD, reg);
401 }
402
403 /*
388 * On Tomatillo clear the I/O prefetch lengths (workaround for a
389 * Jalapeno bug).
390 */
391 if (mode == SCHIZO_MODE_TOM)
392 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
393 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
394 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
395

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692 * Set the latency timer register as this isn't always done by the
693 * firmware.
694 */
695 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
696 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
697
698 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
699
404 * On Tomatillo clear the I/O prefetch lengths (workaround for a
405 * Jalapeno bug).
406 */
407 if (mode == SCHIZO_MODE_TOM)
408 SCHIZO_PCI_WRITE_8(sc, TOM_PCI_IOC_CSR, TOM_PCI_IOC_PW |
409 (1 << TOM_PCI_IOC_PREF_OFF_SHIFT) | TOM_PCI_IOC_CPRM |
410 TOM_PCI_IOC_CPRO | TOM_PCI_IOC_CPRL);
411

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708 * Set the latency timer register as this isn't always done by the
709 * firmware.
710 */
711 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, STX_CS_DEVICE, STX_CS_FUNC,
712 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
713
714 ofw_bus_setup_iinfo(node, &sc->sc_pci_iinfo, sizeof(ofw_pci_intr_t));
715
700 /*
701 * At least when booting Fire V890 from disk a Schizo comes up with
702 * a PCI bus error residing which triggers as soon as we register
703 * schizo_pci_bus() even when clearing it from all involved registers
704 * beforehand (but is quiet once it has fired). Thus we make PCI bus
705 * errors non-fatal until we actually touch the bus.
706 */
707 sc->sc_flags |= SCHIZO_FLAGS_ARMED;
716#define SCHIZO_SYSCTL_ADD_UINT(name, arg, desc) \
717 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), \
718 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, \
719 (name), CTLFLAG_RD, (arg), 0, (desc))
720
721 SCHIZO_SYSCTL_ADD_UINT("dma_ce", &sc->sc_stats_dma_ce,
722 "DMA correctable errors");
723 SCHIZO_SYSCTL_ADD_UINT("pci_non_fatal", &sc->sc_stats_pci_non_fatal,
724 "PCI bus non-fatal errors");
725
726#undef SCHIZO_SYSCTL_ADD_UINT
727
708 device_add_child(dev, "pci", -1);
709 return (bus_generic_attach(dev));
710}
711
712static void
713schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
714 driver_filter_t handler)
715{

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796 * Interrupt handlers
797 */
798static int
799schizo_pci_bus(void *arg)
800{
801 struct schizo_softc *sc = arg;
802 uint64_t afar, afsr, csr, iommu;
803 uint32_t status;
728 device_add_child(dev, "pci", -1);
729 return (bus_generic_attach(dev));
730}
731
732static void
733schizo_set_intr(struct schizo_softc *sc, u_int index, u_int ino,
734 driver_filter_t handler)
735{

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816 * Interrupt handlers
817 */
818static int
819schizo_pci_bus(void *arg)
820{
821 struct schizo_softc *sc = arg;
822 uint64_t afar, afsr, csr, iommu;
823 uint32_t status;
824 u_int fatal;
804
825
826 fatal = 0;
827
828 mtx_lock_spin(sc->sc_mtx);
829
805 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
806 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
807 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
808 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
809 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
810 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
830 afar = SCHIZO_PCI_READ_8(sc, STX_PCI_AFAR);
831 afsr = SCHIZO_PCI_READ_8(sc, STX_PCI_AFSR);
832 csr = SCHIZO_PCI_READ_8(sc, STX_PCI_CTRL);
833 iommu = SCHIZO_PCI_READ_8(sc, STX_PCI_IOMMU);
834 status = PCIB_READ_CONFIG(sc->sc_dev, sc->sc_pci_secbus,
835 STX_CS_DEVICE, STX_CS_FUNC, PCIR_STATUS, 2);
811 if ((sc->sc_flags & SCHIZO_FLAGS_ARMED) == 0)
812 goto clear_error;
813 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0) {
814 if ((iommu & TOM_PCI_IOMMU_ERR) == 0)
815 goto clear_error;
816
836
817 /* These are non-fatal if target abort was signaled. */
818 if ((status & PCIM_STATUS_STABORT) != 0 &&
819 ((iommu & TOM_PCI_IOMMU_ERRMASK) ==
820 TOM_PCI_IOMMU_INVALID_ERR ||
821 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) != 0 ||
822 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) != 0)) {
823 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
824 goto clear_error;
825 }
826 }
837 /*
838 * IOMMU errors are only fatal on Tomatillo and there also only if
839 * target abort was not signaled.
840 */
841 if ((csr & STX_PCI_CTRL_MMU_ERR) != 0 &&
842 (iommu & TOM_PCI_IOMMU_ERR) != 0 &&
843 ((status & PCIM_STATUS_STABORT) == 0 ||
844 ((iommu & TOM_PCI_IOMMU_ERRMASK) != TOM_PCI_IOMMU_INVALID_ERR &&
845 (iommu & TOM_PCI_IOMMU_ERR_ILLTSBTBW) == 0 &&
846 (iommu & TOM_PCI_IOMMU_ERR_BAD_VA) == 0)))
847 fatal = 1;
848 else if ((status & PCIM_STATUS_STABORT) != 0)
849 fatal = 1;
850 if ((status & (PCIM_STATUS_PERR | PCIM_STATUS_SERR |
851 PCIM_STATUS_RMABORT | PCIM_STATUS_RTABORT |
852 PCIM_STATUS_PERRREPORT)) != 0 ||
853 (csr & (SCZ_PCI_CTRL_BUS_UNUS | TOM_PCI_CTRL_DTO_ERR |
854 STX_PCI_CTRL_TTO_ERR | STX_PCI_CTRL_RTRY_ERR |
855 SCZ_PCI_CTRL_SBH_ERR | STX_PCI_CTRL_SERR)) != 0 ||
856 (afsr & (STX_PCI_AFSR_P_MA | STX_PCI_AFSR_P_TA |
857 STX_PCI_AFSR_P_RTRY | STX_PCI_AFSR_P_PERR | STX_PCI_AFSR_P_TTO |
858 STX_PCI_AFSR_P_UNUS)) != 0)
859 fatal = 1;
860 if (fatal == 0)
861 sc->sc_stats_pci_non_fatal++;
827
862
828 panic("%s: PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
829 "IOMMU %#llx STATUS %#llx", device_get_nameunit(sc->sc_dev),
830 'A' + sc->sc_half, (unsigned long long)afar,
831 (unsigned long long)afsr, (unsigned long long)csr,
832 (unsigned long long)iommu, (unsigned long long)status);
863 device_printf(sc->sc_dev, "PCI bus %c error AFAR %#llx AFSR %#llx "
864 "PCI CSR %#llx IOMMU %#llx STATUS %#llx\n", 'A' + sc->sc_half,
865 (unsigned long long)afar, (unsigned long long)afsr,
866 (unsigned long long)csr, (unsigned long long)iommu,
867 (unsigned long long)status);
833
868
834 clear_error:
835 if (bootverbose)
836 device_printf(sc->sc_dev,
837 "PCI bus %c error AFAR %#llx AFSR %#llx PCI CSR %#llx "
838 "STATUS %#llx", 'A' + sc->sc_half,
839 (unsigned long long)afar, (unsigned long long)afsr,
840 (unsigned long long)csr, (unsigned long long)status);
841 /* Clear the error bits that we caught. */
842 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
843 STX_CS_FUNC, PCIR_STATUS, status, 2);
844 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
845 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
869 /* Clear the error bits that we caught. */
870 PCIB_WRITE_CONFIG(sc->sc_dev, sc->sc_pci_secbus, STX_CS_DEVICE,
871 STX_CS_FUNC, PCIR_STATUS, status, 2);
872 SCHIZO_PCI_WRITE_8(sc, STX_PCI_CTRL, csr);
873 SCHIZO_PCI_WRITE_8(sc, STX_PCI_AFSR, afsr);
874 SCHIZO_PCI_WRITE_8(sc, STX_PCI_IOMMU, iommu);
875
876 mtx_unlock_spin(sc->sc_mtx);
877
878 if (fatal != 0)
879 panic("%s: fatal PCI bus error",
880 device_get_nameunit(sc->sc_dev));
846 return (FILTER_HANDLED);
847}
848
849static int
850schizo_ue(void *arg)
851{
852 struct schizo_softc *sc = arg;
853 uint64_t afar, afsr;
854 int i;
855
881 return (FILTER_HANDLED);
882}
883
884static int
885schizo_ue(void *arg)
886{
887 struct schizo_softc *sc = arg;
888 uint64_t afar, afsr;
889 int i;
890
856 mtx_lock_spin(sc->sc_mtx);
857 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
858 for (i = 0; i < 1000; i++)
859 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
860 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
861 break;
891 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFAR);
892 for (i = 0; i < 1000; i++)
893 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
894 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
895 break;
862 mtx_unlock_spin(sc->sc_mtx);
863 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
864 device_get_nameunit(sc->sc_dev), (unsigned long long)afar,
865 (unsigned long long)afsr);
866 return (FILTER_HANDLED);
867}
868
869static int
870schizo_ce(void *arg)
871{
872 struct schizo_softc *sc = arg;
873 uint64_t afar, afsr;
874 int i;
875
876 mtx_lock_spin(sc->sc_mtx);
896 panic("%s: uncorrectable DMA error AFAR %#llx AFSR %#llx",
897 device_get_nameunit(sc->sc_dev), (unsigned long long)afar,
898 (unsigned long long)afsr);
899 return (FILTER_HANDLED);
900}
901
902static int
903schizo_ce(void *arg)
904{
905 struct schizo_softc *sc = arg;
906 uint64_t afar, afsr;
907 int i;
908
909 mtx_lock_spin(sc->sc_mtx);
910
877 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
878 for (i = 0; i < 1000; i++)
879 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
880 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
881 break;
911 afar = SCHIZO_CTRL_READ_8(sc, STX_CTRL_CE_AFAR);
912 for (i = 0; i < 1000; i++)
913 if (((afsr = SCHIZO_CTRL_READ_8(sc, STX_CTRL_UE_AFSR)) &
914 STX_CTRL_CE_AFSR_ERRPNDG) == 0)
915 break;
916 sc->sc_stats_dma_ce++;
882 device_printf(sc->sc_dev,
883 "correctable DMA error AFAR %#llx AFSR %#llx\n",
884 (unsigned long long)afar, (unsigned long long)afsr);
917 device_printf(sc->sc_dev,
918 "correctable DMA error AFAR %#llx AFSR %#llx\n",
919 (unsigned long long)afar, (unsigned long long)afsr);
920
885 /* Clear the error bits that we caught. */
886 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
921 /* Clear the error bits that we caught. */
922 SCHIZO_CTRL_WRITE_8(sc, STX_CTRL_UE_AFSR, afsr);
923
887 mtx_unlock_spin(sc->sc_mtx);
924 mtx_unlock_spin(sc->sc_mtx);
925
888 return (FILTER_HANDLED);
889}
890
891static int
892schizo_host_bus(void *arg)
893{
894 struct schizo_softc *sc = arg;
895 uint64_t errlog;

--- 587 unchanged lines hidden --- 		926 return (FILTER_HANDLED);
927}
928
929static int
930schizo_host_bus(void *arg)
931{
932 struct schizo_softc *sc = arg;
933 uint64_t errlog;

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