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psycho.c (178840) psycho.c (182020)
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

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26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions

--- 17 unchanged lines hidden (view full) ---

26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 178840 2008-05-07 21:22:15Z marius $");
34__FBSDID("$FreeBSD: head/sys/sparc64/pci/psycho.c 182020 2008-08-22 20:28:19Z marius $");
35
36/*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41#include "opt_ofw_pci.h"
42#include "opt_psycho.h"

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276 const char *dtype;
277
278 dtype = ofw_bus_get_type(dev);
279 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
280 psycho_get_desc(dev) != NULL) {
281 device_set_desc(dev, "U2P UPA-PCI bridge");
282 return (0);
283 }
35
36/*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41#include "opt_ofw_pci.h"
42#include "opt_psycho.h"

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276 const char *dtype;
277
278 dtype = ofw_bus_get_type(dev);
279 if (dtype != NULL && strcmp(dtype, OFW_PCI_TYPE) == 0 &&
280 psycho_get_desc(dev) != NULL) {
281 device_set_desc(dev, "U2P UPA-PCI bridge");
282 return (0);
283 }
284
285 return (ENXIO);
286}
287
288static int
289psycho_attach(device_t dev)
290{
291 char name[sizeof("pci108e,1000")];
292 struct psycho_icarg *pica;

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326 sc->sc_half = 0;
327 break;
328 case PSR_PCICTL1:
329 sc->sc_half = 1;
330 break;
331 default:
332 panic("%s: bogus PCI control register location",
333 __func__);
284 return (ENXIO);
285}
286
287static int
288psycho_attach(device_t dev)
289{
290 char name[sizeof("pci108e,1000")];
291 struct psycho_icarg *pica;

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325 sc->sc_half = 0;
326 break;
327 case PSR_PCICTL1:
328 sc->sc_half = 1;
329 break;
330 default:
331 panic("%s: bogus PCI control register location",
332 __func__);
333 /* NOTREACHED */
334 }
335 } else {
336 rid = 0;
337 sc->sc_pcictl = PSR_PCICTL0;
338 sc->sc_half = 0;
339 }
340 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
341 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |

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646 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
647 PCIM_STATUS_PERRREPORT, 2);
648
649 /*
650 * Set the latency timer register as this isn't always done by the
651 * firmware.
652 */
653 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
334 }
335 } else {
336 rid = 0;
337 sc->sc_pcictl = PSR_PCICTL0;
338 sc->sc_half = 0;
339 }
340 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
341 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |

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646 PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
647 PCIM_STATUS_PERRREPORT, 2);
648
649 /*
650 * Set the latency timer register as this isn't always done by the
651 * firmware.
652 */
653 PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
654 PCIR_LATTIMER, 64, 1);
654 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
655
656 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t))
657 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2(
658 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
659 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
660 PCS_FUNC, n)));
661 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t))
662 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt,

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961 r = shrt;
962 break;
963 case 4:
964 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
965 r = wrd;
966 break;
967 default:
968 panic("%s: bad width", __func__);
655
656 for (n = PCIR_VENDOR; n < PCIR_STATUS; n += sizeof(uint16_t))
657 le16enc(&sc->sc_pci_hpbcfg[n], bus_space_read_2(
658 sc->sc_pci_cfgt, sc->sc_pci_bh[OFW_PCI_CS_CONFIG],
659 PSYCHO_CONF_OFF(sc->sc_pci_secbus, PCS_DEVICE,
660 PCS_FUNC, n)));
661 for (n = PCIR_REVID; n <= PCIR_BIST; n += sizeof(uint8_t))
662 sc->sc_pci_hpbcfg[n] = bus_space_read_1(sc->sc_pci_cfgt,

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961 r = shrt;
962 break;
963 case 4:
964 i = bus_space_peek_4(sc->sc_pci_cfgt, bh, offset, &wrd);
965 r = wrd;
966 break;
967 default:
968 panic("%s: bad width", __func__);
969 /* NOTREACHED */
969 }
970
971 if (i) {
972#ifdef PSYCHO_DEBUG
973 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
974 __func__, bus, slot, func, reg);
975#endif
976 r = -1;

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996 case 2:
997 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
998 break;
999 case 4:
1000 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1001 break;
1002 default:
1003 panic("%s: bad width", __func__);
970 }
971
972 if (i) {
973#ifdef PSYCHO_DEBUG
974 printf("%s: read data error reading: %d.%d.%d: 0x%x\n",
975 __func__, bus, slot, func, reg);
976#endif
977 r = -1;

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997 case 2:
998 bus_space_write_2(sc->sc_pci_cfgt, bh, offset, val);
999 break;
1000 case 4:
1001 bus_space_write_4(sc->sc_pci_cfgt, bh, offset, val);
1002 break;
1003 default:
1004 panic("%s: bad width", __func__);
1005 /* NOTREACHED */
1004 }
1005}
1006
1007static int
1008psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1009{
1010 struct psycho_softc *sc;
1011 struct ofw_pci_register reg;

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1273 break;
1274 case SYS_RES_IOPORT:
1275 rm = &sc->sc_pci_io_rman;
1276 bt = sc->sc_pci_iot;
1277 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1278 break;
1279 default:
1280 return (NULL);
1006 }
1007}
1008
1009static int
1010psycho_route_interrupt(device_t bridge, device_t dev, int pin)
1011{
1012 struct psycho_softc *sc;
1013 struct ofw_pci_register reg;

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1275 break;
1276 case SYS_RES_IOPORT:
1277 rm = &sc->sc_pci_io_rman;
1278 bt = sc->sc_pci_iot;
1279 bh = sc->sc_pci_bh[OFW_PCI_CS_IO];
1280 break;
1281 default:
1282 return (NULL);
1283 /* NOTREACHED */
1281 }
1282
1283 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1284 if (rv == NULL)
1285 return (NULL);
1286 rman_set_rid(rv, *rid);
1287 bh += rman_get_start(rv);
1288 rman_set_bustag(rv, bt);
1289 rman_set_bushandle(rv, bh);
1290
1291 if (needactivate) {
1292 if (bus_activate_resource(child, type, *rid, rv)) {
1293 rman_release_resource(rv);
1294 return (NULL);
1295 }
1296 }
1284 }
1285
1286 rv = rman_reserve_resource(rm, start, end, count, flags, child);
1287 if (rv == NULL)
1288 return (NULL);
1289 rman_set_rid(rv, *rid);
1290 bh += rman_get_start(rv);
1291 rman_set_bustag(rv, bt);
1292 rman_set_bushandle(rv, bh);
1293
1294 if (needactivate) {
1295 if (bus_activate_resource(child, type, *rid, rv)) {
1296 rman_release_resource(rv);
1297 return (NULL);
1298 }
1299 }
1297
1298 return (rv);
1299}
1300
1301static int
1302psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1303 struct resource *r)
1304{
1305 void *p;

--- 84 unchanged lines hidden --- 		1300 return (rv);
1301}
1302
1303static int
1304psycho_activate_resource(device_t bus, device_t child, int type, int rid,
1305 struct resource *r)
1306{
1307 void *p;

--- 84 unchanged lines hidden ---